JP5882326B2 - 傾斜スタックチップパッケージにおける光通信 - Google Patents

傾斜スタックチップパッケージにおける光通信 Download PDF

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Publication number
JP5882326B2
JP5882326B2 JP2013525930A JP2013525930A JP5882326B2 JP 5882326 B2 JP5882326 B2 JP 5882326B2 JP 2013525930 A JP2013525930 A JP 2013525930A JP 2013525930 A JP2013525930 A JP 2013525930A JP 5882326 B2 JP5882326 B2 JP 5882326B2
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semiconductor die
chip package
semiconductor
optical
optical signal
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JP2013536475A (ja
JP2013536475A5 (enExample
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ハラダ,ジョン・エイ
ダグラス,デイビッド・シィ
ドロスト,ロバート・ジェイ
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オラクル・インターナショナル・コーポレイション
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
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    • H01L25/04Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24Coupling light guides
    • G02B6/42Coupling light guides with opto-electronic elements
    • G02B6/43Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
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    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19102Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Optics & Photonics (AREA)
  • Optical Couplings Of Light Guides (AREA)
  • Optical Integrated Circuits (AREA)
JP2013525930A 2010-08-25 2011-08-04 傾斜スタックチップパッケージにおける光通信 Active JP5882326B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/868,577 2010-08-25
US12/868,577 US8290319B2 (en) 2010-08-25 2010-08-25 Optical communication in a ramp-stack chip package
PCT/US2011/046518 WO2012027081A2 (en) 2010-08-25 2011-08-04 Optical communication in a ramp-stack chip package

Publications (3)

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JP2013536475A JP2013536475A (ja) 2013-09-19
JP2013536475A5 JP2013536475A5 (enExample) 2014-09-18
JP5882326B2 true JP5882326B2 (ja) 2016-03-09

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US (1) US8290319B2 (enExample)
EP (1) EP2609623B1 (enExample)
JP (1) JP5882326B2 (enExample)
KR (1) KR101831275B1 (enExample)
CN (1) CN103081102B (enExample)
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Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8373280B2 (en) * 2010-09-01 2013-02-12 Oracle America, Inc. Manufacturing fixture for a ramp-stack chip package using solder for coupling a ramp component
US8283766B2 (en) * 2010-09-02 2012-10-09 Oracle America, Inc Ramp-stack chip package with static bends
US8390109B2 (en) * 2011-02-17 2013-03-05 Oracle America, Inc. Chip package with plank stack of semiconductor dies
US9082632B2 (en) 2012-05-10 2015-07-14 Oracle International Corporation Ramp-stack chip package with variable chip spacing
WO2014003533A1 (en) 2012-06-25 2014-01-03 Intel Corporation Multi-die semiconductor structure with intermediate vertical side chip and semiconductor package for same
US9250403B2 (en) * 2013-04-26 2016-02-02 Oracle International Corporation Hybrid-integrated photonic chip package with an interposer
US10230458B2 (en) 2013-06-10 2019-03-12 Nxp Usa, Inc. Optical die test interface with separate voltages for adjacent electrodes
US9094135B2 (en) 2013-06-10 2015-07-28 Freescale Semiconductor, Inc. Die stack with optical TSVs
US9261556B2 (en) 2013-06-10 2016-02-16 Freescale Semiconductor, Inc. Optical wafer and die probe testing
US9766409B2 (en) 2013-06-10 2017-09-19 Nxp Usa, Inc. Optical redundancy
US9442254B2 (en) 2013-06-10 2016-09-13 Freescale Semiconductor, Inc. Method and apparatus for beam control with optical MEMS beam waveguide
US9810843B2 (en) 2013-06-10 2017-11-07 Nxp Usa, Inc. Optical backplane mirror
US9091820B2 (en) 2013-06-10 2015-07-28 Freescale Semiconductor, Inc. Communication system die stack
US9435952B2 (en) 2013-06-10 2016-09-06 Freescale Semiconductor, Inc. Integration of a MEMS beam with optical waveguide and deflection in two dimensions
US8971676B1 (en) * 2013-10-07 2015-03-03 Oracle International Corporation Hybrid-integrated photonic chip package
US9209165B2 (en) * 2013-10-21 2015-12-08 Oracle International Corporation Technique for controlling positions of stacked dies
CN104730653B (zh) * 2013-12-23 2016-08-31 华为技术有限公司 光互连系统和方法
US9323008B2 (en) 2014-03-25 2016-04-26 Globalfoundries Inc. Optoelectronic structures having multi-level optical waveguides and methods of forming the structures
US9825002B2 (en) * 2015-07-17 2017-11-21 Invensas Corporation Flipped die stack
US9871019B2 (en) 2015-07-17 2018-01-16 Invensas Corporation Flipped die stack assemblies with leadframe interconnects
JP6649076B2 (ja) * 2015-10-26 2020-02-19 京セラ株式会社 光回路基板の製造方法
US9508691B1 (en) 2015-12-16 2016-11-29 Invensas Corporation Flipped die stacks with multiple rows of leadframe interconnects
US10566310B2 (en) 2016-04-11 2020-02-18 Invensas Corporation Microelectronic packages having stacked die and wire bond interconnects
JP6820671B2 (ja) * 2016-06-02 2021-01-27 富士通株式会社 光回路デバイスとこれを用いた光トランシーバ
US9728524B1 (en) 2016-06-30 2017-08-08 Invensas Corporation Enhanced density assembly having microelectronic packages mounted at substantial angle to board
CN107706170A (zh) * 2016-08-09 2018-02-16 晟碟信息科技(上海)有限公司 垂直半导体装置
CN108933109B (zh) * 2017-05-27 2020-07-07 晟碟信息科技(上海)有限公司 成角度的裸芯的半导体器件
US10141259B1 (en) * 2017-12-22 2018-11-27 Micron Technology, Inc. Semiconductor devices having electrically and optically conductive vias, and associated systems and methods
KR102578797B1 (ko) 2018-02-01 2023-09-18 삼성전자주식회사 반도체 패키지
US20190279962A1 (en) * 2018-03-09 2019-09-12 Oracle International Corporation Method and apparatus for stacking warped chips to assemble three-dimensional integrated circuits
US10742217B2 (en) * 2018-04-12 2020-08-11 Apple Inc. Systems and methods for implementing a scalable system
US10600770B2 (en) 2018-05-14 2020-03-24 Micron Technology, Inc. Semiconductor dice assemblies, packages and systems, and methods of operation
US11532574B2 (en) * 2019-03-12 2022-12-20 Intel Coropration Through-substrate waveguide
US12009349B2 (en) * 2021-03-26 2024-06-11 Taiwan Semiconductor Manufacturing Company Limited Vertical semiconductor package including horizontally stacked dies and methods of forming the same
US11894343B2 (en) * 2021-05-24 2024-02-06 Western Digital Technologies, Inc. Vertical semiconductor device with side grooves
US20230247795A1 (en) 2022-01-28 2023-08-03 The Research Foundation For The State University Of New York Regenerative preheater for phase change cooling applications

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3334739B2 (ja) * 1995-08-03 2002-10-15 日本電信電話株式会社 ボード間光インタコネクション装置
US5652811A (en) * 1996-03-06 1997-07-29 The United States Of America As Represented By The Secretary Of The Air Force Semiconductor on fiber optic substrate (SOFOS)
DK174111B1 (da) * 1998-01-26 2002-06-24 Giga As Elektrisk forbindelseselement samt fremgangsmåde til fremstilling af et sådant
TW460927B (en) 1999-01-18 2001-10-21 Toshiba Corp Semiconductor device, mounting method for semiconductor device and manufacturing method for semiconductor device
JP4630409B2 (ja) * 1999-03-18 2011-02-09 富士通株式会社 光電子集積回路装置
JP2001036309A (ja) 1999-07-15 2001-02-09 Nec Eng Ltd マルチチップモジュール接続構造
US6376904B1 (en) 1999-12-23 2002-04-23 Rambus Inc. Redistributed bond pads in stacked integrated circuit die package
US7687400B2 (en) * 2005-06-14 2010-03-30 John Trezza Side stacking apparatus and method
US7215845B1 (en) * 2006-01-20 2007-05-08 Apic Corporation Optical interconnect architecture
US8064739B2 (en) * 2007-10-23 2011-11-22 Hewlett-Packard Development Company, L.P. Three-dimensional die stacks with inter-device and intra-device optical interconnect
KR100997787B1 (ko) 2008-06-30 2010-12-02 주식회사 하이닉스반도체 적층 반도체 패키지 및 이의 제조 방법

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WO2012027081A3 (en) 2012-04-19
CN103081102A (zh) 2013-05-01
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US8290319B2 (en) 2012-10-16
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US20120051695A1 (en) 2012-03-01

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