JP5740048B2 - 高性能ガラスベースの60GHz/MM波フェーズドアレイアンテナおよびその製造方法 - Google Patents
高性能ガラスベースの60GHz/MM波フェーズドアレイアンテナおよびその製造方法 Download PDFInfo
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- JP5740048B2 JP5740048B2 JP2014509326A JP2014509326A JP5740048B2 JP 5740048 B2 JP5740048 B2 JP 5740048B2 JP 2014509326 A JP2014509326 A JP 2014509326A JP 2014509326 A JP2014509326 A JP 2014509326A JP 5740048 B2 JP5740048 B2 JP 5740048B2
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/141—Analog devices
- H01L2924/142—HF devices
- H01L2924/1421—RF devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1433—Application-specific integrated circuit [ASIC]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/14335—Digital signal processor [DSP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49016—Antenna or wave energy "plumbing" making
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Description
Claims (14)
- 複数のエミッタ配線を有する第1の誘電体層と、
前記第1の誘電体層に結合されている第2の誘電体層と
を備え、
前記第1の誘電体層は、前記第2の誘電体層よりも誘電率が高く、
前記第2の誘電体層は、ガラスであり、上面に配設されている複数の平面状アンテナ素子から構成されるアレイを支持しており、
前記第2の誘電体層は、前記複数の平面状アンテナ素子から構成されるアレイに対応する複数のキャビティから構成されるアレイを有し、
前記複数の平面状アンテナ素子はそれぞれ、前記第2の誘電体層において、前記複数のキャビティのうち対応するキャビティと垂直方向において位置合わせされ、
前記複数の平面状アンテナ素子はそれぞれ所与の領域を持ち、前記複数のキャビティのそれぞれのフットプリントは前記複数の平面状のアンテナ素子のうち対応する一の平面状アンテナ素子の領域よりも小さい又は等しい、フェーズドアレイアンテナ基板(PAA基板)。 - 前記複数の平面状アンテナ素子のそれぞれの底面が、前記第2の誘電体層で被覆されている、請求項1に記載のPAA基板。
- 前記複数の平面状アンテナ素子のそれぞれの底面が、前記複数のキャビティのうち対応するキャビティによって露出している、請求項1に記載のPAA基板。
- 前記複数の平面状アンテナ素子はそれぞれ、前記複数のキャビティのうち対応するキャビティの内部に配設されており、前記複数の平面状アンテナ素子のそれぞれの上面が、前記第2の誘電体層で被覆されている、請求項1に記載のPAA基板。
- スルーシリコンビアおよび無線周波数集積回路を有するダイ(TSV RFIC)と、
前記TSV RFICと垂直方向に集積化されているフェーズドアレイアンテナ基板(PAA基板)とを備え、
前記PAA基板は、少なくとも一の配線を支持している第1の誘電体層を有し、
前記PAA基板は、ガラス製の第2の誘電体層上に配設されている複数のアンテナ素子を有し、
前記複数のアンテナ素子はそれぞれ、複数のTSVを介して前記TSV RFICに結合されており、
前記複数のアンテナ素子はそれぞれ、キャビティの上方に配設されており、
前記第2の誘電体層は、少なくとも一のエミッタ配線を支持している第1の誘電体層上に配設され、
前記複数のアンテナ素子はそれぞれ所与の領域を持ち、前記キャビティのフットプリントは前記複数のアンテナ素子のそれぞれの領域よりも小さい又は等しい、装置。 - 前記PAA基板が有する前記複数のアンテナ素子は、前記PAA基板内の誘導結合開口を介して、前記TSV RFICに結合されている、請求項5に記載の装置。
- 前記PAA基板が有する前記複数のアンテナ素子は、前記PAA基板内のビア結合によって、前記TSV RFICに結合されている、請求項5に記載の装置。
- 前記TSV RFICが実装されている第一次実装基板と、
前記PAA基板と前記TSV RFICが実装されている前記第一次実装基板との間に配設される少なくとも一のダミーバンプと
をさらに備え、
前記PAA基板は、前記複数のアンテナ素子および前記TSV RFICに結合されている埋め込み接地面を有している、請求項5から7のいずれか一項に記載の装置。 - スルーシリコンビアデジタルプロセッサダイ(TSV DP)と、
前記TSV DPが実装されている第一次実装基板と、
前記PAA基板と、前記TSV RFICが実装されている前記基板との間に配置されている少なくとも一のダミーバンプと
をさらに備え、
前記TSV DPは、前記TSV RFIC内の少なくとも一のTSVおよび前記TSV DP内の少なくとも一のTSVを介して前記TSV RFICに結合されており、
前記TSV DPおよび前記TSV RFICは前記PAA基板の下方において垂直方向に集積化されており、
前記PAA基板は、前記複数のアンテナ素子および前記TSV RFICに結合されている埋め込み接地面を含む
請求項5から8のいずれか一項に記載の装置。 - スルーシリコンビアメモリダイ(TSVメモリダイ)と、
前記TSVメモリダイが実装されている第一次実装基板と
をさらに備え、
前記TSVメモリダイは、前記TSV RFIC内の少なくとも一のTSVおよび前記TSVメモリダイ内の少なくとも一のTSVを介して前記TSV RFICに結合されており、
前記TSVメモリダイおよび前記TSV RFICは前記PAA基板の下方において垂直方向に集積化されており、
前記第一次実装基板は、前記TSV RFICと共に機能する、内部に埋め込まれている少なくとも一の受動型デバイスを有する
請求項5から8のいずれか一項に記載の装置。 - 垂直方向に集積化されている装置を形成するプロセスであって、
ガラス基板内にキャビティを形成する段階と、
前記キャビティの上方であって前記ガラス基板上にフェーズドアレイアンテナ素子(PAA素子)を形成する段階と、を備え、
前記PAA素子は所与の領域を持ち、前記キャビティのフットプリントは前記PAA素子の領域よりも小さい又は等しい、プロセス。 - 前記PAA素子は、底面が誘電体層で被覆されるように形成される、請求項11に記載のプロセス。
- 前記PAA素子は、前記キャビティによって、底面が露出するように形成される、請求項11に記載のプロセス。
- 前記PAA素子は、前記キャビティの内部に配設されると共に上面が誘電体層で被覆されるように形成される、請求項11に記載のプロセス。
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US13/101,891 | 2011-05-05 | ||
PCT/US2012/035421 WO2012151123A2 (en) | 2011-05-05 | 2012-04-27 | High performance glass-based 60 ghz / mm-wave phased array antennas and methods of making same |
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JP (1) | JP5740048B2 (ja) |
KR (1) | KR101537884B1 (ja) |
CN (1) | CN103782448B (ja) |
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-
2011
- 2011-05-05 US US13/101,891 patent/US8901688B2/en active Active
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2012
- 2012-04-27 EP EP12779473.3A patent/EP2705572B1/en active Active
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- 2012-04-27 JP JP2014509326A patent/JP5740048B2/ja active Active
- 2012-04-27 WO PCT/US2012/035421 patent/WO2012151123A2/en active Application Filing
- 2012-04-27 BR BR112013033613-7A patent/BR112013033613A2/pt not_active IP Right Cessation
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WO2012151123A2 (en) | 2012-11-08 |
KR101537884B1 (ko) | 2015-07-21 |
TW201251198A (en) | 2012-12-16 |
WO2012151123A3 (en) | 2013-01-10 |
WO2012151123A9 (en) | 2013-05-30 |
EP2705572A4 (en) | 2014-11-26 |
TWI557994B (zh) | 2016-11-11 |
US8901688B2 (en) | 2014-12-02 |
CN103782448A (zh) | 2014-05-07 |
KR20140005339A (ko) | 2014-01-14 |
JP2014513493A (ja) | 2014-05-29 |
CN103782448B (zh) | 2017-02-15 |
EP2705572B1 (en) | 2018-11-21 |
BR112013033613A2 (pt) | 2020-08-04 |
EP2705572A2 (en) | 2014-03-12 |
US20120280380A1 (en) | 2012-11-08 |
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