JP5735494B2 - 自己整合ローカル・インターコネクト・プロセスにおけるゲートへの選択的なローカル・インターコネクト - Google Patents
自己整合ローカル・インターコネクト・プロセスにおけるゲートへの選択的なローカル・インターコネクト Download PDFInfo
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- JP5735494B2 JP5735494B2 JP2012514025A JP2012514025A JP5735494B2 JP 5735494 B2 JP5735494 B2 JP 5735494B2 JP 2012514025 A JP2012514025 A JP 2012514025A JP 2012514025 A JP2012514025 A JP 2012514025A JP 5735494 B2 JP5735494 B2 JP 5735494B2
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- 238000000034 method Methods 0.000 title claims description 49
- 239000004020 conductor Substances 0.000 claims description 39
- 239000000758 substrate Substances 0.000 claims description 29
- 239000004065 semiconductor Substances 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 18
- 125000006850 spacer group Chemical group 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000011960 computer-aided design Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 238000013461 design Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 238000011161 development Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 238000000354 decomposition reaction Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000001900 extreme ultraviolet lithography Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000000671 immersion lithography Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000011165 process development Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Memories (AREA)
Description
Claims (14)
- 半導体デバイス生産プロセスであって、
半導体基板上のトランジスタのゲートの上の1つ以上の選択された領域においてハードマスクを選択的に除去することによって、実質的に前記トランジスタの上にある少なくとも1つの絶縁層を通して前記ゲートが上部金属層に接続されるのを可能にすることと、
前記少なくとも1つの絶縁層を通して形成された1つ以上のトレンチ内に導電性材料を堆積することと、を備え、少なくとも1つのトレンチは、前記ゲート上に設けられており、且つ、前記ゲートの2つの側面が前記少なくとも1つのトレンチ内で露出するとともに、前記少なくとも1つのトレンチ内で前記ゲートの底面側の前記半導体基板の少なくとも一部が露出するように、ゲートよりも広く形成されており、前記導電性材料は少なくとも1つの前記選択された領域において前記ゲートへのローカル・インターコネクトを形成する半導体デバイス生産プロセス。 - 前記選択された領域は前記少なくとも1つの絶縁層を通して前記ゲートへ接続するための前記ゲートの上方の所望の位置に位置する領域を備える請求項1のプロセス。
- 前記ハードマスクが除去されなかった領域の上方の前記少なくとも1つの絶縁層を通して形成された少なくとも1つのトレンチ内に前記導電性材料が堆積され、前記ハードマスクは当該トレンチ内での前記導電性材料と前記ゲート間の接続を阻害する請求項1のプロセス。
- 少なくとも1つの追加的な絶縁層を通した少なくとも1つのヴィア・インターコネクトを使用して前記上部金属層へ前記ゲートを接続することをさらに備える請求項1のプロセス。
- 少なくとも1つの前記選択された領域において前記ゲートを囲むスペーサの少なくとも一部を除去することをさらに備える請求項1のプロセス。
- 前記導電性材料の少なくとも一部および前記少なくとも1つの絶縁層を除去して前記基板上にほぼ平坦な表面を形成することをさらに備える請求項1のプロセス。
- 半導体デバイス生産プロセスであって、
ハードマスクを用いて半導体基板上にトランジスタのゲートを形成することと、
前記トランジスタの上にゲート・ハードマスク・エッチング・パターンを配置することと、
前記ゲート・ハードマスク・エッチング・パターンを使用して前記ゲートの上の1つ以上の選択された領域における前記ハードマスクを選択的に除去することと、
前記トランジスタの上に1つ以上の絶縁層を形成することと、
前記ゲートの上の少なくとも1つの前記選択された領域における少なくとも1つの前記絶縁層を通るトレンチを、前記ゲートが前記トレンチ内で露出するように形成し、且つ、前記ゲートの2つの側面が前記トレンチ内で露出するとともに、前記トレンチ内で前記ゲートの底面側の前記半導体基板の少なくとも一部が露出するように、前記ゲートよりも広く形成することと、
前記トレンチ内に導電性材料を堆積することと、を備え、前記導電性材料は少なくとも1つの前記選択された領域における前記ゲートへのローカル・インターコネクトを形成する半導体デバイス生産プロセス。 - 前記1つ以上の絶縁層が2つの絶縁層を備える請求項7のプロセス。
- 前記導電性材料の少なくとも一部と少なくとも1つの前記絶縁層を除去して前記基板上にほぼ平坦な表面を形成することをさらに備える請求項7のプロセス。
- 前記1つ以上の選択された領域において前記ハードマスクを選択的に除去した後に前記ゲート・ハードマスク・エッチング・パターンを除去することをさらに備える請求項7のプロセス。
- 前記ハードマスクが除去されなかった領域の上方の少なくとも1つの前記絶縁層内にに少なくとも1つの追加のトレンチを形成することと、前記少なくとも1つの追加のトレンチに前記導電性材料を堆積することと、をさらに備え、前記ハードマスクは当該トレンチ内での前記導電性材料と前記ゲート間の接続を阻害する請求項7のプロセス。
- 半導体デバイス生産プロセスであって、
ハードマスクを用いて半導体基板上にトランジスタのゲートを形成することと、
前記トランジスタの上に1つ以上の絶縁層を形成することと、
前記ゲートの上の少なくとも1つの選択された領域における少なくとも1つの前記絶縁層を通るトレンチを、前記ゲートと前記ハードマスクが前記トレンチ内で露出するように形成し、且つ、前記ゲートの2つの側面が前記トレンチ内で露出するとともに、前記トレンチ内で前記ゲートの底面側の前記半導体基板の少なくとも一部が露出するように、前記ゲートよりも広く形成することと、
前記トランジスタの上にゲート・ハードマスク・エッチング・パターンを配置することと、
前記ゲート・ハードマスク・エッチング・パターンを使用して前記ゲートの上の前記選択された領域における前記ハードマスクを選択的に除去することと、
前記トレンチ内に導電性材料を堆積することと、を備え、前記導電性材料は少なくとも1つの前記選択された領域における前記ゲートへのローカル・インターコネクトを形成する半導体デバイス生産プロセス。 - 前記導電性材料の少なくとも一部と少なくとも1つの前記絶縁層を除去して前記基板上にほぼ平坦な表面を形成することをさらに備える請求項12のプロセス。
- 前記ハードマスクが除去されなかった領域の上方の少なくとも1つの前記絶縁層内に少なくとも1つの追加のトレンチを形成することと、前記少なくとも1つの追加のトレンチに前記導電性材料を堆積することと、をさらに備え、前記ハードマスクは当該トレンチ内で前記導電性材料と前記ゲート間の接続を阻害する請求項12のプロセス。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/475,796 | 2009-06-01 | ||
US12/475,796 US8563425B2 (en) | 2009-06-01 | 2009-06-01 | Selective local interconnect to gate in a self aligned local interconnect process |
PCT/US2010/036793 WO2010141394A1 (en) | 2009-06-01 | 2010-06-01 | Process for selectively forming a self aligned local interconnect to gate |
Publications (2)
Publication Number | Publication Date |
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JP2012529183A JP2012529183A (ja) | 2012-11-15 |
JP5735494B2 true JP5735494B2 (ja) | 2015-06-17 |
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JP2012514025A Active JP5735494B2 (ja) | 2009-06-01 | 2010-06-01 | 自己整合ローカル・インターコネクト・プロセスにおけるゲートへの選択的なローカル・インターコネクト |
Country Status (6)
Country | Link |
---|---|
US (1) | US8563425B2 (ja) |
JP (1) | JP5735494B2 (ja) |
KR (1) | KR101609329B1 (ja) |
CN (1) | CN102460671B (ja) |
TW (1) | TWI575575B (ja) |
WO (1) | WO2010141394A1 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
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US8532796B2 (en) | 2011-03-31 | 2013-09-10 | Tokyo Electron Limited | Contact processing using multi-input/multi-output (MIMO) models |
US8954913B1 (en) * | 2013-10-01 | 2015-02-10 | Globalfoundries Inc. | Methods of generating circuit layouts that are to be manufactured using SADP routing techniques and virtual non-mandrel mask rules |
US9443851B2 (en) * | 2014-01-03 | 2016-09-13 | Samsung Electronics Co., Ltd. | Semiconductor devices including finFETs and local interconnect layers and methods of fabricating the same |
US9640625B2 (en) | 2014-04-25 | 2017-05-02 | Globalfoundries Inc. | Self-aligned gate contact formation |
US9362001B2 (en) * | 2014-10-14 | 2016-06-07 | Ememory Technology Inc. | Memory cell capable of operating under low voltage conditions |
US9397049B1 (en) | 2015-08-10 | 2016-07-19 | International Business Machines Corporation | Gate tie-down enablement with inner spacer |
US9508818B1 (en) | 2015-11-02 | 2016-11-29 | International Business Machines Corporation | Method and structure for forming gate contact above active area with trench silicide |
US11211330B2 (en) * | 2017-05-01 | 2021-12-28 | Advanced Micro Devices, Inc. | Standard cell layout architectures and drawing styles for 5nm and beyond |
US10586765B2 (en) * | 2017-06-22 | 2020-03-10 | Tokyo Electron Limited | Buried power rails |
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JPS63143845A (ja) * | 1986-12-08 | 1988-06-16 | Hitachi Ltd | 半導体集積回路装置 |
EP0362571A3 (en) * | 1988-10-07 | 1990-11-28 | International Business Machines Corporation | Method for forming semiconductor components |
JP2954223B2 (ja) * | 1988-11-08 | 1999-09-27 | 富士通株式会社 | 半導体装置の製造方法 |
JPH1056080A (ja) * | 1996-08-12 | 1998-02-24 | Fujitsu Ltd | 半導体装置の製造方法 |
JPH10308445A (ja) * | 1997-05-07 | 1998-11-17 | Nec Corp | 半導体装置及びその製造方法 |
JPH11135779A (ja) | 1997-10-28 | 1999-05-21 | Toshiba Corp | 半導体装置及びその製造方法 |
US6214656B1 (en) | 1999-05-17 | 2001-04-10 | Taiwian Semiconductor Manufacturing Company | Partial silicide gate in sac (self-aligned contact) process |
US6274471B1 (en) | 1999-06-04 | 2001-08-14 | Taiwan Semiconductor Manufacturing Company | Method for making high-aspect-ratio contacts on integrated circuits using a borderless pre-opened hard-mask technique |
US6232222B1 (en) | 1999-09-14 | 2001-05-15 | International Business Machines Corporation | Method of eliminating a critical mask using a blockout mask and a resulting semiconductor structure |
KR100331568B1 (ko) | 2000-05-26 | 2002-04-06 | 윤종용 | 반도체 메모리 소자 및 그 제조방법 |
JP3449998B2 (ja) * | 2000-10-05 | 2003-09-22 | 沖電気工業株式会社 | 半導体装置におけるコンタクトホールの形成方法 |
CN1153273C (zh) * | 2001-03-29 | 2004-06-09 | 华邦电子股份有限公司 | 一种具有牺牲型填充柱的自行对准接触方法 |
JP2003031581A (ja) * | 2001-07-12 | 2003-01-31 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
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JP2004241508A (ja) | 2003-02-04 | 2004-08-26 | Matsushita Electric Ind Co Ltd | 半導体素子の製造方法 |
JP2004253730A (ja) * | 2003-02-21 | 2004-09-09 | Renesas Technology Corp | 半導体集積回路装置およびその製造方法 |
TWI242797B (en) * | 2004-06-01 | 2005-11-01 | Nanya Technology Corp | Method for forming self-aligned contact of semiconductor device |
JP2008041835A (ja) | 2006-08-03 | 2008-02-21 | Nec Electronics Corp | 半導体装置とその製造方法 |
-
2009
- 2009-06-01 US US12/475,796 patent/US8563425B2/en active Active
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2010
- 2010-06-01 JP JP2012514025A patent/JP5735494B2/ja active Active
- 2010-06-01 TW TW099117535A patent/TWI575575B/zh active
- 2010-06-01 KR KR1020117031181A patent/KR101609329B1/ko active IP Right Grant
- 2010-06-01 WO PCT/US2010/036793 patent/WO2010141394A1/en active Application Filing
- 2010-06-01 CN CN201080032262.6A patent/CN102460671B/zh active Active
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Publication number | Publication date |
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KR101609329B1 (ko) | 2016-04-05 |
CN102460671A (zh) | 2012-05-16 |
US20100304564A1 (en) | 2010-12-02 |
JP2012529183A (ja) | 2012-11-15 |
US8563425B2 (en) | 2013-10-22 |
WO2010141394A1 (en) | 2010-12-09 |
KR20120018372A (ko) | 2012-03-02 |
TWI575575B (zh) | 2017-03-21 |
TW201108310A (en) | 2011-03-01 |
CN102460671B (zh) | 2014-11-26 |
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