JP5726320B2 - 単一のモデム・ボードにおける改善されたマルチセル・サポートのための方法およびシステム - Google Patents
単一のモデム・ボードにおける改善されたマルチセル・サポートのための方法およびシステム Download PDFInfo
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- JP5726320B2 JP5726320B2 JP2013541997A JP2013541997A JP5726320B2 JP 5726320 B2 JP5726320 B2 JP 5726320B2 JP 2013541997 A JP2013541997 A JP 2013541997A JP 2013541997 A JP2013541997 A JP 2013541997A JP 5726320 B2 JP5726320 B2 JP 5726320B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
- G06F9/546—Message passing systems or structures, e.g. queues
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
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Description
Claims (4)
- モデム・ボードにおいてマルチコア・プロセッサを用いてワイヤレス・ネットワークにおけるデータ・パケットを処理する、コンピュータ実装方法であって、
ポーリング・モードでキュー・マネージャを実行している間、入力データ・パケットのバッファを取得し、フレーム・キューに前記データ・パケットをエンキューするステップであって、前記フレーム・キューは、前記キュー・マネージャによって扱われるべきフレーム記述子のリンクされたリストを含む、ステップと、
キューに入れられたフレーム記述子について、前記キュー・マネージャを定期的にポーリングするためにカーネル・スレッドを使用するステップと、
前記ハードウェア・コンポーネントからN個のフレーム記述子をデキューするステップであって、ここでNは、調整可能なパラメータである、ステップと、
カーネル空間でデキューされた各フレーム記述子に関連するコールバック機能を実行するステップであって、前記コールバック機能は、前記フレーム記述子内のデータ・パケットのバッファ・ポインタを処理のためにバッファ記述子のカーネルからユーザへのマップされたリングにエンキューする、ステップと、
コンテキスト・スイッチなしでメッセージング・モジュールに前記データ・パケットを送るステップと
を含み、前記マルチコア・プロセッサは、データ・プレーン機能を実行するように構成された1つまたは複数のデータ・プレーン・コアと、コントロール・プレーン機能を実行するように構成された1つまたは複数のコントロール・プレーン・コアとを含み、前記方法は、前記データ・プレーン・コアで受信された重要でない割込みを無効にし、
さらに、コントロール・プレーン・コアに前記重要でない割込みをルーティングするステップを含む方法。 - 前記キュー・マネージャは、ハードウェア・コンポーネントを含み、ソフトウェア初期化の間にポーリング・モードで実行するように構成されている請求項1に記載の方法。
- バッファ・マネージャは、前記入力データ・パケットの前記バッファを提供する請求項1に記載の方法。
- 前記マルチコア・プロセッサは、すべての非リアル・タイムのスレッドおよびプロセスが、すべてのコントロール・プレーン活動専用のプロセッサ・コアに結合され、すべてのデータ・プレーン活動専用のプロセッサ・コアは、データ経路の実装またはレイヤ2処理に直接的に必要ないスレッドをホストまたは実行しないように構成されている請求項1に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/955,202 US8861434B2 (en) | 2010-11-29 | 2010-11-29 | Method and system for improved multi-cell support on a single modem board |
US12/955,202 | 2010-11-29 | ||
PCT/US2011/057965 WO2012074632A1 (en) | 2010-11-29 | 2011-10-27 | A method and system for improved multi-cell support on a single modem board |
Publications (2)
Publication Number | Publication Date |
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JP2014506346A JP2014506346A (ja) | 2014-03-13 |
JP5726320B2 true JP5726320B2 (ja) | 2015-05-27 |
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JP2013541997A Expired - Fee Related JP5726320B2 (ja) | 2010-11-29 | 2011-10-27 | 単一のモデム・ボードにおける改善されたマルチセル・サポートのための方法およびシステム |
Country Status (7)
Country | Link |
---|---|
US (1) | US8861434B2 (ja) |
EP (2) | EP2647163B1 (ja) |
JP (1) | JP5726320B2 (ja) |
KR (1) | KR101502808B1 (ja) |
CN (1) | CN103348641B (ja) |
TW (1) | TWI479850B (ja) |
WO (1) | WO2012074632A1 (ja) |
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2010
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- 2011-10-27 JP JP2013541997A patent/JP5726320B2/ja not_active Expired - Fee Related
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JP2014506346A (ja) | 2014-03-13 |
WO2012074632A1 (en) | 2012-06-07 |
EP2647163B1 (en) | 2015-01-14 |
CN103348641B (zh) | 2016-11-23 |
TW201238295A (en) | 2012-09-16 |
US20120134320A1 (en) | 2012-05-31 |
EP2814214B1 (en) | 2018-01-17 |
EP2814214A1 (en) | 2014-12-17 |
US8861434B2 (en) | 2014-10-14 |
KR101502808B1 (ko) | 2015-03-24 |
TWI479850B (zh) | 2015-04-01 |
KR20130099185A (ko) | 2013-09-05 |
CN103348641A (zh) | 2013-10-09 |
EP2647163A1 (en) | 2013-10-09 |
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