JP5714157B1 - Power semiconductor device - Google Patents

Power semiconductor device Download PDF

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Publication number
JP5714157B1
JP5714157B1 JP2014087856A JP2014087856A JP5714157B1 JP 5714157 B1 JP5714157 B1 JP 5714157B1 JP 2014087856 A JP2014087856 A JP 2014087856A JP 2014087856 A JP2014087856 A JP 2014087856A JP 5714157 B1 JP5714157 B1 JP 5714157B1
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Japan
Prior art keywords
power semiconductor
semiconductor device
lead
joint
semiconductor chip
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Application number
JP2014087856A
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Japanese (ja)
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JP2015207675A (en
Inventor
達也 深瀬
達也 深瀬
政紀 加藤
政紀 加藤
友宏 仁科
友宏 仁科
孝信 梶原
孝信 梶原
藤田　暢彦
暢彦 藤田
中島　泰
泰 中島
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2014087856A priority Critical patent/JP5714157B1/en
Priority to DE102014223863.3A priority patent/DE102014223863B4/en
Application granted granted Critical
Publication of JP5714157B1 publication Critical patent/JP5714157B1/en
Publication of JP2015207675A publication Critical patent/JP2015207675A/en
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Abstract

【課題】製造時におけるはんだの這い上がりを抑制可能な技術を提供することを目的とする。【解決手段】パワー半導体装置は、下面がリード１ａの他端側上に接合されたパワー半導体チップ２と、パワー半導体チップ２の上面電極２ａ上に導電性部材３ｂを介して接合された第１接合部４ａと、リード１ｂの他端側上に導電性部材３ｃを介して接合された第２接合部４ｂと、これらを連接する胴体部４ｃとを有するインナーリード４とを備える。第１接合部４ａが胴体部４ｃよりも厚く形成されたことによって、第１接合部４ａの下端が胴体部４ｃの下端よりも下側に位置する。【選択図】図１An object of the present invention is to provide a technique capable of suppressing the creeping of solder during manufacturing. A power semiconductor device includes a power semiconductor chip 2 having a lower surface bonded to the other end of a lead 1a, and a first bonded to an upper surface electrode 2a of the power semiconductor chip 2 via a conductive member 3b. An inner lead 4 having a joint portion 4a, a second joint portion 4b joined to the other end side of the lead 1b via a conductive member 3c, and a body portion 4c connecting these members is provided. Since the first joint portion 4a is formed thicker than the body portion 4c, the lower end of the first joint portion 4a is positioned below the lower end of the body portion 4c. [Selection] Figure 1

Description

本発明は、パワー半導体チップの上面に設けられた上面電極と、リードとをインナーリードで接合するモールド封止型のパワー半導体装置に関する。   The present invention relates to a mold-sealed power semiconductor device in which a top electrode provided on an upper surface of a power semiconductor chip and a lead are joined by an inner lead.

電力変換用のパワー半導体装置は、輸送用機器や生活家電など様々な製品に組み込まれている。また、これまでパワー半導体装置を備えていなかった製品においても、さらなる省電力化や高効率化などの要求から、パワー半導体装置が組み込まれるケースが増加している。これらの製品では、さらなる小型化や耐久性の向上が求められており、当該製品に搭載されるパワー半導体装置にもさらなる小型化、高耐久化などが求められている。パワー半導体装置は、配線パターンを備える基板やリード（リードフレーム）上にパワー半導体チップを導電性部材で接合し、パワー半導体チップ上面の上面電極と、他のリード（端子）とを、ワイヤーボンドや銅板を成形したインナーリードなどの配線部材で接続する構成が一般的である。   Power semiconductor devices for power conversion are incorporated in various products such as transportation equipment and household appliances. In addition, even in products that have not been provided with a power semiconductor device so far, cases where the power semiconductor device is incorporated are increasing due to demands for further power saving and higher efficiency. These products are required to be further reduced in size and improved in durability, and the power semiconductor device mounted on the product is required to be further reduced in size and increased in durability. In a power semiconductor device, a power semiconductor chip is bonded to a substrate or lead (lead frame) having a wiring pattern with a conductive member, and an upper electrode on the upper surface of the power semiconductor chip and another lead (terminal) are connected to each other by wire bonding or A configuration in which a copper plate is connected by a wiring member such as an inner lead is generally used.

パワー半導体装置の構成要素のなかで、パワー半導体装置のサイズや寿命に影響を与えるもののひとつがパワー半導体チップ上の電極に接続される配線部材の形状である。パワー半導体チップは、線膨張係数が小さいＳｉ、ＳｉＣなどの半導体材料からなり、その表面にデバイス構造が形成される。パワー半導体チップの配線部材は、一般に電気電導率が大きい金属材料で構成されており、その線膨張係数は半導体材料と比較して大きい。このため、パワー半導体装置の温度が変化すると、線膨張係数の差から、パワー半導体チップと配線部材の接続部との間に応力が生じる。パワー半導体装置の小型化や高耐久性を実現するためには、この接続部に生じる応力を許容範囲内に抑えると同時に、サイズの小さい配線部材が必要である。そこで、このような課題に対して、過去に様々なパワー半導体装置の配線部材の形状が提案されている。   One of the components of the power semiconductor device that affects the size and life of the power semiconductor device is the shape of the wiring member connected to the electrode on the power semiconductor chip. The power semiconductor chip is made of a semiconductor material such as Si or SiC having a small linear expansion coefficient, and a device structure is formed on the surface thereof. A wiring member of a power semiconductor chip is generally made of a metal material having a high electric conductivity, and its linear expansion coefficient is larger than that of a semiconductor material. For this reason, when the temperature of the power semiconductor device changes, a stress is generated between the power semiconductor chip and the connection portion of the wiring member due to the difference in the coefficient of linear expansion. In order to realize the miniaturization and high durability of the power semiconductor device, it is necessary to suppress the stress generated in the connection portion within an allowable range and at the same time to use a small-sized wiring member. In view of such a problem, various shapes of wiring members of power semiconductor devices have been proposed in the past.

例えば、特許文献１に半導体装置（半導体パッケージ）が示されている。この半導体装置では、パワー半導体チップ上面の電極とリード（端子）とを接続する配線部材に、折り曲げることで成形した銅板を用いる。このような特許文献１の半導体装置によれば、意図しない部分への配線部材の接触による回路故障を抑制することが可能となるとともに、パワー半導体チップとリードとをワイヤーボンドで接続する構成と比較して、配線部材の電気抵抗やインダクタンスを低下させることが可能となる。   For example, Patent Document 1 discloses a semiconductor device (semiconductor package). In this semiconductor device, a copper plate formed by bending is used as a wiring member that connects an electrode on the upper surface of a power semiconductor chip and a lead (terminal). According to such a semiconductor device of Patent Document 1, it becomes possible to suppress a circuit failure due to the contact of the wiring member to an unintended portion and to compare with a configuration in which the power semiconductor chip and the lead are connected by wire bonding. Thus, the electrical resistance and inductance of the wiring member can be reduced.

特許第３２４０２９２号公報Japanese Patent No. 3340292

しかしながら、特許文献１に示された技術では、銅板を曲げて成形している配線部材は、曲げ部において丸みを持つ構成となっている。このような構成において、パワー半導体チップの上面電極と配線部材とを接合する接合部材としてはんだを適用すると、製造時のはんだ溶融時に配線部材（銅板）の丸みを伝って、はんだが這い上がることがある。この場合には、パワー半導体チップと配線部材との間に位置ずれが生じたり、はんだの端部の断面形状であるはんだフィレット形状が、パワー半導体チップ上面に応力集中しやすい形状で凝固してしまったりすることがある。この結果、パワー半導体装置の温度変化や保証期間などが制限されてしまうという問題がある。   However, in the technique disclosed in Patent Document 1, a wiring member formed by bending a copper plate has a configuration in which a bent portion is rounded. In such a configuration, when solder is applied as a joining member for joining the upper surface electrode of the power semiconductor chip and the wiring member, the solder may crawl up through the roundness of the wiring member (copper plate) when the solder melts during manufacturing. is there. In this case, a position shift occurs between the power semiconductor chip and the wiring member, or the solder fillet shape, which is the cross-sectional shape of the end portion of the solder, is solidified in a shape that tends to concentrate stress on the upper surface of the power semiconductor chip. May be frustrated. As a result, there is a problem that the temperature change and guarantee period of the power semiconductor device are limited.

そこで、本発明は、上記のような問題点を鑑みてなされたものであり、製造時におけるはんだの這い上がりを抑制可能な技術を提供することを目的とする。   Therefore, the present invention has been made in view of the above-described problems, and an object thereof is to provide a technique capable of suppressing the creeping of solder during manufacturing.

本発明に係るパワー半導体装置は、一端側が外部端子となる第１及び第２リードと、上面に設けられた上面電極を備え、下面が前記第１リードの他端側上に接合されたパワー半導体チップと、前記上面電極上に第１導電性部材を介して接合された第１接合部と、前記第２リードの他端側上に第２導電性部材を介して接合された第２接合部と、前記第１接合部と前記第２接合部とを連接する胴体部とを有するインナーリードと、前記第１及び第２リードの他端側、前記パワー半導体チップ及び前記インナーリードを覆うモールド樹脂とを備える。前記第１接合部が前記胴体部よりも厚く形成されたことによって、前記第１接合部の下端が前記胴体部の下端よりも下側に位置する。前記パワー半導体チップは、前記上面電極上に円形の開口が設けられた電極保護膜をさらに備え、前記第１接合部の下面の外郭形状は、前記開口の直径より小さい直径を有する円形であり、前記第１接合部は、前記開口内に設けられた前記第１導電性部材を介して前記上面電極と、平面視において前記開口の外周内に接合されている。
A power semiconductor device according to the present invention includes a first and second lead whose one end is an external terminal, and an upper surface electrode provided on the upper surface, and a lower surface bonded to the other end of the first lead. A chip, a first joint joined to the upper surface electrode via a first conductive member, and a second joint joined to the other end of the second lead via a second conductive member And an inner lead having a body portion connecting the first joint portion and the second joint portion, and a mold resin that covers the other end side of the first and second leads, the power semiconductor chip, and the inner lead. With. By forming the first joint portion thicker than the body portion, the lower end of the first joint portion is positioned below the lower end of the body portion. The power semiconductor chip further includes an electrode protection film provided with a circular opening on the upper surface electrode, and the outer shape of the lower surface of the first bonding portion is a circle having a diameter smaller than the diameter of the opening, The first joining portion is joined to the upper surface electrode and the outer periphery of the opening in a plan view via the first conductive member provided in the opening.

本発明によれば、第１接合部が胴体部よりも厚く形成されたことによって、第１接合部の下端が胴体部の下端よりも下側に位置する。これにより、第１接合部の下面の端部の丸みを小さくすることができ、製造時におけるはんだの這い上がりを抑制することができる。   According to the present invention, the lower end of the first joint portion is positioned below the lower end of the body portion because the first joint portion is formed thicker than the body portion. Thereby, the roundness of the edge part of the lower surface of a 1st junction part can be made small, and the creeping of the solder at the time of manufacture can be suppressed.

実施の形態１に係るパワー半導体装置の構成を模式的に示す断面図である。1 is a cross-sectional view schematically showing a configuration of a power semiconductor device according to a first embodiment. 実施の形態１に係るパワー半導体装置の構成を模式的に示す平面図である。1 is a plan view schematically showing a configuration of a power semiconductor device according to a first embodiment. 関連パワー半導体装置の構成を模式的に示す断面図である。It is sectional drawing which shows the structure of a related power semiconductor device typically. 関連パワー半導体装置の構成を模式的に示す拡大断面図である。It is an expanded sectional view showing the composition of a related power semiconductor device typically. 実施の形態１に係るパワー半導体装置の構成を模式的に示す拡大断面図である。1 is an enlarged cross-sectional view schematically showing a configuration of a power semiconductor device according to a first embodiment. 実施の形態２に係るパワー半導体装置の構成を模式的に示す分解斜視図である。FIG. 5 is an exploded perspective view schematically showing a configuration of a power semiconductor device according to a second embodiment. 実施の形態２に係るパワー半導体装置の構成を模式的に示す平面図である。FIG. 6 is a plan view schematically showing a configuration of a power semiconductor device according to a second embodiment. フィレット角度の一例を示す断面図である。It is sectional drawing which shows an example of a fillet angle. 実施の形態２に係るパワー半導体装置の構成を模式的に示す分解平面図である。FIG. 6 is an exploded plan view schematically showing a configuration of a power semiconductor device according to a second embodiment.

＜実施の形態１＞
図１は、本発明の実施の形態１に係るパワー半導体装置の構成を模式的に示す断面図であり、図２は、当該パワー半導体装置の構成を模式的に示す平面図である。 <Embodiment 1>
FIG. 1 is a cross-sectional view schematically showing the configuration of the power semiconductor device according to the first embodiment of the present invention, and FIG. 2 is a plan view schematically showing the configuration of the power semiconductor device.

このパワー半導体装置は、複数のリード１（リード１ａ，１ｂ，１ｃ）と、パワー半導体チップ２と、導電性部材３ａ，３ｂ，３ｃと、インナーリード４と、ワイヤー５（ワイヤー５ａ，５ｂ）と、これらの構成要素を概ね覆うモールド樹脂６とを備えている。なお、パワー半導体チップ２は、図２の上面に設けられた上面電極２ａと、下面に設けられた図示しない下面電極とを備えている。   This power semiconductor device includes a plurality of leads 1 (leads 1a, 1b, 1c), a power semiconductor chip 2, conductive members 3a, 3b, 3c, an inner lead 4, and wires 5 (wires 5a, 5b). , And a mold resin 6 that substantially covers these components. The power semiconductor chip 2 includes an upper surface electrode 2a provided on the upper surface of FIG. 2 and a lower surface electrode (not shown) provided on the lower surface.

＜リード＞
リード（第１リード）１ａ、リード（第２リード）１ｂ、及び、リード（第３リード）の一端側は、モールド樹脂６から露出する外部端子となり、他端側は、モールド樹脂６に覆われる内部端子となる。 <Lead>
One end of the lead (first lead) 1a, the lead (second lead) 1b, and the lead (third lead) is an external terminal exposed from the mold resin 6, and the other end is covered with the mold resin 6. This is an internal terminal.

リード１ａは、導電性部材３ａを介してパワー半導体チップ２の下面電極と電気的に接続されている。リード１ｂは、導電性部材３ｂ，３ｃ及びインナーリード４を介してパワー半導体チップ２の上面電極２ａと電気的に接続されている。リード１ｃについては後述する。   The lead 1a is electrically connected to the lower surface electrode of the power semiconductor chip 2 through the conductive member 3a. The lead 1 b is electrically connected to the upper surface electrode 2 a of the power semiconductor chip 2 through the conductive members 3 b and 3 c and the inner lead 4. The lead 1c will be described later.

リード１ａ，１ｂ，１ｃ（これらを区別しない場合には以下「リード１」と記す）は、金属製であり、例えば、銅やアルミニウムを基材とした合金から形成されている。リード１の表面にて基材の金属が露出していてもよいし、当該表面の少なくとも一部にめっき処理が施されていてもよい。   The leads 1a, 1b, and 1c (hereinafter referred to as “lead 1” when they are not distinguished) are made of metal, and are formed of, for example, an alloy based on copper or aluminum. The metal of the substrate may be exposed on the surface of the lead 1, or at least a part of the surface may be plated.

リード１は、例えば、板状の材料をエッチング加工や、プレス加工などによって配線パターン状に成形された一つのリードフレームを選択的に切断することにより形成される。具体的には、リードフレームの片面に、パワー半導体チップ２、インナーリード４、導電性部材３ａ，３ｂ，３ｃ及びワイヤー５などを分散して搭載し、外部端子を除いてこれらをモールド樹脂６で包み込むように封止する。その後、リードフレームの電気配線上不要な部分が除去されることにより、パワー半導体装置に回路が構成されている。   The lead 1 is formed, for example, by selectively cutting a single lead frame formed into a wiring pattern by etching or pressing a plate-like material. Specifically, the power semiconductor chip 2, the inner lead 4, the conductive members 3a, 3b, 3c, the wires 5 and the like are dispersedly mounted on one side of the lead frame, and these are molded resin 6 except for external terminals. Seal to wrap. Thereafter, unnecessary portions on the electrical wiring of the lead frame are removed, whereby a circuit is configured in the power semiconductor device.

＜パワー半導体チップ、ワイヤー＞
上述したように、パワー半導体チップ２は、図２の上面に設けられた上面電極２ａと、下面に設けられた図示しない下面電極とを備えている。図１に示すように、パワー半導体チップ２の下面（下面電極）は、リード１ａの内部端子（他端側）上に導電性部材３ａを介して接合されることによって、リード１ａと機械的及び電気的に接続されている。パワー半導体チップ２の上面電極２ａは、インナーリード４の下部と導電性部材３ｂを介して接合されることによって、インナーリード４と機械的及び電気的に接続されている。 <Power semiconductor chip, wire>
As described above, the power semiconductor chip 2 includes the upper surface electrode 2a provided on the upper surface of FIG. 2 and the lower surface electrode (not shown) provided on the lower surface. As shown in FIG. 1, the lower surface (lower surface electrode) of the power semiconductor chip 2 is joined to the lead 1a mechanically and electrically by being joined to the internal terminal (other end side) of the lead 1a via a conductive member 3a. Electrically connected. The upper surface electrode 2a of the power semiconductor chip 2 is mechanically and electrically connected to the inner lead 4 by being joined to the lower portion of the inner lead 4 via the conductive member 3b.

パワー半導体チップ２は、オン時にはその厚さ方向に電流を流し、オフ時には当該電流を遮断する。なお、パワー半導体チップ２の材料としては、例えば、Ｓｉのみならず、ＳｉＣ、ＳｉＮ、ＧａＮ、ＧａＡｓなどが用いられてもよい。また、パワー半導体チップ２の上面電極２ａの表面上には、Ｎｉめっき層などのはんだ付けができる層が設けられてもよい。   When the power semiconductor chip 2 is turned on, a current flows in the thickness direction, and when the power semiconductor chip 2 is turned off, the current is cut off. In addition, as a material of the power semiconductor chip 2, not only Si but SiC, SiN, GaN, GaAs, etc. may be used, for example. Further, on the surface of the upper surface electrode 2a of the power semiconductor chip 2, a solderable layer such as a Ni plating layer may be provided.

本実施の形態１では、パワー半導体チップ２は、ＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）であり、かつ、図２に示すように、上面電極２ａとは別に上面に設けられたゲート電極２ｂをさらに含むものとして説明する。しかしこれに限ったものではなく、パワー半導体チップ２は、ＭＯＳＦＥＴの代わりに、ＩＧＢＴ（Insulated Gate Bipolar Transistor）であってもよい。   In the first embodiment, the power semiconductor chip 2 is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and, as shown in FIG. 2, further includes a gate electrode 2b provided on the upper surface separately from the upper surface electrode 2a. It will be described as including. However, the invention is not limited to this, and the power semiconductor chip 2 may be an IGBT (Insulated Gate Bipolar Transistor) instead of the MOSFET.

また本実施の形態１では、パワー半導体チップ２は、上面において温度を検知する図示しない検温ダイオードをさらに含んでいるものとして説明する。これに伴い、図２に示すように、パワー半導体チップ２は、上面電極２ａ及びゲート電極２ｂとは別に上面に設けられた、検温ダイオードの電極２ｃ（以下「検温ダイオード電極２ｃ」と記す）をさらに含むものとする。   In the first embodiment, power semiconductor chip 2 will be described as further including a temperature detection diode (not shown) that detects the temperature on the upper surface. Accordingly, as shown in FIG. 2, the power semiconductor chip 2 includes a temperature detection diode electrode 2c (hereinafter referred to as a "temperature detection diode electrode 2c") provided on the upper surface separately from the upper surface electrode 2a and the gate electrode 2b. In addition.

本実施の形態１のように、ゲート電極２ｂ及び検温ダイオード電極２ｃが、パワー半導体チップ２に搭載される場合には、ゲート端子用のリード１ｃ（図２のリード１ｃ１）と、検温ダイオード端子用のリード１ｃ（図２のリード１ｃ２）とが、パワー半導体装置に備えられる。そして、ゲート電極２ｂとリード１ｃ１とが、ワイヤー５（図２のワイヤー５ａ）のボンディングによって接続され、検温ダイオード電極２ｃとリード１ｃ２とが、ワイヤー５（図２のワイヤー５ｂ）のボンディングによって接続されている。   When the gate electrode 2b and the temperature detection diode electrode 2c are mounted on the power semiconductor chip 2 as in the first embodiment, the gate terminal lead 1c (the lead 1c1 in FIG. 2) and the temperature detection diode terminal The lead 1c (lead 1c2 in FIG. 2) is provided in the power semiconductor device. The gate electrode 2b and the lead 1c1 are connected by bonding of the wire 5 (wire 5a in FIG. 2), and the temperature detecting diode electrode 2c and the lead 1c2 are connected by bonding of the wire 5 (wire 5b in FIG. 2). ing.

なお、本実施の形態１に係るパワー半導体装置は、１個のパワー半導体チップ２を備えているものとして説明するが、これに限ったものではなく、複数個のパワー半導体チップ２を備えてもよい。そして、例えば、１つのパワー半導体装置内の複数個（例えば６個など）のパワー半導体チップ２を組み合せて、インバータ、コンバータ、整流器の回路を構成してもよいし、複数のパワー半導体装置のパワー半導体チップ２を組み合せて、インバータ、コンバータ、整流器の回路を構成してもよい。また、パワー半導体装置内に、コンデンサもしくはシャント抵抗などのチップ部品、または、制御用のＩＣなども搭載してもよい。   Although the power semiconductor device according to the first embodiment is described as including one power semiconductor chip 2, the present invention is not limited to this, and a plurality of power semiconductor chips 2 may be included. Good. For example, a plurality of (for example, six) power semiconductor chips 2 in one power semiconductor device may be combined to form an inverter, converter, rectifier circuit, or the power of the plurality of power semiconductor devices. The semiconductor chip 2 may be combined to form an inverter, converter, and rectifier circuit. Further, a chip component such as a capacitor or a shunt resistor or a control IC may be mounted in the power semiconductor device.

＜導電性部材＞
図１に示されるように、導電性部材３ｂは、パワー半導体チップ２の上面電極２ａとインナーリード４の一端との間に配設される。導電性部材３ｂには、例えばはんだが用いられる。特に、ＭＯＳＦＥＴやＩＧＢＴなどをパワー半導体チップ２に適用する場合には、当該パワー半導体チップ２に必要な機能を持たせるために、複雑な微細構造を有する上面電極２ａが形成される。この微細構造は、外力や変形により生じる応力などに弱く、当該応力などによって微細構造にクラックなどの欠陥が生じると、多くの場合、上記機能が失われる。このため、はんだ材料の硬化後の硬さ、及び、硬化後のはんだ端部の断面形状であるフィレット形状を、上面電極２ａに極力応力が生じないような硬さ及び形状にする必要がある。 <Conductive member>
As shown in FIG. 1, the conductive member 3 b is disposed between the upper surface electrode 2 a of the power semiconductor chip 2 and one end of the inner lead 4. For example, solder is used for the conductive member 3b. In particular, when a MOSFET, IGBT, or the like is applied to the power semiconductor chip 2, the upper surface electrode 2a having a complicated fine structure is formed in order to give the power semiconductor chip 2 the necessary function. This microstructure is weak against stresses caused by external force or deformation, and when the defects such as cracks occur in the microstructure due to the stresses, the above functions are often lost. For this reason, it is necessary to make the hardness after hardening of solder material and the fillet shape which is a cross-sectional shape of the solder end part after hardening into such a hardness and shape that stress is not generated as much as possible in the upper surface electrode 2a.

導電性部材３ａは、リード１ａの内部端子とパワー半導体チップ２の下面電極との間に配設される。導電性部材３ｃは、リード１ｂの内部端子とインナーリード４の他端との間に配設される。導電性部材３ａ，３ｃには、例えばはんだやＡｇ（銀）ペーストなどが用いられる。導電性部材３ａ，３ｃに、導電性部材３ｂと同じはんだを用いた場合には、接合時に全ての導電性部材３ａ，３ｂ，３ｃを同時に接合することができるので、製造時の効率が向上する。もちろん、導電性部材３ａ，３ｃには、導電性部材３ｂと組成が異なるはんだを用いることもできる。この場合、はんだの溶融温度を異ならせることができ、どちらか一方のみを他方より先に溶融するなどが可能となるので、製造時の自由度が向上する。また、導電性部材３ａ，３ｃに、Ａｇペーストを用いてもよく、この場合も、導電性部材３ａ，３ｃに、導電性部材３ｂと組成が異なるはんだを用いた場合と同様の効果が得られる。   The conductive member 3 a is disposed between the internal terminal of the lead 1 a and the lower surface electrode of the power semiconductor chip 2. The conductive member 3 c is disposed between the internal terminal of the lead 1 b and the other end of the inner lead 4. For the conductive members 3a and 3c, for example, solder or Ag (silver) paste is used. When the same solder as that of the conductive member 3b is used for the conductive members 3a and 3c, all the conductive members 3a, 3b and 3c can be bonded simultaneously at the time of bonding, so that the manufacturing efficiency is improved. . Of course, solder having a composition different from that of the conductive member 3b can be used for the conductive members 3a and 3c. In this case, the melting temperature of the solder can be made different, and only one of them can be melted before the other, so that the degree of freedom in manufacturing is improved. Further, Ag paste may be used for the conductive members 3a and 3c. In this case, the same effect as that obtained when solder having a composition different from that of the conductive member 3b is used for the conductive members 3a and 3c can be obtained. .

＜モールド樹脂＞
モールド樹脂６は、リード１ａ，１ｂ，１ｃの内部端子（他端側）、パワー半導体チップ２及びインナーリード４などを覆う。 <Mold resin>
The mold resin 6 covers the internal terminals (the other end side) of the leads 1a, 1b, 1c, the power semiconductor chip 2, the inner leads 4, and the like.

＜インナーリード＞
インナーリード４は、第１接合部４ａと、第２接合部４ｂと、胴体部４ｃとを有している。第１接合部４ａは、上面電極２ａ上に導電性部材（第１導電性部材）３ｂを介して接合されている。第２接合部４ｂは、リード１ｂの内部端子（他端側）上に導電性部材（第２導電性部材）３ｃを介して接合されている。胴体部４ｃは、第１接合部４ａと第２接合部４ｂとを連接する。 <Inner lead>
The inner lead 4 has a first joint portion 4a, a second joint portion 4b, and a body portion 4c. The first joint 4a is joined to the upper surface electrode 2a via a conductive member (first conductive member) 3b. The second joint portion 4b is joined to the internal terminal (the other end side) of the lead 1b via a conductive member (second conductive member) 3c. The body part 4c connects the first joint part 4a and the second joint part 4b.

そして、第１接合部４ａが、胴体部４ｃよりも厚く形成されたことによって、第１接合部４ａの下端が胴体部４ｃの下端よりも下側に位置している。同様に、第２接合部４ｂが、胴体部４ｃよりも厚く形成されたことによって、第２接合部４ｂの下端が胴体部４ｃの下端よりも下側に位置している。つまり、胴体部４ｃは、第１接合部４ａ及び第２接合部４ｂよりもリード１ａから離れている。これにより、リード１ａとインナーリード４とが短絡することが抑制されている。なお、インナーリード４は、切削加工、押出し加工、引抜き加工、鋳造、鍛造、つぶし加工、または、放電加工などの加工で成型される。   And since the 1st junction part 4a was formed thicker than the trunk | drum part 4c, the lower end of the 1st junction part 4a is located below the lower end of the trunk | drum 4c. Similarly, since the second joint portion 4b is formed thicker than the body portion 4c, the lower end of the second joint portion 4b is positioned below the lower end of the body portion 4c. That is, the body part 4c is farther from the lead 1a than the first joint part 4a and the second joint part 4b. Thereby, it is suppressed that the lead 1a and the inner lead 4 are short-circuited. The inner lead 4 is formed by a process such as cutting, extruding, drawing, casting, forging, crushing, or electric discharge.

胴体部４ｃの断面積は、通電する電流の量によって決められる。本実施の形態１では、瞬間的に流れる電流まで含めると数Ａから数百Ａ程度まで通電するパワー半導体装置を想定しており、断面積１ｍｍ２以上に設定することが好ましい。本実施の形態１では、このことを考慮して、胴体部４ｃの断面積は約１．５ｍｍとし、板厚は約０．５ｍｍとしている。 The cross-sectional area of the body portion 4c is determined by the amount of current to be energized. In the first embodiment, a power semiconductor device that energizes from several A to several hundred A when including even a current that flows instantaneously is assumed, and the cross-sectional area is preferably set to 1 mm 2 or more. In the first embodiment, considering this, the cross-sectional area of the body portion 4c is about 1.5 mm, and the plate thickness is about 0.5 mm.

また、本実施の形態１では、インナーリード４の導電性部材３ｂ，３ｃにより接合される部分以外は、モールド樹脂６に接して内包されるように設けられており、インナーリードは、製造時に外部から支えられずに、パワー半導体チップ２及びリード１ｂ上に搭載される。   Further, in the first embodiment, the portions other than the portion joined by the conductive members 3b and 3c of the inner lead 4 are provided so as to be included in contact with the mold resin 6, and the inner lead is externally provided at the time of manufacture. It is mounted on the power semiconductor chip 2 and the lead 1b without being supported from the above.

＜関連パワー半導体装置＞
図３は、本実施の形態１に係るパワー半導体装置に関連するパワー半導体装置（以下「関連パワー半導体装置」と記す）の構成を図１と同様に示す断面図であり、図４は、図３の一点鎖線の四角形で囲まれた部分を拡大した断面図である。ただし、図４においては便宜上、モールド樹脂６の図示は省略している。 <Related power semiconductor devices>
3 is a cross-sectional view showing the configuration of a power semiconductor device related to the power semiconductor device according to the first embodiment (hereinafter referred to as “related power semiconductor device”) in the same manner as FIG. 1, and FIG. 3 is an enlarged cross-sectional view of a portion surrounded by a one-dot chain line quadrilateral. However, in FIG. 4, illustration of the mold resin 6 is omitted for convenience.

以下、関連パワー半導体装置において、以上で説明した構成要素と同一のものについては同じ参照符号を付して、関連パワー半導体装置のうち上述の構成要素と異なる構成要素と問題点とについて説明する。   Hereinafter, in the related power semiconductor device, the same components as those described above are denoted by the same reference numerals, and components and problems different from the above-described components in the related power semiconductor device will be described.

図３に示すように、関連パワー半導体装置は、上述のインナーリード４に対応するインナーリード４１を備えており、当該インナーリード４１が、一枚の板材を曲げたような形状を有している。このため、図４に示されるように、インナーリード４１の上面電極２ａと接合される接合面（下面）の端部４１ａは、断面視にて丸みを持った曲げ部となる。この丸みの半径は、曲げ加工の原理から、一般的にインナーリード４１の厚さと同程度となる。   As shown in FIG. 3, the related power semiconductor device includes an inner lead 41 corresponding to the inner lead 4 described above, and the inner lead 41 has a shape obtained by bending a single plate material. . For this reason, as shown in FIG. 4, the end 41a of the joint surface (lower surface) joined to the upper surface electrode 2a of the inner lead 41 is a bent portion having a roundness in a sectional view. The radius of this roundness is generally the same as the thickness of the inner lead 41 from the principle of bending.

このように端部４１ａが丸みを持つ場合には、製造工程における導電性部材３ｂのはんだ溶融時に、はんだが端部４１ａを伝って、インナーリード４１の胴体部の下面４１ｂに向かって這い上がり、はんだのフィレット３ｂ１が、パワー半導体チップ２の上面に応力集中しやすい形状で凝固することがある。具体的には、フィレット３ｂ１の主たる線状部分が、パワー半導体チップ２の上面と、断面視にて楔形状を成した状態で固定されることがある。   When the end portion 41a is round as described above, when the solder of the conductive member 3b is melted in the manufacturing process, the solder crawls up to the lower surface 41b of the body portion of the inner lead 41 through the end portion 41a. The solder fillet 3b1 may solidify in a shape that tends to concentrate stress on the upper surface of the power semiconductor chip 2. Specifically, the main linear portion of the fillet 3b1 may be fixed to the upper surface of the power semiconductor chip 2 in a wedge shape in a sectional view.

この状態で、パワー半導体チップ２下方のリード１ａが搬送や温度変化などによって反った場合には、上記楔形状の先端に隣接するパワー半導体チップ２の上面が、フィレット３ｂ１を介して、インナーリード４１を引き剥がす方向に押すような応力が生じることがある。この際、反作用として、パワー半導体チップ２の上面に応力が集中することになり、パワー半導体チップ２の上面に形成されていた上面電極２ａの微細構造などが破損するリスクがある。関連パワー半導体装置では、このような応力による不良を抑制するために、搬送、温度変化、保証期間などに制限が生じていた。また、はんだが這い上がると、溶融時のはんだの表面張力のバランスが悪くなり、パワー半導体チップ２とインナーリード４１との間に位置ずれが生じる場合がある。   In this state, when the lead 1a below the power semiconductor chip 2 warps due to conveyance or temperature change, the upper surface of the power semiconductor chip 2 adjacent to the wedge-shaped tip is connected to the inner lead 41 via the fillet 3b1. Stress that pushes in the direction of peeling off may occur. At this time, as a reaction, stress concentrates on the upper surface of the power semiconductor chip 2, and there is a risk that the fine structure of the upper surface electrode 2 a formed on the upper surface of the power semiconductor chip 2 is damaged. In related power semiconductor devices, in order to suppress defects due to such stress, there are limitations on transportation, temperature change, warranty period, and the like. Moreover, when the solder creeps up, the balance of the surface tension of the solder at the time of melting is deteriorated, and there may be a displacement between the power semiconductor chip 2 and the inner lead 41.

しかも、パワー半導体装置に通電する電流が大きくなることに従って、インナーリード４１の厚さが大きくなるように設計される傾向にあるため、インナーリード４１の端部４１ａの丸み半径は増加し、さらにはんだが這い上がりやすくなってきている。また、厚さが増すと、曲げ加工の加工精度は低下するため、インナーリード４１の形状ばらつきも大きくなり、製造時の管理コストが増大する。また、曲げ加工により成型する場合には、加工方法の制約から屈曲部（端部４１ａ）の起点は直線状に並んでいる必要があり、上面電極２ａやリード１ｂと接合する面の形状が制限される。この結果、パワー半導体チップ２の上面の耐久性が低下し、機能が制限される原因となる。また、パワー半導体チップ２の温度上昇を抑えるためには、パワー半導体チップ２の近傍にできるだけヒートマスの機能を有する部材（熱量量の大きい部材）を設けることが好ましい。しかしながら、図２の構造では、上述のような制約やパワー半導体装置のサイズに起因する制約から、インナーリード４１を厚くすることが困難であり、ヒートマスの機能を有する部材を設けることが難しい。   Moreover, since the thickness of the inner lead 41 tends to increase as the current flowing to the power semiconductor device increases, the round radius of the end portion 41a of the inner lead 41 increases, and the solder Is becoming easier to crawl up. Further, as the thickness increases, the processing accuracy of the bending process decreases, so that the shape variation of the inner lead 41 also increases, and the management cost during manufacturing increases. Further, when forming by bending, the starting point of the bent portion (end portion 41a) needs to be arranged in a straight line due to limitations of the processing method, and the shape of the surface to be joined to the upper surface electrode 2a or the lead 1b is limited. Is done. As a result, the durability of the upper surface of the power semiconductor chip 2 is lowered, which causes the function to be limited. In order to suppress the temperature rise of the power semiconductor chip 2, it is preferable to provide a member having a heat mass function (a member having a large amount of heat) as close as possible to the power semiconductor chip 2. However, in the structure of FIG. 2, it is difficult to increase the thickness of the inner leads 41 due to the above-described restrictions and restrictions due to the size of the power semiconductor device, and it is difficult to provide a member having a heat mass function.

＜実施の形態１に係るパワー半導体装置の効果＞
これに対して、図１に示す本実施の形態１に係るインナーリード４では、曲げ加工を行わずに下面に段差が形成されている。すなわち、インナーリード４において、第１接合部４ａが、胴体部４ｃよりも厚く形成されたことによって、第１接合部４ａの下端が胴体部４ｃの下端よりも下側に位置している。このような構成によれば、インナーリード４の上面電極２ａと接合される接合面の端部の丸みを、図３の曲げ加工で成形したインナーリード４１の端部４１ａよりも小さくすることができる。例えば、図３のインナーリード４１の端部の丸み半径は、インナーリード４１の厚さ程度であるのに対して、本実施の形態１に係るインナーリード４の端部の丸み半径は、胴体部４ｃの厚さの２０％以下に低減することができる。 <Effect of Power Semiconductor Device According to First Embodiment>
On the other hand, in the inner lead 4 according to the first embodiment shown in FIG. 1, a step is formed on the lower surface without bending. That is, in the inner lead 4, the first joint portion 4a is formed thicker than the body portion 4c, so that the lower end of the first joint portion 4a is located below the lower end of the body portion 4c. According to such a configuration, the roundness of the end portion of the joint surface joined to the upper surface electrode 2a of the inner lead 4 can be made smaller than the end portion 41a of the inner lead 41 formed by the bending process of FIG. . For example, the radius of roundness at the end of the inner lead 41 in FIG. 3 is about the thickness of the inner lead 41, whereas the radius of roundness at the end of the inner lead 4 according to the first embodiment is the body portion. It can be reduced to 20% or less of the thickness of 4c.

したがって、本実施の形態１に係るパワー半導体装置によれば、製造工程における導電性部材３ｂのはんだ溶融時に、はんだがインナーリード４を這い上がることを抑制することができ、これに伴いはんだのフィレット形状の悪化を抑制することができる。これにより、温度変化などでリード１ａが反ることに起因して生じていた、パワー半導体チップ２の上面への応力集中を抑制することができる。また、はんだの這い上がりが抑制されることに伴い、はんだ溶融時のはんだの表面張力のバランスを保つことができるので、パワー半導体チップ２とインナーリード４との間の位置ずれを低減することができる。これらの結果として、耐久性の低下を抑制することが可能となり、パワー半導体装置の機能が制限されることを回避できる。   Therefore, according to the power semiconductor device according to the first embodiment, it is possible to prevent the solder from scooping up the inner lead 4 when the conductive member 3b is melted in the manufacturing process. Deterioration of the shape can be suppressed. Thereby, it is possible to suppress stress concentration on the upper surface of the power semiconductor chip 2 caused by the warping of the lead 1a due to a temperature change or the like. In addition, since the solder creeping is suppressed, the balance of the surface tension of the solder at the time of melting the solder can be maintained, so that the positional deviation between the power semiconductor chip 2 and the inner lead 4 can be reduced. it can. As a result of these, it becomes possible to suppress a decrease in durability, and it is possible to avoid limiting the function of the power semiconductor device.

また、本実施の形態１では、インナーリード４において、第１接合部４ａが、胴体部４ｃよりも厚く形成されているので、第１接合部４ａに、ヒートマスの機能を持たせることができる。これにより、パワー半導体チップ２の温度が上昇するために必要な熱量が大きくなるため、同じ熱量下では、パワー半導体チップ２の温度上昇量を小さくすることができる。したがって、例えば瞬時に大電流を通電する時の、パワー半導体チップ２の温度上昇を小さくすることができる。これに伴い、パワー半導体チップ２のサイズの縮小が可能となり、ひいては、パワー半導体装置の通電抵抗及びコストの低減も可能となる。   In the first embodiment, in the inner lead 4, the first joint portion 4a is formed thicker than the body portion 4c. Therefore, the first joint portion 4a can have a heat mass function. As a result, the amount of heat necessary for the temperature of the power semiconductor chip 2 to rise increases, so that the amount of temperature rise of the power semiconductor chip 2 can be reduced under the same amount of heat. Therefore, for example, the temperature rise of the power semiconductor chip 2 when a large current is passed instantaneously can be reduced. As a result, the size of the power semiconductor chip 2 can be reduced, and as a result, the energization resistance and cost of the power semiconductor device can be reduced.

また、本実施の形態１では、インナーリード４は、モールド樹脂６に内包されている。これにより、モールド樹脂６の成形時には、リード１のみが金型に接するようになるため、型締めによる外力がインナーリード４に直接伝わらないようにすることができる。そして、インナーリード４とパワー半導体チップ２とを接合する導電性部材３ｂなどにおいて応力が集中することを抑制することができ、当該応力に起因する不良を抑制することができる。この結果、製造時の歩留まりを向上することができる。   In the first embodiment, the inner lead 4 is included in the mold resin 6. As a result, only the lead 1 comes into contact with the mold when the mold resin 6 is molded, so that an external force due to mold clamping can be prevented from being directly transmitted to the inner lead 4. And it can suppress that stress concentrates in the electroconductive member 3b etc. which join the inner lead 4 and the power semiconductor chip 2, and the defect resulting from the said stress can be suppressed. As a result, the manufacturing yield can be improved.

＜その他＞
以下、本実施の形態１に係るその他の構成及び効果などについて説明する。 <Others>
Hereinafter, other configurations and effects according to the first embodiment will be described.

本実施の形態１では、リード１ａ，１ｂは、一平面上に配置されている。このような構成によれば、リード１ａ，１ｂに段差形状、厚さが部分的に異なる異厚形状、または、突起形状を設けなくて済むので、リード１ａ，１ｂのコストの増大を防ぐことができる。また、モールド樹脂６の成形時に金型内へ樹脂が流れ込む際に、当該樹脂の流動性が悪化するのを抑制することができる。また、仮に、リード１ａ，１ｂが異なる平面に配置されると、モールド成形時の型締め圧力や、流入する樹脂の圧力により、リード１ａ，１ｂの間に接続されたインナーリード４やそれを接続する導電性部材３ｂ，３ｃに応力が生じる。しかし、本実施の形態１では、リード１ａ，１ｂを一平面上に配置しているので、当該応力を抑制することができる。なお、上記の観点から、リード１ｃも同様に、リード１ａ，１ｂと一平面上に配置されることが好ましい。   In the first embodiment, the leads 1a and 1b are arranged on one plane. According to such a configuration, the leads 1a and 1b do not need to be provided with a stepped shape, a different thickness shape having a partially different thickness, or a protrusion shape, thereby preventing an increase in the cost of the leads 1a and 1b. it can. Moreover, when resin flows into a metal mold | die at the time of shaping | molding of mold resin 6, it can suppress that the fluidity | liquidity of the said resin deteriorates. Further, if the leads 1a and 1b are arranged on different planes, the inner lead 4 connected between the leads 1a and 1b and the inner lead 4 are connected by the clamping pressure at the time of molding and the pressure of the inflowing resin. Stress is generated in the conductive members 3b and 3c. However, in the first embodiment, since the leads 1a and 1b are arranged on one plane, the stress can be suppressed. From the above viewpoint, it is preferable that the lead 1c is also arranged on the same plane as the leads 1a and 1b.

また、本実施の形態１では、インナーリード４は、一つの導電性板材に、その幅方向（断面方向）の片側からつぶし加工を行うことによって形成されている。これにより、所望の断面積または厚さ（例えばパワー半導体装置に流す電流に応じた必要最低限の断面積または厚さ）を有する胴体部４ｃを容易に実現することができるとともに、所望の断面積（例えばヒートマスの機能が十分得られる断面積）を有する第１接合部４ａを容易に実現することができる。また、曲げ加工で形成したインナーリード４１を搭載する関連パワー半導体装置よりも薄いパワー半導体装置の実現も期待できる。ただし、つぶし加工に限ったものではなく、上述したように、切削加工、押出し加工、引抜き加工、鋳造、鍛造または放電加工などによって、インナーリード４は形成されてもよい。また、インナーリード４の材料には、例えば銅合金やアルミニウム合金などが用いられる。   In the first embodiment, the inner lead 4 is formed by crushing one conductive plate material from one side in the width direction (cross-sectional direction). Thus, the body portion 4c having a desired cross-sectional area or thickness (for example, a minimum necessary cross-sectional area or thickness corresponding to a current flowing through the power semiconductor device) can be easily realized, and a desired cross-sectional area can be realized. The first joint portion 4a having (for example, a cross-sectional area that can sufficiently obtain the function of the heat mass) can be easily realized. In addition, a power semiconductor device that is thinner than the related power semiconductor device on which the inner lead 41 formed by bending is mounted can be expected. However, the inner lead 4 may be formed by cutting, extruding, drawing, casting, forging, or electric discharge machining as described above. For example, a copper alloy or an aluminum alloy is used as the material of the inner lead 4.

また、本実施の形態１では、インナーリード４の接合に関与しない面である上面（つぶし加工が行われた片側と逆側の面）は平坦化されている。これにより、製造時の部品実装時にパワー半導体チップ２や、他のチップ部品と同様に、真空吸着による取扱いが可能となり、マウンターなどにより、インナーリード４をパワー半導体チップ２及びリード１ｂ上に搭載することが可能となる。これにより、既存の工程を、インナーリード４を搭載する工程に流用することができるので、製造コストを低減することができる。また、製造ラインなどで、新たにインナーリード４の搭載用の機械を設けなくて済むので、機械購入費用や製造エリアの増大を抑制することができる。   Further, in the first embodiment, the upper surface (the surface on the opposite side to the one subjected to the crushing process) that is a surface not involved in the joining of the inner leads 4 is flattened. As a result, it becomes possible to handle by vacuum suction like the power semiconductor chip 2 and other chip parts at the time of component mounting at the time of manufacture, and the inner lead 4 is mounted on the power semiconductor chip 2 and the lead 1b by a mounter or the like. It becomes possible. Thereby, since an existing process can be diverted to the process of mounting the inner lead 4, the manufacturing cost can be reduced. In addition, since it is not necessary to newly provide a machine for mounting the inner leads 4 on the production line or the like, it is possible to suppress an increase in machine purchase costs and a production area.

また、本実施の形態１では、第１接合部４ａが、胴体部４ｃよりも厚く形成されたことによって、第１接合部４ａの下端が胴体部４ｃの下端よりも下側に位置しているだけでなく、第２接合部４ｂを第１接合部４ａよりも厚く形成することによって、第２接合部４ｂの下端が第１接合部４ａの下端よりも下側に位置している。これにより、インナーリード４を介して上面電極２ａとリード１ａとが短絡することを抑制することができる。また、パワー半導体チップ２の外周に設けられた、素子耐圧を保つ機能を有するガードリング部（図示せず）にインナーリード４が接触して、耐圧不良になることを抑制することができる。   In the first embodiment, the first joint 4a is formed thicker than the body 4c, so that the lower end of the first joint 4a is positioned below the lower end of the body 4c. In addition, by forming the second joint 4b thicker than the first joint 4a, the lower end of the second joint 4b is located below the lower end of the first joint 4a. Thereby, it is possible to prevent the upper surface electrode 2 a and the lead 1 a from being short-circuited via the inner lead 4. In addition, it is possible to prevent the inner lead 4 from coming into contact with a guard ring portion (not shown) provided on the outer periphery of the power semiconductor chip 2 and having a function of maintaining the element breakdown voltage, resulting in a breakdown voltage failure.

また、本実施の形態１では、導電性部材３ａ、パワー半導体チップ２、導電性部材３ｂ及び第１接合部４ａの厚さの合計と、導電性部材３ｃ及び第２接合部４ｂの厚さの合計とが同じ程度としている。これにより、インナーリード４の上面と、リード１ａ，１ｂが配置された一平面とが略平行に配設されている。例えば、厚さの合計同士の差が５００μｍ以内であれば、モールド樹脂６の成形時に、樹脂の流動性が低下するのを抑制することができる。また、インナーリード４を実装する際に、マウンターによって、インナーリード４を吸着してから、インナーリード４の上面を水平方向に平行にしたまま、インナーリード４を搭載位置に運んで搭載位置に載置することができる。この結果として、インナーリード４の位置ずれを小さくすることができる。   Further, in the first embodiment, the total thickness of the conductive member 3a, the power semiconductor chip 2, the conductive member 3b, and the first joint portion 4a, and the thickness of the conductive member 3c and the second joint portion 4b. The total is about the same. Thereby, the upper surface of the inner lead 4 and the one plane on which the leads 1a and 1b are arranged are arranged substantially in parallel. For example, when the difference between the total thicknesses is 500 μm or less, it is possible to prevent the fluidity of the resin from being lowered when the mold resin 6 is molded. Further, when the inner lead 4 is mounted, the inner lead 4 is sucked by the mounter, and then the inner lead 4 is carried to the mounting position while the upper surface of the inner lead 4 is kept parallel to the horizontal direction. Can be placed. As a result, the positional deviation of the inner lead 4 can be reduced.

図５は、図１の一点鎖線の四角形で囲まれた部分を拡大した断面図である。ただし、図５においては、便宜上、モールド樹脂６の図示は省略している。   FIG. 5 is an enlarged cross-sectional view of a portion surrounded by a dashed-dotted line in FIG. However, in FIG. 5, illustration of the mold resin 6 is omitted for convenience.

本実施の形態１では、図５に示すように、第１接合部４ａの胴体部４ｃ側の側面と、第１接合部４ａの下面とがなす角度の補角をθとした場合に、６０°≦θ≦９０°の関係が満たされている。これにより、はんだの這い上がりを可及的に抑制することができる。例えば、第１接合部４ａと胴体部４ｃとの厚さの差が小さく、第１接合部４ａの下面と、胴体部４ｃの下面との間の距離が小さい場合（例えば当該距離が２００μｍである場合）であっても、角度θをほぼ９０°にすることで、はんだの這い上がりを抑制することができる。   In the first embodiment, as shown in FIG. 5, when the complementary angle of the angle formed between the side surface of the first joint portion 4 a on the body portion 4 c side and the lower surface of the first joint portion 4 a is θ, The relationship of ° ≦ θ ≦ 90 ° is satisfied. Thereby, the creeping of the solder can be suppressed as much as possible. For example, when the difference in thickness between the first joint portion 4a and the body portion 4c is small and the distance between the lower surface of the first joint portion 4a and the lower surface of the body portion 4c is small (for example, the distance is 200 μm). Even in this case, the creeping of the solder can be suppressed by setting the angle θ to approximately 90 °.

また、本実施の形態１では、図１及び図２に示すように、ゲート電極２ｂとリード１ｃ１とが、ワイヤー５ａのボンディングによって接続されている。ここで、仮にパワー半導体チップ２においてはんだ付けの箇所が複数個ある場合には、はんだ溶融時に複数の箇所で引張り力が生じ、位置ずれの原因になる。これに対して、本実施の形態１では、ゲート電極２ｂをはんだ付けではなく、ワイヤーボンドを用いて接続するので、はんだ付けの箇所を減らすことができ、結果として位置ずれを抑制することができる。また、同様に本実施の形態１では、検温ダイオード電極２ｃとリード１ｃ２とが、ワイヤー５ｂのボンディングによって接続されている。これにより、上述と同様の効果を得ることができる。   In the first embodiment, as shown in FIGS. 1 and 2, the gate electrode 2b and the lead 1c1 are connected by bonding of the wire 5a. Here, if there are a plurality of locations to be soldered in the power semiconductor chip 2, tensile forces are generated at the plurality of locations when the solder is melted, which causes positional displacement. On the other hand, in this Embodiment 1, since the gate electrode 2b is connected not by soldering but by wire bonding, the number of soldering locations can be reduced, and consequently displacement can be suppressed. . Similarly, in the first embodiment, the temperature detection diode electrode 2c and the lead 1c2 are connected by bonding of the wire 5b. Thereby, the effect similar to the above can be acquired.

また、本実施の形態１では、図２に示すように、平面視において第１接合部４ａの中央部を貫通する貫通穴４ａ１が、第１接合部４ａに設けられている。この貫通穴４ａ１は、厚さ方向、つまり図１の上下方向に沿って設けられている。このように設けられた貫通穴４ａ１によれば、製造時の溶融中のはんだ（導電性部材３ｂ）を適宜吸い上げることが可能となる。このため、溶融中のはんだの量が多い場合において、インナーリード４を当該はんだ上に載置しても、貫通穴４ａ１の吸い上げにより、余剰のはんだが第１接合部４ａの下面端部に向かうことを抑制することができ、はんだの這い上がりをさらに抑制することができる。なお、貫通穴４ａ１がはんだで完全に満たされないように、はんだの量を調整した場合には、貫通穴４ａ１の残余の部分にモールド樹脂６を充填することができる。これにより、インナーリード４とモールド樹脂６との密着性をより強固にすることができる。この結果、インナーリード４及びその周りの構成部材がモールド樹脂６に強固に固定されるので、例えば、使用環境温度が厳しい場合、または、通電する電流値が大きい場合に対する耐久性をさらに向上させることができる。   Further, in the first embodiment, as shown in FIG. 2, a through hole 4a1 penetrating the central portion of the first joint portion 4a in the plan view is provided in the first joint portion 4a. The through hole 4a1 is provided along the thickness direction, that is, the vertical direction in FIG. According to the through hole 4a1 provided in this way, it is possible to appropriately suck up the molten solder (conductive member 3b) at the time of manufacture. For this reason, when the amount of solder being melted is large, even if the inner lead 4 is placed on the solder, surplus solder moves toward the lower surface end portion of the first joint portion 4a by sucking up the through hole 4a1. This can be suppressed, and solder creeping can be further suppressed. When the amount of solder is adjusted so that the through hole 4a1 is not completely filled with solder, the remaining portion of the through hole 4a1 can be filled with the mold resin 6. Thereby, the adhesiveness between the inner lead 4 and the mold resin 6 can be further strengthened. As a result, the inner lead 4 and the constituent members around the inner lead 4 are firmly fixed to the mold resin 6, so that the durability against, for example, a severe operating environment temperature or a large current value to be energized can be further improved. Can do.

また、本実施の形態１では、図２に示すように、貫通穴４ａ１の有無などの点で、平面視において第１接合部４ａの形状と第２接合部４ｂの形状とが異なる。これにより、パワー半導体装置の製造時における、インナーリード４の実装工程において、インナーリード４の向き間違いを抑制することができる。この結果、製造時の歩留まりを向上させることができる。   Moreover, in this Embodiment 1, as shown in FIG. 2, the shape of the 1st junction part 4a differs from the shape of the 2nd junction part 4b in planar view by points, such as the presence or absence of the through-hole 4a1. Thereby, the orientation mistake of the inner lead 4 can be suppressed in the mounting process of the inner lead 4 at the time of manufacturing the power semiconductor device. As a result, the manufacturing yield can be improved.

＜実施の形態２＞
図６は、本発明の実施の形態２に係るパワー半導体装置の一部の構成を模式的に示す分解斜視図である。なお、本実施の形態２に係るパワー半導体装置において、以上で説明した構成要素と同一または類似するものについては同じ参照符号を付し、異なる部分について主に説明する。 <Embodiment 2>
FIG. 6 is an exploded perspective view schematically showing a partial configuration of the power semiconductor device according to the second embodiment of the present invention. In the power semiconductor device according to the second embodiment, components that are the same as or similar to the components described above are denoted by the same reference numerals, and different portions are mainly described.

図６では、本実施の形態２に係るパワー半導体装置のうちパワー半導体チップ２及びインナーリード４が抜き出されて図示されている。   In FIG. 6, the power semiconductor chip 2 and the inner lead 4 are extracted from the power semiconductor device according to the second embodiment.

パワー半導体チップ２は、上面電極２ａ上に円形の開口２ｄ１が設けられた電極保護膜２ｄをさらに含んでいる。開口２ｄ１内には、導電性部材３ｂが設けられる。このような構成によれば、電極保護膜２ｄが円形の開口２ｄ１を有するので、上面電極２ａのはんだ付け可能領域は円形となる。   The power semiconductor chip 2 further includes an electrode protective film 2d provided with a circular opening 2d1 on the upper surface electrode 2a. A conductive member 3b is provided in the opening 2d1. According to such a configuration, since the electrode protective film 2d has the circular opening 2d1, the solderable region of the upper surface electrode 2a is circular.

インナーリード４の第１接合部４ａの下面の外郭形状は、電極保護膜２ｄの開口２ｄ１の直径より小さい直径を有する円形となっている。そして、第１接合部４ａは、開口２ｄ１内に設けられた導電性部材３ｂを介して上面電極２ａと、平面視において開口２ｄ１の外周内に接合されている。   The outer shape of the lower surface of the first joint portion 4a of the inner lead 4 is a circle having a diameter smaller than the diameter of the opening 2d1 of the electrode protective film 2d. And the 1st junction part 4a is joined with the upper surface electrode 2a via the electroconductive member 3b provided in opening 2d1, and the outer periphery of opening 2d1 in planar view.

図７（ａ）は、本実施の形態２に係るパワー半導体装置に関連するパワー半導体装置（以下「関連パワー半導体装置」と記す）の構成を模式的に示す平面図である。図７（ｂ）は、本実施の形態２に係るパワー半導体装置の構成を模式的に示す平面図である。図７（ａ）では、関連パワー半導体装置のうちパワー半導体チップ２（実線）及び第１接合部４ａ（二点鎖線）が抜き出されて図示されており、図７（ｂ）では、本実施の形態２に係るパワー半導体装置のうちパワー半導体チップ２（実線）及び第１接合部４ａ（二点鎖線）が抜き出されて図示されている。   FIG. 7A is a plan view schematically showing a configuration of a power semiconductor device (hereinafter referred to as “related power semiconductor device”) related to the power semiconductor device according to the second embodiment. FIG. 7B is a plan view schematically showing the configuration of the power semiconductor device according to the second embodiment. In FIG. 7A, the power semiconductor chip 2 (solid line) and the first joint portion 4a (two-dot chain line) are extracted from the related power semiconductor device and illustrated in FIG. 7B. In the power semiconductor device according to the second embodiment, the power semiconductor chip 2 (solid line) and the first joint portion 4a (two-dot chain line) are extracted and illustrated.

以下、この図７（ａ）及び図７（ｂ）を用いて、本実施の形態２に係るパワー半導体装置の効果について説明する。   Hereinafter, the effect of the power semiconductor device according to the second embodiment will be described with reference to FIGS. 7A and 7B.

関連パワー半導体装置では、図７（ａ）に示すように、電極保護膜２ｄの開口２ｄ１、及び、第１接合部４ａの下面（接合面）の外郭形状が、いずれも四角形となっている。このような構成において、何らかの理由で第１接合部４ａの端部が開口２ｄ１の端部に重なるように第１接合部４ａが偏って配置されると、破線で囲まれる重なり部分のフィレット角度αが大きくなる。図８に、フィレット角度αの一例を示す。なお、このフィレット角度αが大きいほど、パワー半導体装置の温度変化などに起因した上面電極２ａに生じる応力が大きくなる。   In the related power semiconductor device, as shown in FIG. 7A, the outer shape of the opening 2d1 of the electrode protection film 2d and the lower surface (bonding surface) of the first bonding portion 4a is a quadrangle. In such a configuration, when the first joint portion 4a is disposed so that the end portion of the first joint portion 4a overlaps the end portion of the opening 2d1 for some reason, the fillet angle α of the overlapping portion surrounded by the broken line Becomes larger. FIG. 8 shows an example of the fillet angle α. Note that the greater the fillet angle α, the greater the stress generated on the upper surface electrode 2a due to temperature changes of the power semiconductor device.

開口２ｄ１及び第１接合部４ａの端部の一辺同士が重なると、比較的広い範囲でフィレット角度αが大きくなるが、図７（ａ）に示すように端部の二辺同士が重なると、さらに広い範囲でフィレット角度αが大きくなってしまう。この結果、パワー半導体装置に不具合が生じる可能性が多少高くなる。   When one side of the opening 2d1 and the end of the first joint portion 4a overlap, the fillet angle α increases in a relatively wide range, but when the two sides of the end overlap as shown in FIG. In addition, the fillet angle α increases in a wider range. As a result, the possibility that the power semiconductor device is defective is somewhat increased.

これに対して本実施の形態２に係るパワー半導体装置では、図７（ｂ）に示すように、開口２ｄ１及び第１接合部４ａの端部が重なったとしても、開口２ｄ１の円に第１接合部４ａの円が接する箇所でしか重ならない。したがって、開口２ｄ１及び第１接合部４ａの端部が重なる範囲を狭くすることができ、フィレット角度αが大きくなる範囲をごく一部に抑えることができるので、信頼性を向上させることができる。また、第１接合部４ａの下面が円形になることで、はんだ付け可能領域の外郭形状から角部がなくなる。このため、パワー半導体装置の温度変化に起因にしてはんだ（導電性部材３ｂ）に生じる応力が集中することを抑制することができる。   On the other hand, in the power semiconductor device according to the second embodiment, as shown in FIG. 7B, even if the opening 2d1 and the end of the first joint 4a overlap, the first in the circle of the opening 2d1. It overlaps only at the place where the circle of the joint 4a contacts. Therefore, the range in which the opening 2d1 and the end of the first joint portion 4a overlap can be narrowed, and the range in which the fillet angle α increases can be suppressed to a very small portion, so that the reliability can be improved. Moreover, since the lower surface of the 1st junction part 4a becomes circular, a corner | angular part will disappear from the outline shape of a solderable area | region. For this reason, it can suppress that the stress which arises in a solder (conductive member 3b) resulting from the temperature change of a power semiconductor device concentrates.

なお、図９（ａ）及び図９（ｂ）に示すように、開口２ｄ１の円形の直径をｄｓ、第１接合部４ａの下面の円形の直径をｄｌとする。この場合に、本実施の形態２では、０．７×ｄｓ＜ｄｌ、かつ、０．０５ｍｍ＜（ｄｓ−ｄｌ）の関係が満たされている。   9A and 9B, the circular diameter of the opening 2d1 is ds, and the circular diameter of the lower surface of the first joint 4a is dl. In this case, in the second embodiment, the relationship of 0.7 × ds <dl and 0.05 mm <(ds−dl) is satisfied.

ここで、仮にｄｌが０．７×ｄｓよりも小さくなると、上面電極２ａのうちはんだ（導電性部材３ｂ）で覆われない部分が生じるので、その部分がモールド樹脂６と直接接触することになる。この場合、上面電極２ａの微細構造が、モールド樹脂６によって損傷を受けて、信頼性が低下する場合があり、製品の機能が制限される。一方、仮に（ｄｓ−ｄｌ）が０．０５ｍｍ以下になると、フィレット角度αが大きくなり、パワー半導体装置の温度変化などに起因した上面電極２ａに生じる応力が大きくなる。   Here, if dl is smaller than 0.7 × ds, a portion of the upper surface electrode 2a that is not covered with the solder (conductive member 3b) is generated, so that the portion is in direct contact with the mold resin 6. . In this case, the fine structure of the upper surface electrode 2a may be damaged by the mold resin 6, and the reliability may be lowered, and the function of the product is limited. On the other hand, if (ds−dl) is 0.05 mm or less, the fillet angle α is increased, and the stress generated in the upper surface electrode 2a due to the temperature change of the power semiconductor device is increased.

これに対して、本実施の形態２では、０．７×ｄｓ＜ｄｌ、かつ、０．０５ｍｍ＜（ｄｓ−ｄｌ）の関係が満たされているので、上面電極２ａのモールド樹脂６と直接接触する部分を低減することができるとともに、フィレット角度αが大きくなることを抑制することができる。   On the other hand, in the second embodiment, since the relationship of 0.7 × ds <dl and 0.05 mm <(ds−dl) is satisfied, it is in direct contact with the mold resin 6 of the upper surface electrode 2a. The portion to be reduced can be reduced, and the increase of the fillet angle α can be suppressed.

なお、本実施の形態２のインナーリード４の形状は、第１接合部４ａの下面が円形状を有しているため、切削加工、鋳造、鍛造、つぶし加工または放電加工などで形成することが好ましく、特にパワー半導体装置を大量生産する場合には、生産効率が比較的良いつぶし加工が好ましい。   The shape of the inner lead 4 of the second embodiment can be formed by cutting, casting, forging, crushing or electric discharge machining because the lower surface of the first joint 4a has a circular shape. In particular, when mass-producing power semiconductor devices, crushing with relatively good production efficiency is preferable.

また、以上の説明では、パワー半導体チップ２は、オン時に厚さ方向に電流を流す縦型の半導体チップであるものとして説明したが、これに限ったものではなく、例えばオン時に水平方向に電流を流す横型の半導体チップであってもよい。   In the above description, the power semiconductor chip 2 has been described as a vertical semiconductor chip that allows a current to flow in the thickness direction when the power semiconductor chip 2 is turned on. However, the power semiconductor chip 2 is not limited thereto. It may be a horizontal semiconductor chip through which the current flows.

なお、本発明は、その発明の範囲内において、各実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、省略したりすることが可能である。   It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

１，１ａ，１ｂ，１ｃ リード、２ パワー半導体チップ、２ａ 上面電極、２ｂ ゲート電極、２ｄ 電極保護膜、２ｄ１ 開口、３ａ，３ｂ，３ｃ 導電性部材、４ インナーリード、４ａ 第１接合部、４ａ１ 貫通穴、４ｂ 第２接合部、４ｃ 胴体部、５，５ａ，５ｂ ワイヤー、６ モールド樹脂。   1, 1a, 1b, 1c lead, 2 power semiconductor chip, 2a upper surface electrode, 2b gate electrode, 2d electrode protective film, 2d1 opening, 3a, 3b, 3c conductive member, 4 inner lead, 4a first junction, 4a1 Through hole, 4b second joint, 4c body, 5, 5a, 5b wire, 6 mold resin.

Claims (12)

一端側が外部端子となる第１及び第２リードと、
上面に設けられた上面電極を備え、下面が前記第１リードの他端側上に接合されたパワー半導体チップと、
前記上面電極上に第１導電性部材を介して接合された第１接合部と、前記第２リードの他端側上に第２導電性部材を介して接合された第２接合部と、前記第１接合部と前記第２接合部とを連接する胴体部とを有するインナーリードと、
前記第１及び第２リードの他端側、前記パワー半導体チップ及び前記インナーリードを覆うモールド樹脂と
を備え、
前記第１接合部が前記胴体部よりも厚く形成されたことによって、前記第１接合部の下端が前記胴体部の下端よりも下側に位置し、
前記パワー半導体チップは、
前記上面電極上に円形の開口が設けられた電極保護膜をさらに備え、
前記第１接合部の下面の外郭形状は、前記開口の直径より小さい直径を有する円形であり、
前記第１接合部は、前記開口内に設けられた前記第１導電性部材を介して前記上面電極と、平面視において前記開口の外周内に接合されている、パワー半導体装置。 First and second leads whose one end side is an external terminal;
A power semiconductor chip comprising an upper surface electrode provided on the upper surface, and a lower surface bonded to the other end of the first lead;
A first joint joined to the upper surface electrode via a first conductive member; a second joint joined to the other end of the second lead via a second conductive member; An inner lead having a body portion connecting the first joint portion and the second joint portion;
A mold resin covering the other end side of the first and second leads, the power semiconductor chip and the inner lead;
By forming the first joint part thicker than the body part, the lower end of the first joint part is located below the lower end of the body part ,
The power semiconductor chip is
An electrode protective film provided with a circular opening on the upper surface electrode;
The outer shape of the lower surface of the first joint is a circle having a diameter smaller than the diameter of the opening,
Said first junction, and said upper surface electrode through the first conductive member provided in the opening, that is joined to the periphery of the opening in a plan view, the power semiconductor device. 請求項１に記載のパワー半導体装置であって、
前記第１及び第２リードは、一平面上に配置されている、パワー半導体装置。 The power semiconductor device according to claim 1,
The power semiconductor device, wherein the first and second leads are arranged on one plane. 請求項１または請求項２に記載のパワー半導体装置であって、
前記インナーリードは、
一つの導電性板材につぶし加工を行うことによって形成された、パワー半導体装置。 The power semiconductor device according to claim 1 or 2,
The inner lead is
A power semiconductor device formed by crushing a single conductive plate. 請求項１から請求項３のうちいずれか１項に記載のパワー半導体装置であって、
前記インナーリードの前記接合に関与しない面である上面が平坦化された、パワー半導体装置。 The power semiconductor device according to any one of claims 1 to 3,
A power semiconductor device in which an upper surface, which is a surface not involved in the joining of the inner leads, is planarized. 請求項１から請求項４のうちいずれか１項に記載のパワー半導体装置であって、
前記第２接合部を前記第１接合部よりも厚く形成することによって、前記第２接合部の下端が前記第１接合部の下端よりも下側に位置する、パワー半導体装置。 The power semiconductor device according to any one of claims 1 to 4,
A power semiconductor device in which the second joint is formed thicker than the first joint so that the lower end of the second joint is positioned below the lower end of the first joint. 請求項４に記載のパワー半導体装置であって、
前記インナーリードの前記上面と、前記第１及び第２リードが配置された一平面とが略平行に配設されている、パワー半導体装置。 The power semiconductor device according to claim 4,
The power semiconductor device, wherein the upper surface of the inner lead and a plane on which the first and second leads are arranged are arranged substantially in parallel. 請求項１から請求項６のうちいずれか１項に記載のパワー半導体装置であって、
前記第１接合部の前記胴体部側の側面と、前記第１接合部の下面とがなす角度の補角をθとした場合に、６０°≦θ≦９０°の関係が満たされている、パワー半導体装置。 The power semiconductor device according to any one of claims 1 to 6,
When the complementary angle of the angle formed by the side surface of the first joint portion on the body portion side and the lower surface of the first joint portion is θ, the relationship of 60 ° ≦ θ ≦ 90 ° is satisfied. Power semiconductor device. 請求項１から請求項７のうちいずれか１項に記載のパワー半導体装置であって、
一端側が外部端子となる第３リードをさらに備え、
前記パワー半導体チップは、ＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）またはＩＧＢＴ（Insulated Gate Bipolar Transistor）であり、かつ、前記上面電極とは別に前記上面に設けられたゲート電極をさらに備え、
前記ゲート電極と前記第３リードとがワイヤーのボンディングによって接続されている、パワー半導体装置。 The power semiconductor device according to any one of claims 1 to 7,
A third lead whose one end is an external terminal;
The power semiconductor chip is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or IGBT (Insulated Gate Bipolar Transistor), and further includes a gate electrode provided on the top surface separately from the top surface electrode,
The power semiconductor device, wherein the gate electrode and the third lead are connected by wire bonding. 請求項１から請求項７のうちいずれか１項に記載のパワー半導体装置であって、
一端側が外部端子となる第３リードをさらに備え、
前記パワー半導体チップは、前記上面において温度を検知する検温ダイオードをさらに備え、
前記検温ダイオードの電極と前記第３リードとがワイヤーのボンディングによって接続されている、パワー半導体装置。 The power semiconductor device according to any one of claims 1 to 7,
A third lead whose one end is an external terminal;
The power semiconductor chip further includes a temperature detection diode for detecting a temperature on the upper surface,
The power semiconductor device, wherein the electrode of the temperature sensing diode and the third lead are connected by wire bonding. 請求項１から請求項９のうちいずれか１項に記載のパワー半導体装置であって、
平面視において前記第１接合部の中央部を貫通する貫通穴が、前記第１接合部に設けられた、パワー半導体装置。 The power semiconductor device according to any one of claims 1 to 9,
A power semiconductor device, wherein a through hole penetrating a central portion of the first joint portion in the plan view is provided in the first joint portion. 請求項１から請求項１０のうちいずれか１項に記載のパワー半導体装置であって、
平面視において前記第１接合部の形状と前記第２接合部の形状とが異なる、パワー半導体装置。 It is a power semiconductor device given in any 1 paragraph among Claims 1-10,
A power semiconductor device, wherein a shape of the first joint portion and a shape of the second joint portion are different in a plan view. 請求項１から請求項１１のうちいずれか１項に記載のパワー半導体装置であって、
前記開口の前記円形の直径をｄｓ、前記第１接合部の下面の前記円形の直径をｄｌとした場合に、０．７×ｄｓ＜ｄｌ、かつ、０．０５ｍｍ＜（ｄｓ−ｄｌ）の関係が満たされている、パワー半導体装置。 The power semiconductor device according to any one of claims 1 to 11 ,
When the circular diameter of the opening is ds and the circular diameter of the lower surface of the first joint is dl, a relationship of 0.7 × ds <dl and 0.05 mm <(ds−dl) is established. It is met, the power semiconductor device.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110892527A (en) * 2017-10-26 2020-03-17 新电元工业株式会社 Semiconductor device and method for manufacturing semiconductor device

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6834815B2 (en) * 2017-07-06 2021-02-24 株式会社デンソー Semiconductor module
CN112119491A (en) * 2018-11-05 2020-12-22 富士电机株式会社 Lead frame wiring structure and semiconductor module
US11929307B2 (en) 2019-02-13 2024-03-12 Hitachi Astemo, Ltd. Plurality of lead frames for cooling a power device
DE112021002880T5 (en) * 2020-07-20 2023-04-06 Rohm Co., Ltd. SEMICONDUCTOR DEVICE
WO2024070884A1 (en) * 2022-09-28 2024-04-04 ニデック株式会社 Semiconductor module

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03240292A (en) 1990-02-19 1991-10-25 Matsushita Electric Ind Co Ltd Manufacture of printed circuit board
US6040626A (en) 1998-09-25 2000-03-21 International Rectifier Corp. Semiconductor package
JP4710131B2 (en) * 2000-12-21 2011-06-29 株式会社豊田自動織機 Semiconductor device
JP4899481B2 (en) * 2006-01-10 2012-03-21 サンケン電気株式会社 Manufacturing method of resin-encapsulated semiconductor device having a heat radiator exposed outside
US7880280B2 (en) 2007-02-16 2011-02-01 Infineon Technologies Ag Electronic component and method for manufacturing an electronic component
JP2010050286A (en) * 2008-08-21 2010-03-04 Toshiba Corp Semiconductor device
JP5540857B2 (en) * 2010-04-16 2014-07-02 日立金属株式会社 Lead component, semiconductor package using the same, and lead component manufacturing method
JP5270614B2 (en) * 2010-05-24 2013-08-21 三菱電機株式会社 Semiconductor device
JP2013251500A (en) * 2012-06-04 2013-12-12 Renesas Electronics Corp Semiconductor device and manufacturing method of the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110892527A (en) * 2017-10-26 2020-03-17 新电元工业株式会社 Semiconductor device and method for manufacturing semiconductor device
CN110892527B (en) * 2017-10-26 2023-10-27 新电元工业株式会社 Semiconductor device and method for manufacturing semiconductor device

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