JP2010050286A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2010050286A
JP2010050286A JP2008213353A JP2008213353A JP2010050286A JP 2010050286 A JP2010050286 A JP 2010050286A JP 2008213353 A JP2008213353 A JP 2008213353A JP 2008213353 A JP2008213353 A JP 2008213353A JP 2010050286 A JP2010050286 A JP 2010050286A
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semiconductor device
electrode lead
resin
semiconductor chip
wiring
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Takao Atagi
孝男 能木
Kentaro Suga
謙太郎 菅
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Toshiba Corp
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Toshiba Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is compact and has high heat dissipation characteristics. <P>SOLUTION: The semiconductor device includes: first and second electrode leads 11 and 12 disposed apart from each other; a semiconductor chip 13 mounted on a first surface 11a of the first electrode lead 11; a resin 14 for sealing the first electrode lead 11, second electrode lead 12 and semiconductor chip 13 while exposing a second surface 11b opposed to the first surface 11a of the first electrode 11 and a second surface 12b opposed to a first surface 12a of the second electrode lead 12; and wiring 15 formed on the resin 14 and having one side 15a connected to the semiconductor chip 13 by penetrating a part of the resin 14 which corresponds to the semiconductor chip 13 and the other side 15b connected to the second electrode lead 12 by penetrating a part of the resin 14 which corresponds to the second electrode lead 12. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半導体装置に関する。   The present invention relates to a semiconductor device.

近年、携帯電話や移動式携帯端末に代表される各種の小型電子機器の普及に伴い、樹脂封止型の半導体装置では、電極リードが基板に直接ハンダ付けできる表面実装型のパッケージが主流になってきている。   In recent years, with the spread of various small electronic devices typified by mobile phones and mobile portable terminals, surface mount packages in which electrode leads can be directly soldered to a substrate have become mainstream in resin-encapsulated semiconductor devices. It is coming.

従来、第１電極リードに半導体チップを載置し、ワイヤを介して半導体チップと第２電極リードを接続し、樹脂でモールドした半導体装置は、ワイヤがループを巻くため半導体装置の高さを低くすることが難しいという問題がある。また、ワイヤからの放熱が期待できず十分な放熱特性が得られないという問題がある。   Conventionally, a semiconductor device in which a semiconductor chip is mounted on a first electrode lead, the semiconductor chip and the second electrode lead are connected via a wire, and is molded with a resin has a low height because the wire winds around a loop. There is a problem that it is difficult to do. Further, there is a problem that heat radiation from the wire cannot be expected and sufficient heat radiation characteristics cannot be obtained.

これに対して、ワイヤを用いずに小型で放熱特性を向上させた半導体装置が知られている（例えば、特許文献１または特許文献２参照。）。   On the other hand, a semiconductor device that is small and has improved heat dissipation characteristics without using a wire is known (see, for example, Patent Document 1 or Patent Document 2).

特許文献１に開示された半導体装置は、フリップ実装によって配線基板に搭載された半導体チップを封止体によって封止したワイヤレスのパッケージ構造とし、封止体上面から露出した放熱板でもある上部導電板および封止体下面から露出した放熱板でもある外部接続用電極を有している。
上部導電板は半導体チップの裏面と電気的に接続されており、外部接続用電極は半導体チップの主面と基板上部電極およびビアホールを介して電気的に接続されている。 The semiconductor device disclosed in Patent Document 1 has a wireless package structure in which a semiconductor chip mounted on a wiring board by flip mounting is sealed with a sealing body, and an upper conductive plate that is also a heat dissipation plate exposed from the top surface of the sealing body And it has the electrode for external connection which is also a heat sink exposed from the lower surface of the sealing body.
The upper conductive plate is electrically connected to the back surface of the semiconductor chip, and the external connection electrode is electrically connected to the main surface of the semiconductor chip via the substrate upper electrode and via holes.

特許文献２に開示された半導体装置は、基板上に、電子部品と端子とを設け、端子本体部の上面を電子部品の面よりも高くすると共に、端子本体部の上面を露出するように封止樹脂を設けて、端子と配線パターンとを直接接続している。   In the semiconductor device disclosed in Patent Document 2, an electronic component and a terminal are provided on a substrate, the upper surface of the terminal main body is made higher than the surface of the electronic component, and the upper surface of the terminal main body is exposed. A stop resin is provided to directly connect the terminal and the wiring pattern.

然しながら特許文献１または特許文献２に開示された半導体装置は、電極が封止体の上面と下面に引き出されているので、表面実装型のパッケージを有する半導体装置が得られないという問題がある。
特開２００８−４２０６３号公報 特開２００７−４２９７７号公報 However, the semiconductor device disclosed in Patent Document 1 or Patent Document 2 has a problem in that a semiconductor device having a surface mount type package cannot be obtained because the electrodes are drawn out from the upper surface and the lower surface of the sealing body.
JP 2008-42063 A JP 2007-42977 A

本発明は、小型で放熱特性の高い半導体装置を提供する。   The present invention provides a small semiconductor device having high heat dissipation characteristics.

本発明の一態様の半導体装置は、離間して配置された第１および第２電極リードと、前記第１電極リードの第１の面に載置された半導体チップと、前記第１電極リードの前記第１の面と対向する面、および前記第２電極リードの第１の面と対向する面をそれぞれ露出させて、前記第１電極リード、前記第２電極リードおよび前記半導体チップを封止する樹脂と、前記樹脂上に形成され、一方が前記樹脂の前記半導体チップに対応する部位を貫通して前記半導体チップに接続され、他方が前記樹脂の前記第２電極リードに対応する部位を貫通して前記第２電極リードに接続された配線と、を具備することを特徴としている。   A semiconductor device according to an aspect of the present invention includes a first electrode lead and a second electrode lead that are spaced apart from each other, a semiconductor chip placed on a first surface of the first electrode lead, and the first electrode lead The surface facing the first surface and the surface facing the first surface of the second electrode lead are exposed to seal the first electrode lead, the second electrode lead, and the semiconductor chip. A resin and one formed through the resin, one through the portion corresponding to the semiconductor chip and connected to the semiconductor chip, and the other through the portion corresponding to the second electrode lead of the resin. And a wiring connected to the second electrode lead.

本発明によれば、小型で放熱特性の高い半導体装置が得られる。   According to the present invention, a small semiconductor device having high heat dissipation characteristics can be obtained.

以下、本発明の実施例について図面を参照しながら説明する。   Embodiments of the present invention will be described below with reference to the drawings.

本発明の実施例１について、図１乃至図３を参照して説明する。図１は本発明の実施例１に係る半導体装置を示す図で、図１（ａ）はパッケージの一部が切り欠きされたその平面図、図１（ｂ）は図１（ａ）のＡ−Ａ線に沿って切断し、矢印方向に眺めた断面図、図１（ｃ）は半導体装置の側面図、図２は半導体装置を示す斜視図、図３は半導体装置の特性を比較例と対比して示す図で、図３（ａ）が本実施例の半導体装置の特性を示す図、図３（ｂ）が比較例の半導体装置の特性を示すである。   A first embodiment of the present invention will be described with reference to FIGS. 1A and 1B are diagrams showing a semiconductor device according to a first embodiment of the present invention, in which FIG. 1A is a plan view of a part of a package cut out, and FIG. 1B is A in FIG. FIG. 1C is a side view of the semiconductor device, FIG. 2C is a perspective view showing the semiconductor device, and FIG. 3 is a comparison of the characteristics of the semiconductor device with that of the comparative example. In comparison, FIG. 3A shows the characteristics of the semiconductor device of this example, and FIG. 3B shows the characteristics of the semiconductor device of the comparative example.

本実施例は、ｐｎ接合を有するシリコンダイオードチップが表面実装型のパッケージに樹脂封止された半導体装置の例である。   This embodiment is an example of a semiconductor device in which a silicon diode chip having a pn junction is resin-sealed in a surface mount type package.

図１に示すように、本実施例の半導体装置１０は、離間して配置された第１および第２電極リード１１、１２と、第１電極リード１１の第１の面１１ａに載置された半導体チップ１３と、第１電極リード１１の第１の面１１ａと対向する第２の面１１ｂ、および第２電極リード１２の第１の面１２ａと対向する第２の面１２ｂをそれぞれ露出させて、第１電極リード１１、第２電極リード１２および半導体チップ１３を封止する樹脂１４と、を具備している。   As shown in FIG. 1, the semiconductor device 10 according to the present embodiment is placed on the first and second electrode leads 11 and 12 that are spaced apart from each other and the first surface 11 a of the first electrode lead 11. The semiconductor chip 13, the second surface 11b facing the first surface 11a of the first electrode lead 11, and the second surface 12b facing the first surface 12a of the second electrode lead 12 are exposed. , A first electrode lead 11, a second electrode lead 12, and a resin 14 that seals the semiconductor chip 13.

更に、半導体装置１０は、樹脂１４上に形成され、一方１５ａが樹脂１４の半導体チップ１３に対応する部位を貫通して半導体チップ１３に接続され、他方１５ｂが樹脂１４の第２電極リード１２に対応する部位を貫通して第２電極リード１２に接続された板状主要部を有する配線１５（以後、単に配線１５という）と、を具備している。   Furthermore, the semiconductor device 10 is formed on the resin 14, one side 15 a passes through a portion corresponding to the semiconductor chip 13 of the resin 14 and is connected to the semiconductor chip 13, and the other 15 b is connected to the second electrode lead 12 of the resin 14. Wiring 15 (hereinafter simply referred to as wiring 15) having a plate-like main portion that penetrates the corresponding portion and is connected to the second electrode lead 12 is provided.

第１および第２電極リード１１、１２は、例えば第２の面１１ｂ、１２ｂ側から第１の面１１ａ、１２ａに向かって、第１のＡｕ膜、第１のＮｉ膜、Ｃｕ膜、第２のＮｉ膜および第２のＡｕ膜が積層されている。   The first and second electrode leads 11 and 12 are, for example, a first Au film, a first Ni film, a Cu film, and a second film from the second surfaces 11b and 12b toward the first surfaces 11a and 12a. The Ni film and the second Au film are laminated.

Ｃｕ膜は、第１および第２電極リード１１、１２の主要構成材であり、その熱伝導率が３９４Ｗ／ｍＫと高いので、半導体チップ１３の発熱が外部に放散するのを容易にしている。
第１および第２のＡｕ膜は、Ｃｕ膜の酸化を防止し、外部基板（図示せず）へのハンダ付けを容易にしている。
第１および第２のＮｉ膜は、マウント時の加熱によりＡｕとＣｕが拡散して、第１および第２のＡｕ膜がそれぞれＣｕ膜と合金化するのを阻止するバリア層として機能し、マウント不良を防止している。
従って、第１および第２のＡｕ膜の膜厚は、例えば０．２〜２μｍ、Ｎｉ膜の膜厚は、例えば１〜５μｍ、Ｃｕ膜の膜厚は、例えば１０〜５０μｍ程度が適当である。 The Cu film is a main constituent material of the first and second electrode leads 11 and 12 and has a high thermal conductivity of 394 W / mK, so that it is easy to dissipate heat generated by the semiconductor chip 13 to the outside.
The first and second Au films prevent the Cu film from being oxidized and facilitate soldering to an external substrate (not shown).
The first and second Ni films function as a barrier layer that prevents Au and Cu from diffusing by heating during mounting and preventing the first and second Au films from alloying with the Cu film, respectively. Defects are prevented.
Accordingly, it is appropriate that the first and second Au films have a thickness of, for example, 0.2 to 2 μm, the Ni film has a thickness of, for example, 1 to 5 μm, and the Cu film has a thickness of, for example, about 10 to 50 μm. .

半導体チップ１３は、ｐｎ接合を有するシリコンダイオードチップで、上面に例えばアノード端子となるアルミニウムを主成分とする金属電極層１６が形成され、下面にカソード端子となるアルミニウムを主成分とする金属電極層（図示せず）が形成されている。
金属電極層１６は絶縁膜、例えばポリイミド膜（図示せず）で覆われており、配線１５の一方１５ａが接触する部位が露出している。 The semiconductor chip 13 is a silicon diode chip having a pn junction. For example, a metal electrode layer 16 mainly composed of aluminum serving as an anode terminal is formed on the upper surface, and a metal electrode layer mainly composed of aluminum serving as a cathode terminal is formed on the lower surface. (Not shown) is formed.
The metal electrode layer 16 is covered with an insulating film, for example, a polyimide film (not shown), and a portion where the one 15a of the wiring 15 contacts is exposed.

半導体チップ１３は、例えば導電性接着材を介して第１電極リード１１の第１の面１１ａに固着されている。
樹脂１４は、後述するように例えば金型を用いたトランスファーモールド法により形成されたエポキシ樹脂である。 The semiconductor chip 13 is fixed to the first surface 11a of the first electrode lead 11 through, for example, a conductive adhesive.
As will be described later, the resin 14 is an epoxy resin formed by, for example, a transfer molding method using a mold.

配線１５は、後述するように例えば無電界メッキにより形成された幅５０〜１００μｍ、厚さ５〜１０μｍ程度のＣｕ配線である。
配線１５の一方１５ａは、樹脂１４の半導体チップ１３に対応する部位に形成された図示されない第１貫通孔を通して金属電極層１６に接触している。
配線１５の他方１５ｂは、樹脂１４の第２電極リード１２に対応する部位に形成された図示されない第２貫通孔を通して第２電極リード１２の第１の面１２ａに接触している。 As will be described later, the wiring 15 is a Cu wiring having a width of about 50 to 100 μm and a thickness of about 5 to 10 μm formed by, for example, electroless plating.
One side 15 a of the wiring 15 is in contact with the metal electrode layer 16 through a first through hole (not shown) formed in a portion of the resin 14 corresponding to the semiconductor chip 13.
The other 15 b of the wiring 15 is in contact with the first surface 12 a of the second electrode lead 12 through a second through hole (not shown) formed in a portion corresponding to the second electrode lead 12 of the resin 14.

図２は内部が透視された半導体装置１０を示す斜視図である。太い実線は半導体装置１０の外観を示し、細い実線は半導体装置１０の内部の構造を示している。   FIG. 2 is a perspective view showing the semiconductor device 10 whose inside is seen through. A thick solid line indicates the appearance of the semiconductor device 10, and a thin solid line indicates the internal structure of the semiconductor device 10.

図３は半導体装置１０の特性を比較例と対比して示す図で、図３（ａ）が本実施例の半導体装置の特性を示す図、図３（ｂ）が比較例の半導体装置の特性を示す図である。
ここで、比較例とは、半導体チップ１３がワイヤを介して第２電極リード１２に接続された半導体装置のことである。始めに、比較例について説明する。 FIG. 3 is a diagram showing the characteristics of the semiconductor device 10 in comparison with the comparative example. FIG. 3A is a diagram showing the characteristics of the semiconductor device of this example, and FIG. 3B is the characteristics of the semiconductor device of the comparative example. FIG.
Here, the comparative example is a semiconductor device in which the semiconductor chip 13 is connected to the second electrode lead 12 via a wire. First, a comparative example will be described.

図３（ｂ）に示すように、比較例の半導体装置３０は、ワイヤ３１が半導体チップ１３と第２電極リード１２との離間距離に応じてループを描くので、それに応じて樹脂３２の高さＨ２が高くなってしまう。   As shown in FIG. 3B, in the semiconductor device 30 of the comparative example, the wire 31 draws a loop according to the separation distance between the semiconductor chip 13 and the second electrode lead 12, and accordingly the height of the resin 32 is accordingly increased. H2 becomes high.

また、ワイヤ３１は、表面積が小さく、且つ熱伝導率の小さい樹脂３２に取り囲まれているので、ワイヤ３１からの放熱３４は小さい。
更に、ワイヤ３１の断面積も小さいので、熱がワイヤ３１を伝わりにくく、第２電極リードからの放熱も少ない。 Moreover, since the wire 31 has a small surface area and is surrounded by a resin 32 having a low thermal conductivity, the heat radiation 34 from the wire 31 is small.
Furthermore, since the cross-sectional area of the wire 31 is small, heat is not easily transmitted through the wire 31, and heat radiation from the second electrode lead is small.

一方、図３（ａ）に示すように、本実施例の半導体装置１０は、少なくとも半導体チップ１３の上面が樹脂１４で覆われていれば良いので、樹脂１４の高さＨ１を樹脂３２の高さＨ２より十分に低くすることができる。   On the other hand, as shown in FIG. 3A, in the semiconductor device 10 of this embodiment, at least the upper surface of the semiconductor chip 13 only needs to be covered with the resin 14, so that the height H1 of the resin 14 is set to the height of the resin 32. It can be made sufficiently lower than the height H2.

また、配線１５の幅は樹脂１４の幅以内で自由に設定できるので、ワイヤ３１に比べて表面積が十分に大きくなり、且つ大気中に露出しているので、配線１５からの放熱３３を十分に大きくすることができる。
更に、ワイヤ３１に比べて断面積が十分に大きいので、熱が配線１５を伝わりやすくなり、第２電極リード１２からの放熱も大きくすることができる。 In addition, since the width of the wiring 15 can be freely set within the width of the resin 14, the surface area is sufficiently larger than that of the wire 31 and is exposed to the atmosphere. Can be bigger.
Furthermore, since the cross-sectional area is sufficiently larger than that of the wire 31, heat is easily transmitted through the wiring 15, and heat radiation from the second electrode lead 12 can be increased.

但し、第１電極リード１１からの放熱は、本実施例の半導体装置１０および比較例の半導体装置３０とも同様である。   However, the heat radiation from the first electrode lead 11 is the same as in the semiconductor device 10 of the present embodiment and the semiconductor device 30 of the comparative example.

これにより、本実施例の半導体装置１０は、比較例の半導体装置３０に比べて、樹脂１４の高さＨ１を十分に低くすることができるとともに、高い放熱性を得ることが可能である。
半導体チップ１３であるシリコンダイオードに矩形状の所定の順方向電流を流しておき、順方向電流がオフの期間にシリコンダイオードの逆方向電流を測定する方法により求められるシリコンダイオードの接合温度が、比較例より低減される見込みが得られた。 Thereby, the semiconductor device 10 of the present embodiment can sufficiently reduce the height H1 of the resin 14 and can obtain high heat dissipation as compared with the semiconductor device 30 of the comparative example.
The junction temperature of the silicon diode obtained by passing a predetermined rectangular forward current through the silicon diode as the semiconductor chip 13 and measuring the reverse current of the silicon diode while the forward current is off is compared. The prospect of reduction was obtained from the example.

次に、半導体装置１０の製造方法について説明する。図４乃至図７は半導体装置１０の製造工程を順に示す断面図、図８は半導体装置１０を基板に実装した状態を示す断面図である。   Next, a method for manufacturing the semiconductor device 10 will be described. 4 to 7 are cross-sectional views sequentially showing the manufacturing process of the semiconductor device 10, and FIG. 8 is a cross-sectional view showing a state in which the semiconductor device 10 is mounted on a substrate.

始に、図４（ａ）に示すように、第１および第２電極リード１１、１２が格子状に配置された半導体装置用基板４０を用意する。   First, as shown in FIG. 4A, a semiconductor device substrate 40 in which the first and second electrode leads 11 and 12 are arranged in a grid is prepared.

具体的には、導電性の基板、例えば厚さ１５０μｍ程度のステンレス板上に、保護膜としてレジスト膜を形成し、フォトリソグラフィー法により、第１および第２電極リード１１、１２を形成するための第１および第２開口をパターニングする。
保護膜の厚さは、第１のＡｕ膜、第１のＮｉ膜、Ｃｕ膜、第２のＮｉ膜および第２のＡｕ膜の膜厚の和に等しい厚さ、例えば３０〜４０μｍ程度に設定する。 Specifically, a resist film is formed as a protective film on a conductive substrate, for example, a stainless plate having a thickness of about 150 μm, and the first and second electrode leads 11 and 12 are formed by photolithography. The first and second openings are patterned.
The thickness of the protective film is set equal to the sum of the thicknesses of the first Au film, the first Ni film, the Cu film, the second Ni film, and the second Au film, for example, about 30 to 40 μm. To do.

次に、第１および第２開口内の基板４０上に、第１のＡｕ膜、第１のＮｉ膜、Ｃｕ膜、第２のＮｉ膜および第２のＡｕ膜を、電気メッキ法により順次形成する。   Next, a first Au film, a first Ni film, a Cu film, a second Ni film, and a second Au film are sequentially formed on the substrate 40 in the first and second openings by an electroplating method. To do.

次に、保護膜を除去することにより、導電性の基板上に離間して格子状に配置された第１および第２電極リード１１、１２を有する半導体装置用基板４０（以後、単に基板４０ともいう）が得られる。   Next, by removing the protective film, the semiconductor device substrate 40 (hereinafter simply referred to as the substrate 40) having the first and second electrode leads 11 and 12 arranged in a grid pattern on the conductive substrate. Say).

次に、図４（ｂ）に示すように、第１電極リード１１の第１の面１１ａ上に半導体チップ１３を載置する。   Next, as shown in FIG. 4B, the semiconductor chip 13 is placed on the first surface 11 a of the first electrode lead 11.

次に、図５（ａ）に示すように、第２電極リード１２対応する部位に第２電極１２の第１の面１２ａに達する第２貫通孔４２を設けて、基板４０上の第１および第２電極リード１１、１２、半導体チップ１３を樹脂４１で被覆する。   Next, as shown in FIG. 5A, a second through hole 42 reaching the first surface 12a of the second electrode 12 is provided at a portion corresponding to the second electrode lead 12, and the first and The second electrode leads 11 and 12 and the semiconductor chip 13 are covered with a resin 41.

具体的には、内面の第２電極リード１２と対応する部位に、第２電極リード１２の第１の面１２ａに接する棒状の突起を有する金型を用い、トランスファーモールド法により樹脂を注入することにより、第２貫通孔４２を設けて、基板４０上の第１および第２電極リード１１、１２、半導体チップ１３が樹脂４１でモールドされる。   Specifically, a resin having a rod-like protrusion in contact with the first surface 12a of the second electrode lead 12 is used at a portion corresponding to the second electrode lead 12 on the inner surface, and the resin is injected by a transfer molding method. Thus, the second through hole 42 is provided, and the first and second electrode leads 11 and 12 and the semiconductor chip 13 on the substrate 40 are molded with the resin 41.

次に、図５（ｂ）に示すように、樹脂４１の半導体チップ１３に対応する部位に半導体チップ１３の金属電極層１６に達する第１貫通孔４３を形成する。   Next, as shown in FIG. 5B, a first through hole 43 reaching the metal electrode layer 16 of the semiconductor chip 13 is formed in a portion corresponding to the semiconductor chip 13 of the resin 41.

具体的には、樹脂４１の半導体チップ１３に対応する部位にレーザを照射し、照射部の樹脂４１を溶融飛散させることにより、金属電極層１６に達する第１貫通孔４３を形成する。   Specifically, the first through hole 43 reaching the metal electrode layer 16 is formed by irradiating a portion of the resin 41 corresponding to the semiconductor chip 13 with a laser to melt and scatter the resin 41 in the irradiation portion.

このとき、金属電極層１６は、レーザの反射率が高いことが要求されるので、表面に反射率の高い金膜を形成しておくことが望ましい。   At this time, since the metal electrode layer 16 is required to have a high laser reflectance, it is desirable to form a gold film having a high reflectance on the surface.

次に、デスミア処理を行い、第１貫通孔４３、第２貫通孔４２形成時に孔の周りに生じたスミア（有機物残渣）を除去する。   Next, a desmear process is performed to remove smear (organic residue) generated around the holes when the first through holes 43 and the second through holes 42 are formed.

次に、図６（ａ）に示すように、無電界メッキ法により第１貫通孔４３、第２貫通孔４２を含む樹脂４１上の全面に下地メッキを施した後に、フォトリソグラフィー法により樹脂４１上に第１貫通孔４３および第２貫通孔４２を内包する開口４４ａを有するレジスト膜４４を形成する。   Next, as shown in FIG. 6A, after the entire surface of the resin 41 including the first through hole 43 and the second through hole 42 is plated by electroless plating, the resin 41 is formed by photolithography. A resist film 44 having an opening 44a including the first through hole 43 and the second through hole 42 is formed thereon.

次に、図６（ｂ）に示すように、電解メッキ法により、樹脂４１上にＣｕをメッキする。これにより、一端１５ａが第１貫通孔４３を通して半導体チップ１３に接続され、他端１５ｂが第２貫通孔４２を通して第２電極リード１２に接続された配線１５が得られる。   Next, as shown in FIG. 6B, Cu is plated on the resin 41 by electrolytic plating. Thereby, the wiring 15 having one end 15 a connected to the semiconductor chip 13 through the first through hole 43 and the other end 15 b connected to the second electrode lead 12 through the second through hole 42 is obtained.

次に、図７（ａ）に示すように、レジスト膜４４およびレジスト膜４４下の下地メッキ膜を除去する。
次に、図7（ｂ）に示すように、例えば樹脂４１の上面を吸着固定し、基板４０側を巻き取るようにして、基板４０より第１および第２電極リード１１、１２を剥離する。
これにより、樹脂４１より第１電極リード１１の第２の面１１ｂおよび第２電極リード１２の第２の面１２ｂが露出し、半導体装置１０が、例えば数千個程度一括して形成される。 Next, as shown in FIG. 7A, the resist film 44 and the underlying plating film under the resist film 44 are removed.
Next, as shown in FIG. 7B, for example, the upper surface of the resin 41 is suction-fixed, and the first and second electrode leads 11 and 12 are peeled from the substrate 40 so as to wind up the substrate 40 side.
As a result, the second surface 11b of the first electrode lead 11 and the second surface 12b of the second electrode lead 12 are exposed from the resin 41, and, for example, several thousand semiconductor devices 10 are collectively formed.

次に、図７（ｃ）に示すように、半導体装置１０を一括して封止する樹脂４１をダイシング用の粘着性シート４５に貼り付け、ブレード４６を用いて樹脂４１をダイシングすることにより、個々の半導体装置１０に分離する。   Next, as shown in FIG. 7C, a resin 41 that collectively seals the semiconductor device 10 is attached to an adhesive sheet 45 for dicing, and the resin 41 is diced using a blade 46, Separated into individual semiconductor devices 10.

これにより、図１に示す離間して配置された第１および第２電極リード１１、１２と、第１電極リード１１の第１の面１１ａに載置された半導体チップ１３と、第１電極リード１１の第２の面１１ｂ、および第２電極リード１２の第２の面１２ｂをそれぞれ露出させて、第１電極リード１１、第２電極リード１２および半導体チップ１３を封止する樹脂１４と、樹脂１４上に形成され、一方１５ａが樹脂１４の半導体チップ１３に対応する部位を貫通して半導体チップ１３に接続され、他方１５ｂが樹脂１４の第２電極リード１２に対応する部位を貫通して第２電極リード１２に接続された配線１５と、を具備する半導体装置１０が得られる。   Thus, the first and second electrode leads 11 and 12 that are spaced apart from each other as shown in FIG. 1, the semiconductor chip 13 placed on the first surface 11a of the first electrode lead 11, and the first electrode lead A resin 14 for sealing the first electrode lead 11, the second electrode lead 12, and the semiconductor chip 13 by exposing the second surface 11 b of the second electrode 11 and the second surface 12 b of the second electrode lead 12. 14, one side 15 a passes through a part corresponding to the semiconductor chip 13 of the resin 14 and is connected to the semiconductor chip 13, and the other 15 b passes through a part corresponding to the second electrode lead 12 of the resin 14 and passes through the part. The semiconductor device 10 including the wiring 15 connected to the two-electrode lead 12 is obtained.

図８は半導体装置１０が配線基板に実装された状態を示す断面図である。
図８に示すように、半導体装置１０は、配線基板５０上の配線パターン５１の一端に設けられた接続端子５３に第１電極リード１１の第２の面１１ｂが当接し、配線パターン５２の一端に設けられた接続端子５４に第２電極リード１２の第２の面１２ｂが当接するように載置される。 FIG. 8 is a cross-sectional view showing a state where the semiconductor device 10 is mounted on a wiring board.
As shown in FIG. 8, in the semiconductor device 10, the second surface 11 b of the first electrode lead 11 comes into contact with the connection terminal 53 provided at one end of the wiring pattern 51 on the wiring substrate 50, and one end of the wiring pattern 52 is formed. Is mounted so that the second surface 12b of the second electrode lead 12 is in contact with the connection terminal 54 provided in the first electrode 12.

配線基板５０は、例えばガラスエポキシ基板であり、配線パターン５１、５２は、例えば厚さ２０μｍ程度の接着材（図示せず）で貼り付けられた厚さ２０μｍ程度の銅箔であり、接続端子５３、５４は、例えば１００μｍ角程度のはんだ（ペースト）である。   The wiring board 50 is, for example, a glass epoxy board, and the wiring patterns 51 and 52 are, for example, a copper foil having a thickness of about 20 μm bonded with an adhesive (not shown) having a thickness of about 20 μm. , 54 is, for example, solder (paste) of about 100 μm square.

配線基板５０上に半導体装置１０を載置して加熱することにより、第１および第２電極リード１１、１２が接続端子５３、５４にハンダ付けされ、半導体装置１０が配線基板５０にマウントされる。   By placing and heating the semiconductor device 10 on the wiring substrate 50, the first and second electrode leads 11 and 12 are soldered to the connection terminals 53 and 54, and the semiconductor device 10 is mounted on the wiring substrate 50. .

以上説明しように、本実施例の半導体装置１０は、樹脂１４上に形成され、半導体チップ１３と第２電極リード１２とを接続する配線１５を具備している。   As described above, the semiconductor device 10 of this embodiment includes the wiring 15 that is formed on the resin 14 and connects the semiconductor chip 13 and the second electrode lead 12.

その結果、ワイヤを用いて半導体チップ１３と第２電極リード１２とを接続する場合に比べて、樹脂１４の高さＨ１を十分低くすることができるとともに、配線１５が大気中に露出しているので放熱性を向上させることができる。 As a result, compared to the case where the semiconductor chip 13 and the second electrode lead 12 are connected using a wire, the height H1 of the resin 14 can be made sufficiently low, and the wiring 15 is exposed to the atmosphere. Therefore, heat dissipation can be improved.

従って、小型で放熱特性の高い半導体装置、例えば長さ０．３〜２ｍｍ、幅０．１〜１ｍｍ、高さ０．１〜１ｍｍ程度の半導体装置が得られる。   Therefore, a small semiconductor device having high heat dissipation characteristics, for example, a semiconductor device having a length of 0.3 to 2 mm, a width of 0.1 to 1 mm, and a height of 0.1 to 1 mm is obtained.

ここでは、配線１５の他方１５ｂが、第２電極リード１２の第１電極リード１１と反対側の端部に接触している場合について説明したが、特に制限はなく、第２電極リード１２の中央部でも、第１電極リード１１側の端部でも構わない。   Here, the case where the other 15 b of the wiring 15 is in contact with the end of the second electrode lead 12 opposite to the first electrode lead 11 has been described, but there is no particular limitation, and the center of the second electrode lead 12 is not limited. Or an end on the first electrode lead 11 side.

基板４０としては、電気メッキ法により形成される第１および第２電極リード１１、１２との剥離性が良いステンレス板を用いた場合について説明したが、ステンレス以外の金属材料を使用しても構わない。   As the substrate 40, the case where a stainless steel plate having good peelability from the first and second electrode leads 11 and 12 formed by electroplating has been described, but a metal material other than stainless steel may be used. Absent.

また、第１および第２電極リード１１、１２を電気メッキ法で形成する場合について説明したが、無電界メッキ法により形成することもできる。
無電界メッキ法であれば、可塑性のある絶縁性フィルム、例えばポリイミドなどを基板として用いることができる。 Moreover, although the case where the 1st and 2nd electrode leads 11 and 12 were formed by the electroplating method was demonstrated, it can also form by the electroless plating method.
With the electroless plating method, a plastic insulating film such as polyimide can be used as the substrate.

但し、第１および第２電極リード１１、１２の膜厚が大きい場合は、メッキ速度が大きい電界メッキ法が、処理時間や費用の点でより好ましいので、電界メッキ法と無電界メッキ法を組合せて形成しても構わない。   However, when the film thicknesses of the first and second electrode leads 11 and 12 are large, the electroplating method with a high plating speed is more preferable in terms of processing time and cost. Therefore, the electroplating method and the electroless plating method are combined. May be formed.

また、第１および第２電極リード１１、１２をメッキ法により形成する場合について説明したが、目的の厚さが得られる範囲内であれば別の方法、例えば真空蒸着法あるいはスパッタリング法などで形成することもできる。   In addition, the case where the first and second electrode leads 11 and 12 are formed by the plating method has been described. However, if the target thickness is within a range where the target thickness can be obtained, another method such as a vacuum evaporation method or a sputtering method is used. You can also

基板４０側を巻き取るようにして、基板４０より第１および第２電極リード１１、１２を剥離する場合について説明したが、基板４０をエッチングで除去するようにしても構わない。   Although the case where the first and second electrode leads 11 and 12 are peeled from the substrate 40 so as to wind up the substrate 40 side has been described, the substrate 40 may be removed by etching.

本発明の実施例２について、図９を参照して説明する。図９は本発明の実施例２に係る半導体装置を示す図で、図９（ａ）はパッケージの一部が切り欠きされたその平面図、図９（ｂ）は図９（ａ）のＢ−Ｂ線に沿って切断し、矢印の方向に眺めた断面図、図９（ｃ）は半導体装置を示す側面図ある。   A second embodiment of the present invention will be described with reference to FIG. 9A and 9B are diagrams showing a semiconductor device according to Embodiment 2 of the present invention. FIG. 9A is a plan view of a part of the package, and FIG. 9B is a plan view of FIG. 9A. FIG. 9C is a cross-sectional view taken along line B and viewed in the direction of the arrow, and FIG. 9C is a side view showing the semiconductor device.

本実施例において上記実施例１と同一の構成部分には同一符号を付してその説明は省略し、異なる部分についてのみ説明する。本実施例が実施例１と異なる点は、配線の他方を樹脂の側面に露出させたことにある。   In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and only different portions will be described. The present embodiment is different from the first embodiment in that the other side of the wiring is exposed on the side surface of the resin.

即ち、図９に示すように、本実施例に係る半導体装置６０は、第２電極リード１２の第１電極リード１１と反対側の端部が樹脂６１の側面に露出し、配線１５の他方１５ｂが樹脂６１の側面に沿って露出し、第２電極リード１２の端部に接続されている。   That is, as shown in FIG. 9, in the semiconductor device 60 according to this example, the end of the second electrode lead 12 opposite to the first electrode lead 11 is exposed on the side surface of the resin 61, and the other 15 b of the wiring 15. Is exposed along the side surface of the resin 61 and connected to the end of the second electrode lead 12.

配線１５の他方１５ｂが大気中に露出しているので、配線１５の他方１５ｂからの放熱６２を向上させることが可能である。   Since the other 15b of the wiring 15 is exposed to the atmosphere, the heat radiation 62 from the other 15b of the wiring 15 can be improved.

次に、半導体装置６０の製造方法について説明する。図１０は半導体装置６０の製造工程の要部を示す断面図である。   Next, a method for manufacturing the semiconductor device 60 will be described. FIG. 10 is a cross-sectional view showing the main part of the manufacturing process of the semiconductor device 60.

図１０（ａ）に示すように、基板４０上に第１電極リード１１および第２電極リード１２を紙面の横方向に左右対称になるように配置し、隣接する第２電極リード１２同士をダイシングの切り代δを加味して連接し、格子状に形成する。   As shown in FIG. 10A, the first electrode lead 11 and the second electrode lead 12 are arranged on the substrate 40 so as to be symmetrical in the lateral direction of the paper surface, and the adjacent second electrode leads 12 are diced together. In consideration of the cutting allowance δ, they are connected to form a lattice shape.

次に、図５（ａ）から図７（ａ）と同様にして第１電極リード１１上に半導体チップ１３を載置し、樹脂４１でモールドし、配線１５を形成する。   Next, in the same manner as in FIGS. 5A to 7A, the semiconductor chip 13 is placed on the first electrode lead 11 and molded with the resin 41 to form the wiring 15.

次に、図１０（ｂ）に示すように、図７（ｂ）と同様にして基板４０を除去した後、図７（ｃ）と同様にして樹脂４１をシート４５に貼り付け、ブレード４６を用いてダイシングする。
これにより、配線１５の他方１５ｂおよび第２電極１２が２分割され、図９に示す第２電極リード１２の第１電極リード１１と反対側の端部が樹脂６１の側面に露出し、配線１５の他方１５ｂが樹脂６１の側面に沿って露出し、第２電極リード１２の端部に接続された半導体装置６０が得られる。 Next, as shown in FIG. 10B, after removing the substrate 40 in the same manner as in FIG. 7B, the resin 41 is attached to the sheet 45 in the same manner as in FIG. Use dicing.
As a result, the other 15b of the wiring 15 and the second electrode 12 are divided into two, and the end of the second electrode lead 12 shown in FIG. 9 opposite to the first electrode lead 11 is exposed on the side surface of the resin 61. Is exposed along the side surface of the resin 61, and the semiconductor device 60 connected to the end of the second electrode lead 12 is obtained.

以上説明したように、本実施例の半導体装置６０は、配線１５の他方１５ｂが樹脂６１の側面に沿って露出しているので、配線１５の他方１５ｂからの放熱６２を向上させることができる利点がある。   As described above, in the semiconductor device 60 of this embodiment, since the other 15b of the wiring 15 is exposed along the side surface of the resin 61, the heat radiation 62 from the other 15b of the wiring 15 can be improved. There is.

また、配線１５の他方１５ｂを覆う側面の樹脂がないので、半導体装置６０のサイズを更に小さくできる利点がある。
更に、基板４０のサイズの縮小、樹脂４１の使用量の削減が可能であり、生産性を向上させることができる利点がある。 Further, since there is no resin on the side surface covering the other 15b of the wiring 15, there is an advantage that the size of the semiconductor device 60 can be further reduced.
Further, the size of the substrate 40 can be reduced and the amount of the resin 41 used can be reduced, which has the advantage that productivity can be improved.

ここでは、隣接する第２電極リード１２同士を連接して形成し、ダイシングにより配線１５の他方１５ｂを樹脂６１の側面に沿って露出させる場合について説明したが、別の方法によっても構わない。   Here, the case where the adjacent second electrode leads 12 are connected to each other and the other 15b of the wiring 15 is exposed along the side surface of the resin 61 by dicing has been described, but another method may be used.

例えば、図７（ｃ）に示すダイシング位置を配線１５の他方１５ｂに連接させてダイシングすることも可能である。ただし、ダイシング精度に左右されるので、本実施の方法がより適している。   For example, dicing can be performed by connecting the dicing position shown in FIG. 7C to the other 15 b of the wiring 15. However, this method is more suitable because it depends on the dicing accuracy.

本発明の実施例３について、図１１を参照して説明する。図１１は本発明の実施例３に係る半導体装置を示す断面図である。
本実施例において上記実施例１と同一の構成部分には同一符号を付してその説明は省略し、異なる部分についてのみ説明する。本実施例が実施例１と異なる点は、半導体チップ上にバンプを形成したことにある。 A third embodiment of the present invention will be described with reference to FIG. FIG. 11 is a sectional view showing a semiconductor device according to Example 3 of the present invention.
In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and only different portions will be described. This embodiment is different from the first embodiment in that bumps are formed on the semiconductor chip.

即ち、図１１に示すように、本実施例に係る半導体装置７０は、半導体チップ１３上にバンプ７１が形成され、配線１５の一方１５ｂがバンプ７１を介して半導体チップ１３に接続されている。   That is, as shown in FIG. 11, in the semiconductor device 70 according to the present embodiment, bumps 71 are formed on the semiconductor chip 13, and one of the wires 15 is connected to the semiconductor chip 13 via the bumps 71.

バンプ７１は、例えば導電性ペーストを焼結して得た焼結導電層であり、ここでは、金属電極層１６を介して半導体チップ１３上に形成されている。   The bump 71 is a sintered conductive layer obtained by sintering a conductive paste, for example, and is formed on the semiconductor chip 13 via the metal electrode layer 16 here.

これにより、半導体装置７０は、高さＨ３がバンプ７１を有しない半導体装置１０の高さＨ１よりバンプの高さΔＨ、例えば５０μｍだけ高くなるが、配線１５と半導体チップ１３との間の距離が確保され、耐圧を向上させることが可能である。   As a result, the semiconductor device 70 has a height H3 higher than the height H1 of the semiconductor device 10 having no bump 71 by a bump height ΔH, for example, 50 μm, but the distance between the wiring 15 and the semiconductor chip 13 is increased. It is ensured and the breakdown voltage can be improved.

次に、半導体装置７０の製造方法について説明する。図１２は半導体装置７０の製造工程の要部を示す断面図である。   Next, a method for manufacturing the semiconductor device 70 will be described. FIG. 12 is a cross-sectional view showing the main part of the manufacturing process of the semiconductor device 70.

図１２（ａ）に示すように、半導体チップ１３の金属電極膜１６上に導電性ペーストを例えばスクリーン印刷法により塗布し、リフローして金属電極膜１６上に焼結導電層であるバンプ７１を形成する。
次に、図５（ａ）と同様にして第２貫通孔４２を設けて、基板４０上の第１および第２電極リード１１、１２、半導体チップ１３を樹脂４１で被覆する。 As shown in FIG. 12A, a conductive paste is applied on the metal electrode film 16 of the semiconductor chip 13 by, for example, a screen printing method, and reflowed to form bumps 71 that are sintered conductive layers on the metal electrode film 16. Form.
Next, as in FIG. 5A, the second through hole 42 is provided, and the first and second electrode leads 11 and 12 and the semiconductor chip 13 on the substrate 40 are covered with the resin 41.

次に、図１２（ｂ）に示すように、樹脂４１の上面をラッピングし、バンプ７１の上面を露出させる。ここでは、ストッパーがないので、ラッピングの停止位置は樹脂４１の高さ管理により行う。   Next, as shown in FIG. 12B, the upper surface of the resin 41 is lapped to expose the upper surface of the bump 71. Here, since there is no stopper, the lapping stop position is controlled by the height of the resin 41.

次に、図６（ａ）から図７（ｃ）と同様にして、図１１に示す半導体チップ１３上にバンプ７１が形成され、配線１５の一方１５ｂがバンプ７１を介して半導体チップ１３に接続された半導体装置７０が得られる。   Next, in the same manner as in FIGS. 6A to 7C, bumps 71 are formed on the semiconductor chip 13 shown in FIG. 11, and one of the wirings 15 b is connected to the semiconductor chip 13 via the bumps 71. The obtained semiconductor device 70 is obtained.

以上説明したように、本実施例の半導体装置７０は、半導体チップ１３上にバンプ７１が形成され、配線１５の一方１５ｂがバンプ７１を介して半導体チップ１３に接続されているので、配線１５と半導体チップ１３との間の距離が確保され、耐圧を向上させることができる利点がある。   As described above, in the semiconductor device 70 of this embodiment, the bump 71 is formed on the semiconductor chip 13, and the one 15 b of the wiring 15 is connected to the semiconductor chip 13 through the bump 71. There is an advantage that the distance between the semiconductor chip 13 is secured and the breakdown voltage can be improved.

また、予め余裕を見てバンプ７１の高さを定めておけば、ラッピングの加工精度（例えば厚さずれ、面内分布など）にムラがあっても問題なく、高精度なラッピング装置を用いなくても済む利点がある。   Also, if the height of the bump 71 is determined in advance with a margin, there is no problem even if there is unevenness in lapping processing accuracy (for example, thickness deviation, in-plane distribution, etc.), and a high-precision lapping device is not used. There is an advantage that can be done.

また、高価なレーザ加工機を用いて樹脂４１に第１貫通孔４３を形成する必要がないので、半導体装置７０の製造工程が簡略化され、生産性が向上する利点がある。   In addition, since it is not necessary to form the first through hole 43 in the resin 41 using an expensive laser processing machine, there is an advantage that the manufacturing process of the semiconductor device 70 is simplified and the productivity is improved.

ここでは、バンプ７１が焼結導電層である場合について説明したが、ハンダボールなどを用いても構わない。   Although the case where the bump 71 is a sintered conductive layer has been described here, a solder ball or the like may be used.

本発明の実施例４３について、図１３を参照して説明する。図１３は本発明の実施例４に係る半導体装置を示す図で、図１３（ａ）はパッケージの一部が切り欠きされたその平面図、図１３（ｂ）は図１３（ａ）のＣ−Ｃ線に沿って切断し、矢印の方向に眺めた断面図である。
本実施例において上記実施例１と同一の構成部分には同一符号を付してその説明は省略し、異なる部分についてのみ説明する。本実施例が実施例１と異なる点は、複数の配線を有することにある。 Embodiment 43 of the present invention will be described with reference to FIG. 13A and 13B are views showing a semiconductor device according to Embodiment 4 of the present invention. FIG. 13A is a plan view of a part of the package, and FIG. 13B is a plan view of FIG. 13A. It is sectional drawing cut | disconnected along the -C line | wire and it looked at the direction of the arrow.
In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and only different portions will be described. This embodiment is different from the first embodiment in that it has a plurality of wirings.

即ち、図１１に示すように、本実施例に係る半導体装置８０は、第１および第２電極リード１１、１２と離間して配置された第３電極リード８１と、樹脂８２上に形成され、一方８３ａが樹脂８２の半導体チップ８４に対応する部位を貫通して半導体チップ８４に接続され、他方８３ｂが樹脂８２の第３電極リード８１に対応する部位を貫通して第３電極リード８１に接続された配線８３と、を具備している。   That is, as shown in FIG. 11, the semiconductor device 80 according to the present embodiment is formed on the resin 82 and the third electrode lead 81 that is spaced apart from the first and second electrode leads 11 and 12. One side 83a passes through a portion corresponding to the semiconductor chip 84 of the resin 82 and is connected to the semiconductor chip 84, and the other side 83b passes through a portion corresponding to the third electrode lead 81 of the resin 82 and is connected to the third electrode lead 81. Wiring 83 is provided.

第３電極リード８１は、第１電極リード１１を挟んで第２電極リード１２と対向し、一方向（紙面の横方向）に配列されている。   The third electrode lead 81 is opposed to the second electrode lead 12 with the first electrode lead 11 in between, and is arranged in one direction (the horizontal direction on the paper surface).

半導体チップ８４は、３端子の半導体素子、例えば縦型ＭＯＳトランジスタで、上面にソースＳ端子となるアルミニウムを主成分とする金属電極膜８５、およびゲートＧ端子となるアルミニウムを主成分とするとなる金属電極膜８６が形成され、下面にドレインＤ端子となるアルミニウムを主成分とする金属電極膜（図示せず）が形成されている。   The semiconductor chip 84 is a three-terminal semiconductor element, for example, a vertical MOS transistor, and has a metal electrode film 85 mainly composed of aluminum serving as a source S terminal on its upper surface and a metal composed mainly of aluminum serving as a gate G terminal. An electrode film 86 is formed, and a metal electrode film (not shown) containing aluminum as a main component and serving as a drain D terminal is formed on the lower surface.

半導体チップ８４は、ドレインＤが第１電極リード１１に接続され、ソースＳが配線１５を介して第２電極リード１２に接続され、ゲートＧが配線８３を介して第３電極リード８１に接続されている。   In the semiconductor chip 84, the drain D is connected to the first electrode lead 11, the source S is connected to the second electrode lead 12 through the wiring 15, and the gate G is connected to the third electrode lead 81 through the wiring 83. ing.

配線１５の一方１５ａは、半導体チップ８４の金属電極膜８５と接触している。配線８３の一方８３ａは、半導体チップ８４の金属電極膜８６と接触している。   One side 15 a of the wiring 15 is in contact with the metal electrode film 85 of the semiconductor chip 84. One side 83 a of the wiring 83 is in contact with the metal electrode film 86 of the semiconductor chip 84.

これにより、３端子の半導体素子を用いた半導体装置８０においても、半導体装置８０の高さＨ４を半導体装置１０の高さＨ１と同程度にすることができるとともに、高い放熱性を得ることが可能である。   Thereby, also in the semiconductor device 80 using a three-terminal semiconductor element, the height H4 of the semiconductor device 80 can be made substantially equal to the height H1 of the semiconductor device 10, and high heat dissipation can be obtained. It is.

半導体装置８０の製造方法は、図５（ａ）から図７（ｃ）に示す半導体装置１０の製造方法と同様であり、その説明は省略する。   The manufacturing method of the semiconductor device 80 is the same as the manufacturing method of the semiconductor device 10 shown in FIGS. 5A to 7C, and the description thereof is omitted.

以上説明したように、本実施例の半導体装置８０は、第３電極リード８１と、樹脂８２上に形成され、一方８３ａが樹脂８２の半導体チップ８４に対応する部位を貫通して半導体チップ８４に接続され、他方８３ｂが樹脂８２の第３電極リード８１に対応する部位を貫通して第３電極リード８１に接続された配線８３と、を具備している。
これにより、３端子の半導体チップ８４においても、小型で放熱特性の高い半導体装置が得られる利点がある。
特に、トランジスタなどの発熱量のより大きな半導体チップの放熱特性が向上する利点がある。 As described above, the semiconductor device 80 according to the present embodiment is formed on the third electrode lead 81 and the resin 82, and one side 83 a penetrates the portion corresponding to the semiconductor chip 84 of the resin 82 to the semiconductor chip 84. The other 83 b is connected to the third electrode lead 81 through the portion corresponding to the third electrode lead 81 of the resin 82.
As a result, the three-terminal semiconductor chip 84 also has an advantage that a small semiconductor device having high heat dissipation characteristics can be obtained.
In particular, there is an advantage that the heat dissipation characteristics of a semiconductor chip having a larger heat generation amount such as a transistor are improved.

ここでは、第１乃至第３電極リード１１、１２、８１が、一方向に配置されている場合について説明したが、三角形の各頂点に配置しても構わない。
図１４は、第１乃至第３電極リード１１、１２、８１が三角形の各頂点に配置された半導体装置を示すパッケージの一部が切り欠きされた平面図である。 Although the case where the first to third electrode leads 11, 12, 81 are arranged in one direction has been described here, they may be arranged at each vertex of the triangle.
FIG. 14 is a plan view in which a part of a package showing a semiconductor device in which the first to third electrode leads 11, 12, 81 are arranged at each vertex of the triangle is cut out.

図１４に示すように、半導体装置８７は、第１乃至第３電極リード１１、１２、８１がほぼ正三角形の各頂点に配置された第１乃至第３電極リード１１、１２、８１を具備している。
第１乃至第３電極リード１１、１２、８１を三角形の各頂点に配置することにより、横長の長方形状の樹脂８２から正方形状の樹脂８８を有する半導体装置８７が得られるので、基板に実装するに際し、レイアウトの自由度が広がり、実装密度を向上させることができる利点がある。 As shown in FIG. 14, the semiconductor device 87 includes first to third electrode leads 11, 12, 81 in which the first to third electrode leads 11, 12, 81 are arranged substantially at the vertices of an equilateral triangle. ing.
By arranging the first to third electrode leads 11, 12, 81 at the apexes of the triangle, the semiconductor device 87 having the square resin 88 can be obtained from the horizontally long rectangular resin 82, so that it is mounted on the substrate. At this time, there is an advantage that the degree of freedom of layout is widened and the mounting density can be improved.

半導体チップ８４が３端子の半導体素子である場合について説明したが、半導体チップ１３と同じく２端子の半導体素子であっても構わない。
その場合、例えばアノード端子となる金属電極膜８５、８６を連接して形成し、配線１５、８３によりアノード端子が２方向に引き出された半導体装置が得られる。
これにより、２端子の半導体素子でも、発熱量のより大きな半導体チップの放熱特性が向上する利点がある。 Although the case where the semiconductor chip 84 is a three-terminal semiconductor element has been described, it may be a two-terminal semiconductor element like the semiconductor chip 13.
In that case, for example, the metal electrode films 85 and 86 to be the anode terminal are connected and formed, and a semiconductor device in which the anode terminal is drawn in two directions by the wirings 15 and 83 is obtained.
Thereby, even in a two-terminal semiconductor element, there is an advantage that the heat dissipation characteristics of a semiconductor chip having a larger amount of heat generation are improved.

本発明の実施例５について、図１５を参照して説明する。図１５は本発明の実施例５に係る半導体装置を示す図で、図１５（ａ）はパッケージの一部が切り欠きされたその平面図、図１５（ｂ）は図１５（ａ）のＤ−Ｄ線に沿って切断し、矢印の方向に眺めた断面図、図１５（ｃ）は図１５（ａ）のＥ−Ｅ線に沿って切断し、矢印の方向に眺めた断面図である。   A fifth embodiment of the present invention will be described with reference to FIG. 15A and 15B are diagrams showing a semiconductor device according to a fifth embodiment of the present invention, in which FIG. 15A is a plan view of a part of the package cut out, and FIG. 15B is a diagram D of FIG. FIG. 15C is a cross-sectional view taken along the line E and viewed in the direction of the arrow, and FIG. 15C is a cross-sectional view taken along the line E-E in FIG. .

本実施例において上記実施例１と同一の構成部分には同一符号を付してその説明は省略し、異なる部分についてのみ説明する。本実施例が実施例１と異なる点は、樹脂の上面に溝を設け、溝内に配線を形成したことにある。   In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and only different portions will be described. This embodiment differs from the first embodiment in that a groove is provided on the upper surface of the resin and wiring is formed in the groove.

即ち、図１５に示すように、本実施例に係る半導体装置９０は、溝９１が形成された樹脂９２を有し、配線１５が溝９１内に埋め込まれて形成されている。
溝９１は、樹脂９２の半導体チップ１３に対応する部位から樹脂９２の第２電極リード１２に対応する部位まで形成されている。 That is, as shown in FIG. 15, the semiconductor device 90 according to the present embodiment includes a resin 92 in which a groove 91 is formed, and the wiring 15 is embedded in the groove 91.
The groove 91 is formed from a portion of the resin 92 corresponding to the semiconductor chip 13 to a portion of the resin 92 corresponding to the second electrode lead 12.

これにより、配線１５の上部が樹脂９２の上面から突出していないので、配線１５が製造工程中または使用中に擦られた場合に損傷する恐れが防止され、半導体装置９０の信頼性を向上させることが可能である。   Thereby, since the upper part of the wiring 15 does not protrude from the upper surface of the resin 92, the possibility that the wiring 15 is damaged when it is rubbed during the manufacturing process or during use is prevented, and the reliability of the semiconductor device 90 is improved. Is possible.

次に、半導体装置９０の製造方法について説明する。
溝９１は図５（ａ）に示す第２貫通孔４２を形成するときに、同時に形成する。具体的には、内面の第２電極リード１２と対応する部位に第２電極リード１２の第１の面１２ａに接する棒状の突起、および内面の溝９１と対応する部位に棒状の突起の根元に連接した矩形状の凸部を有する金型を用い、トランスファーモールド法により樹脂を注入することにより、第２貫通孔４２、および溝９１が同時に形成される。 Next, a method for manufacturing the semiconductor device 90 will be described.
The groove 91 is formed simultaneously with the formation of the second through hole 42 shown in FIG. Specifically, a rod-shaped protrusion that contacts the first surface 12a of the second electrode lead 12 at a portion corresponding to the second electrode lead 12 on the inner surface, and a rod-shaped protrusion at a portion corresponding to the groove 91 on the inner surface. The second through hole 42 and the groove 91 are simultaneously formed by injecting resin by a transfer molding method using a mold having connected rectangular convex portions.

次に、図６（ａ）、図６（ｂ）と同様にして、レジスト膜をマスクとして電解メッキ法により第１貫通孔４３、第２貫通孔４２、及び溝９１内にＣｕをメッキし、配線１５を形成する。   Next, similarly to FIGS. 6A and 6B, Cu is plated in the first through hole 43, the second through hole 42, and the groove 91 by electrolytic plating using the resist film as a mask, A wiring 15 is formed.

Ｃｕメッキは、配線１５の上部が溝９１から突出しないように行うことが望ましいが、溝９１内にＣｕをメッキした後に、樹脂９２の上面を軽くポリッシュして、表面を平滑化しても良い。   The Cu plating is desirably performed so that the upper portion of the wiring 15 does not protrude from the groove 91. However, after Cu is plated in the groove 91, the upper surface of the resin 92 may be lightly polished to smooth the surface.

以上説明したように、本実例の半導体装置９０は、配線１５が樹脂９２の上面に形成された溝９１に埋め込まれているので、配線１５が擦れて損傷するのが防止され、半導体装置９０の信頼性を向上させることができる利点がある。   As described above, in the semiconductor device 90 of this example, since the wiring 15 is embedded in the groove 91 formed on the upper surface of the resin 92, the wiring 15 is prevented from being rubbed and damaged. There is an advantage that reliability can be improved.

ここでは、溝９１を金型により形成する場合について説明したが、その他の方法でも構わない。
例えば、図５（ｂ）に示す第１貫通孔４３を形成した後に、続けて形成することができる。具体的には、レーザを照射して第１貫通孔４３を形成した後に、レーザパワーを調整し、第１貫通孔４３から第２貫通孔４２までレーザを照射する位置を移動させることにより、溝９１を形成することができる。 Although the case where the groove 91 is formed by a mold has been described here, other methods may be used.
For example, after the first through hole 43 shown in FIG. 5B is formed, it can be formed continuously. Specifically, after forming the first through-hole 43 by irradiating a laser, the laser power is adjusted, and the position of irradiating the laser from the first through-hole 43 to the second through-hole 42 is moved. 91 can be formed.

本発明は、以下の付記に記載されているような構成が考えられる。
（付記１） 請求項３において、前記配線の一方が前記樹脂の前記半導体チップに対応する部位を貫通して前記半導体チップに接続され、前記配線の他方が前記樹脂の前記第３電極リードに対応する部位を貫通して前記第３電極リードに接続されている半導体装置。 The present invention can be configured as described in the following supplementary notes.
(Additional remark 1) In Claim 3, one side of the said wiring penetrates the site | part corresponding to the said semiconductor chip of the said resin, and is connected to the said semiconductor chip, and the other of the said wiring respond | corresponds to the said 3rd electrode lead of the said resin And a semiconductor device connected to the third electrode lead.

（付記２） 請求項３において、前記第３電極リードの前記第１電極リードと反対側の端部が前記樹脂の側面に露出し、前記配線の前記他方が前記樹脂の側面に沿って露出し、前記第３電極リードの前記端部に接続されている半導体装置。 (Additional remark 2) In Claim 3, the edge part on the opposite side to the said 1st electrode lead of the said 3rd electrode lead is exposed to the side surface of the said resin, and the said other side of the said wiring is exposed along the side surface of the said resin. A semiconductor device connected to the end of the third electrode lead.

本発明の実施例１に係る半導体装置を示す図で、図１（ａ）はパッケージの一部が切り欠きされたその平面図、図１（ｂ）は図１（ａ）のＡ−Ａ線に沿って切断し、矢印の方向に眺めた断面図、図１（ｃ）はその側面図。1A and 1B are diagrams illustrating a semiconductor device according to a first embodiment of the present invention, in which FIG. 1A is a plan view in which a part of a package is cut away, and FIG. 1B is a line AA in FIG. FIG. 1C is a side view of the cross-sectional view taken along the line and viewed in the direction of the arrow. 本発明の実施例１に係る半導体装置を示す斜視図。1 is a perspective view showing a semiconductor device according to Embodiment 1 of the present invention. 本発明の実施例１に係る半導体装置の特性を比較例と対比して示す図で、図３（ａ）が本実施例の半導体装置の特性を示す図、図３（ｂ）が比較例の半導体装置の特性を示す図。FIG. 3A is a diagram showing characteristics of the semiconductor device according to Example 1 of the present invention in comparison with a comparative example, FIG. 3A is a diagram showing characteristics of the semiconductor device of this example, and FIG. FIG. 6 shows characteristics of a semiconductor device. 本発明の実施例１に係る半導体装置の製造工程を順に示す断面図。Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 1 of this invention in order. 本発明の実施例１に係る半導体装置の製造工程を順に示す断面図。Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 1 of this invention in order. 本発明の実施例１に係る半導体装置の製造工程を順に示す断面図。Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 1 of this invention in order. 本発明の実施例１に係る半導体装置の製造工程を順に示す断面図。Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 1 of this invention in order. 本発明の実施例１に係る半導体装置が基板に実装された状態を示す断面図。Sectional drawing which shows the state by which the semiconductor device which concerns on Example 1 of this invention was mounted in the board | substrate. 本発明の実施例１に係る半導体装置を示す図で、図９（ａ）はパッケージの一部が切り欠きされたその平面図、図９（ｂ）は図９（ａ）のＢ−Ｂ線に沿って切断し、矢印の方向に眺めた断面図、図９（ｃ）はその側面図。9A and 9B are diagrams illustrating a semiconductor device according to Example 1 of the present invention, in which FIG. 9A is a plan view in which a part of the package is cut out, and FIG. 9B is a BB line in FIG. FIG. 9C is a side view of the cross-sectional view of FIG. 本発明の実施例２に係る半導体装置の製造工程の要部を順に示す断面図。Sectional drawing which shows in order the principal part of the manufacturing process of the semiconductor device which concerns on Example 2 of this invention. 本発明の実施例３に係る半導体装置を示す断面図。Sectional drawing which shows the semiconductor device which concerns on Example 3 of this invention. 本発明の実施例３に係る半導体装置の製造工程の要部を順に示す断面図。Sectional drawing which shows the principal part of the manufacturing process of the semiconductor device which concerns on Example 3 of this invention in order. 本発明の実施例４に係る半導体装置を示す図で、図１３（ａ）はパッケージの一部が切り欠きされたその平面図、図１３（ｂ）は図１３（ａ）のＣ−Ｃ線に沿って切断し、矢印の方向に眺めた断面図。FIGS. 13A and 13B are views showing a semiconductor device according to a fourth embodiment of the present invention, in which FIG. 13A is a plan view in which a part of the package is cut out, and FIG. 13B is a CC line in FIG. Sectional drawing cut | disconnected along and seen in the direction of the arrow. 本発明の実施例４に係る別の半導体装置を示す図で、パッケージの一部が切り欠きされたその平面図。FIG. 11 is a plan view showing another semiconductor device according to Embodiment 4 of the present invention, in which a part of the package is cut away; 本発明の実施例５に係る半導体装置を示す図で、図１５（ａ）はパッケージの一部が切り欠きされたその平面図、図１５（ｂ）は図１５（ａ）のＤ−Ｄ線に沿って切断し、矢印の方向に眺めた断面図、図１５（ｃ）は図１５（ａ）のＥ−Ｅ線に沿って切断し、矢印の方向に眺めた断面図。FIGS. 15A and 15B are diagrams showing a semiconductor device according to a fifth embodiment of the present invention, in which FIG. 15A is a plan view in which a part of the package is cut away, and FIG. 15B is a DD line in FIG. FIG. 15C is a cross-sectional view taken along the line E-E in FIG. 15A and viewed in the direction of the arrow.

符号の説明Explanation of symbols

１０、３０、６０、７０、８０、８７、９０ 半導体装置
１１ 第１電極リード
１２ 第２電極リード
１３、８４ 半導体チップ
１４、４１、８８ 樹脂
１５、８３ 配線
１６、８５、８６ 金属電極層
３１ ワイヤ
３２、６１、８２、９２ 樹脂
３３、３４、６２ 放熱
４０ 半導体装置用基板
４２ 第２貫通孔
４３ 第１貫通孔
４４ レジスト膜
４５ シート
４６ ブレード
５０ 配線基板
５１、５２ 配線パターン
５３、５４ 接続端子
７１ バンプ
８１ 第３電極リード
９１ 溝 10, 30, 60, 70, 80, 87, 90 Semiconductor device 11 First electrode lead 12 Second electrode lead 13, 84 Semiconductor chip 14, 41, 88 Resin 15, 83 Wiring 16, 85, 86 Metal electrode layer 31 Wire 32, 61, 82, 92 Resin 33, 34, 62 Heat dissipation 40 Semiconductor device substrate 42 Second through hole 43 First through hole 44 Resist film 45 Sheet 46 Blade 50 Wiring substrate 51, 52 Wiring pattern 53, 54 Connection terminal 71 Bump 81 Third electrode lead 91 Groove

Claims (5)

離間して配置された第１および第２電極リードと、
前記第１電極リードの第１の面に載置された半導体チップと、
前記第１電極リードの前記第１の面と対向する面、および前記第２電極リードの第１の面と対向する面をそれぞれ露出させて、前記第１電極リード、前記第２電極リードおよび前記半導体チップを封止する樹脂と、
前記樹脂上に形成され、一方が前記樹脂の前記半導体チップに対応する部位を貫通して前記半導体チップに接続され、他方が前記樹脂の前記第２電極リードに対応する部位を貫通して前記第２電極リードに接続された配線と、
を具備することを特徴とする半導体装置。 First and second electrode leads spaced apart;
A semiconductor chip mounted on the first surface of the first electrode lead;
The surface facing the first surface of the first electrode lead and the surface facing the first surface of the second electrode lead are respectively exposed, and the first electrode lead, the second electrode lead, and the A resin for sealing the semiconductor chip;
Formed on the resin, one passing through a portion of the resin corresponding to the semiconductor chip and connected to the semiconductor chip, and the other passing through a portion of the resin corresponding to the second electrode lead Wiring connected to a two-electrode lead;
A semiconductor device comprising: 前記第２電極リードの前記第１電極リードと反対側の端部が前記樹脂の側面に露出し、前記配線の前記他方が前記樹脂の側面に沿って露出し、前記第２電極リードの前記端部に接続されていることを特徴とする請求項１に記載の半導体装置。   The end of the second electrode lead opposite to the first electrode lead is exposed on the side surface of the resin, the other end of the wiring is exposed along the side surface of the resin, and the end of the second electrode lead is exposed. The semiconductor device according to claim 1, wherein the semiconductor device is connected to a portion. 前記第１および第２電極リードと離間して配置された第３電極リードと、
前記樹脂上に形成され、一方が前記樹脂の前記半導体チップに接続され、他方が前記第３電極リードに接続された配線と、
を更に具備することを特徴とする請求項１または請求項２に記載の半導体装置。 A third electrode lead spaced apart from the first and second electrode leads;
A wiring formed on the resin, one connected to the semiconductor chip of the resin and the other connected to the third electrode lead;
The semiconductor device according to claim 1, further comprising: 前記半導体チップ上にバンプが形成され、前記配線の一方が前記バンプを介して前記半導体チップに接続されていることを特徴とする請求項１乃至請求項３に記載の半導体装置。   4. The semiconductor device according to claim 1, wherein bumps are formed on the semiconductor chip, and one of the wirings is connected to the semiconductor chip via the bumps. 前記配線が、前記樹脂の上面に形成された溝に埋め込まれていることを特徴とする請求項１乃至請求項４に記載の半導体装置。   The semiconductor device according to claim 1, wherein the wiring is embedded in a groove formed on an upper surface of the resin.
JP2008213353A 2008-08-21 2008-08-21 Semiconductor device Pending JP2010050286A (en)

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