JP4710131B2 - Semiconductor device - Google Patents

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Publication number
JP4710131B2
JP4710131B2 JP2000389625A JP2000389625A JP4710131B2 JP 4710131 B2 JP4710131 B2 JP 4710131B2 JP 2000389625 A JP2000389625 A JP 2000389625A JP 2000389625 A JP2000389625 A JP 2000389625A JP 4710131 B2 JP4710131 B2 JP 4710131B2
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pad
semiconductor device
anode
cathode
gate
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JP2002190531A (en
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昌吾 森
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Toyota Industries Corp
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Toyota Industries Corp
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置に関し、特に半導体素子の温度を検出することができる半導体装置に係る。
【０００２】
【従来の技術】
従来より、過電流等から半導体素子を保護するために半導体素子を含む半導体装置に温度検出機能を設ける技術はよく知られている。この温度検出機能は、例えば、半導体素子の近くに温度検出用ダイオードを設け、そのダイオードに発生する電圧を検出することにより行われている。このとき、ダイオードの順方向電流−電圧特性が温度に依存して変化することが利用される。
【０００３】
上記電流検出機能を備える半導体装置は、例えば、特開平７−１５３９２０号公報に記載されている。ここで、この半導体装置は、ＭＯＳ型電界効果トランジスタ（以下、ＭＯＳＦＥＴ）、及びそのＭＯＳＦＥＴの近傍に形成されるポリシリコンダイオードを含む。そして、このダイオードに電流を流しながらその順方向電圧を測定することにより、その周辺の温度を検出する。
【０００４】
【発明が解決しようとする課題】
ところで、半導体素子の過電流を監視するためには、基本的に、その半導体素子の近傍の温度を検出する必要がある。すなわち、上記構成の半導体装置においては、温度検出用ダイオードが半導体素子の近くに形成されることが望ましい。そして、このように半導体素子および温度検出用ダイオードが互いに近接して形成されると、半導体素子が形成される半導体チップの中央部に、半導体素子の電極パッド、および温度検出用ダイオードの電極パッドが集中することになる。
【０００５】
この結果、半導体チップ上に設けられている各電極パッドにそれぞれ接続されるボンディングワイヤ同士の間隔が互いに近接し、場合によっては、それらのワイヤ同士が互いに接触してしまうおそれが生じる。そして、もし、ＭＯＳＦＥＴのゲートに接続されるゲートワイヤと他のワイヤとが接触すると、そのＭＯＳＦＥＴに誤った制御信号が与えられることになり、誤動作を引き起こす可能性がある。ここで、上述の温度検出用ダイオードは、通常、その順方向に電流が流れているので、アノードの電位は一定値以上に保持されている。したがって、もし、ＭＯＳＦＥＴのゲートワイヤと温度検出用ダイオードのアノードワイヤとが接触すると、このＭＯＳＦＥＴが誤動作（この場合、実際のゲート信号にかかわらずＭＯＳＦＥＴが継続的にＯＮ状態になる誤動作）を起こす可能性がある。
【０００６】
本発明は、上記の課題に鑑み、トランジスタおよび温度検出用ダイオードを備える半導体装置において、ボンディングワイヤ同士の接触によるトランジスタの誤作動を防止することを目的とする。
【０００７】
【課題を解決するための手段】
本発明の半導体装置は、同一半導体チップ内に形成されたトランジスタおよび温度検出用ダイオードを含み、前記トランジスタの入力端子パッドと前記温度検出用ダイオードのアノードパッドとの間に、前記温度検出用ダイオードのカソードパッドが配置される。
【０００８】
上記構成の半導体装置において、温度検出時には、温度検出用ダイオードに順方向電流が流れるので、アノードの電位は一定値以上の値に保持され、カソードの電位は所定の低い電位に保持される。
そして、上記構成においては、入力端子パッドから引き出されるボンディングワイヤと、アノードパッドから引き出されるボンディングワイヤとが互いに接触することはない。したがって、トランジスタの入力端子パッドにアノード電位が印加されることはなく、トランジスタが誤ってＯＮ状態に制御されることは回避される。一方、入力端子パッドから引き出されるボンディングワイヤと、カソードパッドから引き出されるボンディングワイヤとが互いに接触する可能性は残る。しかし、基本的にカソードの電位は低いので、トランジスタの入力端子パッドにカソード電位が印加されたとしても、トランジスタが誤ってＯＮ状態に制御されることはない（フェールセーフ）。
【０００９】
【発明の実施の形態】
以下、本発明の実施の形態を図面を用いて説明する。なお、本実施形態の半導体装置は、同一半導体チップ内にＭＯＳ型電界効果トランジスタ（以下、ＭＯＳＦＥＴ）、及び温度検出用ダイオードを含む構成である。
第１の実施形態
第１の実施形態としては、半導体チップが回路基板に実装された半導体装置を示す。
【００１０】
図１は、第１の実施形態の半導体装置を上方から見た図である。同図において、回路基板１は、例えば、予め配線パターンが形成されているプリント基板であり、その上に半導体チップ２が実装される。この実施例では、回路基板１には、ソースパターンＳ、ドレインパターンＤ、ゲートパターンＧ、アノードパターンＡ、およびカソードパターンＫが形成されている。
【００１１】
半導体チップ２には、ＭＯＳＦＥＴおよび温度検出用ダイオードが形成されている。そして、この半導体チップ２の上面には、ＭＯＳＦＥＴのソース領域に接続するソースパッド３、ＭＯＳＦＥＴのゲート領域に接続するゲートパッド４、温度検出用ダイオードのアノード領域に接続するアノードパッド５、および温度検出用ダイオードのカソード領域に接続するカソードパッド６が形成されている。ここで、ゲートパッド４、アノードパッド５、およびカソードパッド６は、互いに近接して配置される。ただし、ゲートパッド４およびアノードパッド５は、互いに隣り合わないように配置される。具体的には、ゲートパッド４およびアノードパッド５が互いに所定間隔離れて配置され、それらの間にカソードパッド６が配置される。一方、半導体チップ２の底面は、特に図示しないが、ドレイン領域である。そして、そのドレイン領域がドレインパターンＤに電気的に接続されている。
【００１２】
半導体チップ２の各電極パッドは、ボンディングワイヤにより回路基板１の対応するパターンに接続されている。すなわち、ソースパッド３はソースワイヤ７によりソースパターンＳに接続され、ゲートパッド４はゲートワイヤ８によりゲートパターンＧに接続され、アノードパッド５はアノードワイヤ９によりアノードパターンＡに接続され、そして、カソードパッド６はカソードワイヤ１０によりカソードパターンＫに接続される。
【００１３】
図２は、上記半導体装置の回路を示す図である。ＭＯＳＦＥＴは、例えば、大電流を流すことができるパワーＭＯＳＦＥＴであり、ゲートに所定値以上の電位が印加されたときにＯＮ状態に制御される。温度検出用ダイオードは、１または複数のダイオードから構成され、ＭＯＳＦＥＴの近傍に形成される。なお、温度検出用ダイオードが複数のダイオードから構成される場合は、それらのダイオードが直列的に接続される。
【００１４】
上記構成の半導体装置において、ＭＯＳＦＥＴは、そのゲートに与えられる電位に従ってＯＮ／ＯＦＦ制御される。一方、温度検出用ダイオードには、常に、順方向電流が流れている。このとき、カソードは、接地レベルまたはそれに近いレベルに保持されている。また、アノードは、各ダイオードの順方向電圧および直列に接続されているダイオードの個数に依存する電位となる。例えば、各ダイオードの順方向電圧が約１Ｖであり、５個のダイオードが直列に接続されている場合には、温度検出用ダイオードのアノードの電位は、５Ｖ程度となる。
【００１５】
上記構成において、ＭＯＳＦＥＴまたはその周辺の温度は、アノード／カソード間の電圧を測定することにより検出される。そして、この電位が所定値を下回った場合、ＭＯＳＦＥＴの過電流などにより温度が上昇しているものとみなし、対応する制御（例えば、ＭＯＳＦＥＴを強制的にＯＦＦ状態にする制御）が行われる。
【００１６】
図１に戻る。本実施形態の半導体装置においては、ゲートパッド４とアノードパッド５との間にカソードパッド６が配置されている。したがって、ゲートパッド４から引き出されるゲートワイヤ８と、アノードパッド５から引き出されるアノードワイヤ９とが互いに接触することはない。したがって、ＭＯＳＦＥＴのゲートにアノード電位が印加されることはなく、ＭＯＳＦＥＴが誤ってＯＮ状態に制御されることはない。一方、本実施形態の半導体装置においては、ゲートパッド４とカソードパッド６とが隣り合っているので、ゲートパッド４から引き出されるゲートワイヤ８と、カソードパッド６から引き出されるカソードワイヤ１０とが互いに接触する可能性は残る。しかし、カソードの電位は、接地レベルまたはそれに近いレベルに保持されているので、ＭＯＳＦＥＴのゲートにカソード電位が印加されたとしても、ＭＯＳＦＥＴが誤ってＯＮ状態に制御されることはない。これにより、フェールセーフが実現される。
第２の実施形態
第２の実施形態としては、半導体チップがパッケージ２０に実装された半導体装置を示す。以下、図３を参照しながら、第２の実施形態の半導体装置について説明する。なお、第２の実施形態の半導体装置の回路は、第１実施形態と同じであり、図２に示した通りである。
【００１７】
第２の実施形態の半導体装置では、各電極パッドから引き出されるボンディングワイヤは、対応する電極端子に接続される。具体的には、図３に示すように、ソースパッド３はソースワイヤ７によりソース電極Ｓに接続され、ゲートパッド４はゲートワイヤ８によりゲート電極Ｇに接続され、アノードパッド５はアノードワイヤ９によりアノード電極Ａに接続され、そして、カソードパッド６はカソードワイヤ１０によりカソード電極Ｋに接続される。ここで、これらの電極は、それぞれその先端部がパッケージ２０から突出するように形成されている。なお、半導体チップ２の底面は、ドレイン電極Ｄに電気的に接続されている。
【００１８】
第２の実施形態において、ゲートパッド４、アノードパッド５、およびカソードパッド６の配置は、基本的に、第１の実施形態と同じである。すなわち、ゲートパッド４およびアノードパッド５が互いに所定間隔離れて配置され、それらの間にカソードパッド６が配置されている。そして、この構成により、第１の実施形態と同様の効果が得られる。
【００１９】
なお、上述の実施例では、ゲートパッド４、カソードパッド６、アノードパッド５がこの順番で直線的に並べられているが、本発明はこれに限定されるものではなく、これらのパッドは必ずしも直線上に並べられる必要はない。
また、上述の実施例の半導体装置では、半導体チップの底面がドレイン領域となる構成であるが、本発明は、半導体チップの表面にドレイン領域が形成される構成にも適用することができる。
【００２０】
さらに、上述の実施例の半導体装置は、パワーＭＯＳＦＥＴおよび温度検出用ダイオードを含む構成であるが、本発明は、バイポーラトランジスタやＩＧＢＴなどの他の半導体素子および温度検出用ダイオードを含む構成にも適用可能である。
【００２１】
【発明の効果】
本発明によれば、トランジスタの入力端子ワイヤに温度検出用ダイオードのアノードワイヤが接触することがないので、そのトランジスタが誤動作によりＯＮ状態に制御されることが回避される。トランジスタの近くに温度検出用ダイオードを設けることができるので、トランジスタの温度上昇を的確に検出できる。
【図面の簡単な説明】
【図１】第１の実施形態の半導体装置を上方から見た図である。
【図２】第１の実施形態の半導体装置の回路を示す図である。
【図３】第２の実施形態の半導体装置を上方から見た図である。
【符号の説明】
１ 回路基板
２ 半導体チップ
３ ソースパッド
４ ゲートパッド
５ アノードパッド
６ カソードパッド
７ ソースワイヤ
８ ゲートワイヤ
９ アノードワイヤ
１０ カソードワイヤ
２０ パッケージ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of detecting the temperature of a semiconductor element.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a technique for providing a temperature detection function to a semiconductor device including a semiconductor element in order to protect the semiconductor element from overcurrent or the like is well known. This temperature detection function is performed, for example, by providing a temperature detection diode near the semiconductor element and detecting a voltage generated in the diode. At this time, it is utilized that the forward current-voltage characteristic of the diode changes depending on the temperature.
[0003]
A semiconductor device having the current detection function is described in, for example, Japanese Patent Laid-Open No. 7-153920. Here, the semiconductor device includes a MOS field effect transistor (hereinafter referred to as MOSFET) and a polysilicon diode formed in the vicinity of the MOSFET. And the temperature of the circumference | surroundings is detected by measuring the forward voltage, sending an electric current through this diode.
[0004]
[Problems to be solved by the invention]
Incidentally, in order to monitor an overcurrent of a semiconductor element, it is basically necessary to detect the temperature in the vicinity of the semiconductor element. That is, in the semiconductor device having the above configuration, it is desirable that the temperature detection diode be formed near the semiconductor element. When the semiconductor element and the temperature detecting diode are formed close to each other in this way, the electrode pad of the semiconductor element and the electrode pad of the temperature detecting diode are formed at the center of the semiconductor chip where the semiconductor element is formed. To concentrate.
[0005]
As a result, the bonding wires connected to the electrode pads provided on the semiconductor chip are close to each other, and in some cases, the wires may come into contact with each other. If the gate wire connected to the gate of the MOSFET contacts another wire, an incorrect control signal is given to the MOSFET, which may cause a malfunction. Here, in the above-described temperature detection diode, since the current normally flows in the forward direction, the potential of the anode is maintained at a certain value or more. Therefore, if the gate wire of the MOSFET and the anode wire of the temperature detection diode come into contact with each other, this MOSFET may malfunction (in this case, the malfunction in which the MOSFET is continuously turned on regardless of the actual gate signal). There is sex.
[0006]
In view of the above problems, an object of the present invention is to prevent malfunction of a transistor due to contact between bonding wires in a semiconductor device including a transistor and a temperature detection diode.
[0007]
[Means for Solving the Problems]
The semiconductor device of the present invention includes a transistor and a temperature detection diode formed in the same semiconductor chip, and the temperature detection diode is interposed between an input terminal pad of the transistor and an anode pad of the temperature detection diode. A cathode pad is disposed.
[0008]
In the semiconductor device having the above configuration, when a temperature is detected, a forward current flows through the temperature detection diode, so that the anode potential is held at a value equal to or higher than a predetermined value, and the cathode potential is held at a predetermined low potential.
In the above configuration, the bonding wire drawn from the input terminal pad and the bonding wire drawn from the anode pad do not contact each other. Therefore, the anode potential is not applied to the input terminal pad of the transistor, and it is avoided that the transistor is erroneously controlled to be in the ON state. On the other hand, there remains a possibility that the bonding wire drawn from the input terminal pad and the bonding wire drawn from the cathode pad contact each other. However, since the cathode potential is basically low, even if the cathode potential is applied to the input terminal pad of the transistor, the transistor is not erroneously controlled to be in the ON state (fail safe).
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the semiconductor device of the present embodiment is configured to include a MOS field effect transistor (hereinafter referred to as MOSFET) and a temperature detection diode in the same semiconductor chip.
First embodiment A first embodiment shows a semiconductor device in which a semiconductor chip is mounted on a circuit board.
[0010]
FIG. 1 is a top view of the semiconductor device according to the first embodiment. In the figure, a circuit board 1 is, for example, a printed board on which a wiring pattern is formed in advance, and a semiconductor chip 2 is mounted thereon. In this embodiment, a source pattern S, a drain pattern D, a gate pattern G, an anode pattern A, and a cathode pattern K are formed on the circuit board 1.
[0011]
On the semiconductor chip 2, a MOSFET and a temperature detection diode are formed. On the upper surface of the semiconductor chip 2, a source pad 3 connected to the source region of the MOSFET, a gate pad 4 connected to the gate region of the MOSFET, an anode pad 5 connected to the anode region of the temperature detection diode, and temperature detection A cathode pad 6 connected to the cathode region of the diode is formed. Here, the gate pad 4, the anode pad 5, and the cathode pad 6 are disposed close to each other. However, the gate pad 4 and the anode pad 5 are arranged so as not to be adjacent to each other. Specifically, the gate pad 4 and the anode pad 5 are disposed at a predetermined distance from each other, and the cathode pad 6 is disposed therebetween. On the other hand, the bottom surface of the semiconductor chip 2 is a drain region (not shown). The drain region is electrically connected to the drain pattern D.
[0012]
Each electrode pad of the semiconductor chip 2 is connected to a corresponding pattern on the circuit board 1 by a bonding wire. That is, the source pad 3 is connected to the source pattern S by the source wire 7, the gate pad 4 is connected to the gate pattern G by the gate wire 8, the anode pad 5 is connected to the anode pattern A by the anode wire 9, and the cathode The pad 6 is connected to the cathode pattern K by the cathode wire 10.
[0013]
FIG. 2 is a diagram illustrating a circuit of the semiconductor device. The MOSFET is, for example, a power MOSFET that can flow a large current, and is controlled to be in an ON state when a potential higher than a predetermined value is applied to the gate. The temperature detection diode is composed of one or a plurality of diodes and is formed in the vicinity of the MOSFET. When the temperature detection diode is composed of a plurality of diodes, these diodes are connected in series.
[0014]
In the semiconductor device having the above configuration, the MOSFET is ON / OFF controlled according to the potential applied to the gate. On the other hand, a forward current always flows through the temperature detection diode. At this time, the cathode is held at or near the ground level. The anode has a potential that depends on the forward voltage of each diode and the number of diodes connected in series. For example, when the forward voltage of each diode is about 1V and five diodes are connected in series, the potential of the anode of the temperature detection diode is about 5V.
[0015]
In the above configuration, the temperature of the MOSFET or its surroundings is detected by measuring the voltage between the anode and the cathode. When this potential falls below a predetermined value, it is considered that the temperature has risen due to overcurrent of the MOSFET, and corresponding control (for example, control for forcibly turning off the MOSFET) is performed.
[0016]
Returning to FIG. In the semiconductor device of this embodiment, a cathode pad 6 is disposed between the gate pad 4 and the anode pad 5. Therefore, the gate wire 8 drawn from the gate pad 4 and the anode wire 9 drawn from the anode pad 5 do not contact each other. Therefore, the anode potential is not applied to the gate of the MOSFET, and the MOSFET is not erroneously controlled to be in the ON state. On the other hand, in the semiconductor device of this embodiment, since the gate pad 4 and the cathode pad 6 are adjacent to each other, the gate wire 8 drawn from the gate pad 4 and the cathode wire 10 drawn from the cathode pad 6 are in contact with each other. The possibility remains. However, since the potential of the cathode is held at or near the ground level, even if the cathode potential is applied to the gate of the MOSFET, the MOSFET is not erroneously controlled to the ON state. Thereby, fail safe is realized.
Second Embodiment As a second embodiment, a semiconductor device in which a semiconductor chip is mounted on a package 20 is shown. The semiconductor device according to the second embodiment will be described below with reference to FIG. The circuit of the semiconductor device of the second embodiment is the same as that of the first embodiment, as shown in FIG.
[0017]
In the semiconductor device of the second embodiment, the bonding wires drawn from each electrode pad are connected to the corresponding electrode terminals. Specifically, as shown in FIG. 3, the source pad 3 is connected to the source electrode S by the source wire 7, the gate pad 4 is connected to the gate electrode G by the gate wire 8, and the anode pad 5 is connected by the anode wire 9. Connected to the anode electrode A, and the cathode pad 6 is connected to the cathode electrode K by the cathode wire 10. Here, each of these electrodes is formed such that its tip portion protrudes from the package 20. The bottom surface of the semiconductor chip 2 is electrically connected to the drain electrode D.
[0018]
In the second embodiment, the arrangement of the gate pad 4, the anode pad 5, and the cathode pad 6 is basically the same as that of the first embodiment. That is, the gate pad 4 and the anode pad 5 are arranged at a predetermined distance from each other, and the cathode pad 6 is arranged between them. With this configuration, the same effect as in the first embodiment can be obtained.
[0019]
In the above-described embodiment, the gate pad 4, the cathode pad 6, and the anode pad 5 are linearly arranged in this order, but the present invention is not limited to this, and these pads are not necessarily linear. There is no need to line up.
In the semiconductor device of the above-described embodiment, the bottom surface of the semiconductor chip is the drain region. However, the present invention can also be applied to a configuration in which the drain region is formed on the surface of the semiconductor chip.
[0020]
Furthermore, although the semiconductor device of the above-mentioned embodiment has a configuration including a power MOSFET and a temperature detection diode, the present invention is also applicable to a configuration including another semiconductor element such as a bipolar transistor or IGBT and a temperature detection diode. Is possible.
[0021]
【The invention's effect】
According to the present invention, since the anode wire of the temperature detecting diode does not contact the input terminal wire of the transistor, it is possible to avoid that the transistor is controlled to be in the ON state due to a malfunction. Since the temperature detecting diode can be provided near the transistor, an increase in the temperature of the transistor can be accurately detected.
[Brief description of the drawings]
FIG. 1 is a diagram of a semiconductor device according to a first embodiment viewed from above.
FIG. 2 is a diagram illustrating a circuit of the semiconductor device of the first embodiment.
FIG. 3 is a diagram of a semiconductor device according to a second embodiment viewed from above.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Circuit board 2 Semiconductor chip 3 Source pad 4 Gate pad 5 Anode pad 6 Cathode pad 7 Source wire 8 Gate wire 9 Anode wire 10 Cathode wire 20 Package

Claims (2)

同一半導体チップ内に形成されたトランジスタおよび温度検出用ダイオードを含む半導体装置において、
前記トランジスタの入力端子パッドと前記温度検出用ダイオードのアノードパッドとの間に前記温度検出用ダイオードのカソードパッドが配置され、
前記入力端子パッド、カソードパッド、およびアノードパッドは、互いに近接して配置されるとともに前記半導体チップの中央部に集中して配置されることを特徴とする半導体装置。In a semiconductor device including a transistor and a temperature detection diode formed in the same semiconductor chip,
A cathode pad of the temperature detection diode is disposed between an input terminal pad of the transistor and an anode pad of the temperature detection diode ;
Said input terminal pad, cathode pad and the anode pad, a semiconductor device according to claim Rukoto arranged concentrated in the central portion of the semiconductor chip while being disposed close to each other. 前記トランジスタは、ＭＯＳＦＥＴであることを特徴とする請求項１に記載の半導体装置。The semiconductor device according to claim 1, wherein the transistor is a MOSFET.
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JPH03188661A (en) * 1989-12-18 1991-08-16 Toshiba Corp Resin seal type semiconductor device
JPH06342876A (en) * 1992-10-06 1994-12-13 Matsushita Electron Corp Semiconductor device
JPH08213441A (en) * 1995-01-31 1996-08-20 Nec Corp Method of temperature detection by use of diode froward voltage
JP2000031290A (en) * 1998-07-10 2000-01-28 Nissan Motor Co Ltd Semiconductor device
JP2000058820A (en) * 1998-08-07 2000-02-25 Hitachi Ltd Power semiconductor element and power module

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03188661A (en) * 1989-12-18 1991-08-16 Toshiba Corp Resin seal type semiconductor device
JPH06342876A (en) * 1992-10-06 1994-12-13 Matsushita Electron Corp Semiconductor device
JPH08213441A (en) * 1995-01-31 1996-08-20 Nec Corp Method of temperature detection by use of diode froward voltage
JP2000031290A (en) * 1998-07-10 2000-01-28 Nissan Motor Co Ltd Semiconductor device
JP2000058820A (en) * 1998-08-07 2000-02-25 Hitachi Ltd Power semiconductor element and power module

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