JP5713658B2 - Driving circuit and driving method for electro-optical device - Google Patents

Description

  The present invention relates to a drive circuit and a drive method for an electro-optical device.

  In an active matrix electro-optical device including a liquid crystal display element, a pixel capacitor (liquid crystal capacitor) is provided corresponding to the intersection of a scanning line and a data line. When this pixel capacitor is AC driven, the common electrode is individualized for each scanning line in order to suppress the voltage amplitude of the data line, and when the scanning line is selected, the common electrode corresponding to the selected scanning line is written. A technique is known in which one of binary voltages according to polarity is used.

  The gate circuit for driving the gate line sequentially selects TFT switches connected to the gate line in one scanning period, and supplies a desired data voltage to the liquid crystal capacitor from the source drive circuit for driving the source electrode. Write. After writing the data voltage, by superimposing a predetermined voltage from the storage capacitor drive circuit for driving the storage capacitor line, the data written in the liquid crystal capacitor becomes a desired voltage suitable for the optical characteristics of the liquid crystal. The voltage is converted and maintained until the data voltage is updated again in the next frame. Such a driving method of the electro-optical device is also called independent capacitive coupling driving because the storage capacitor is driven independently, and is described in, for example, Patent Documents 1 and 2, for example. In this configuration, a constant DC voltage can be applied to the common voltage and the amplitude of the data voltage can be reduced as compared with the conventional driving method for inverting the common electrode. It is known as an effective driving method for the conversion.

JP 2002-196358 A JP 2009-223173 A

  However, in the conventional driving method, the distortion of the source line voltage signal is superimposed on the storage capacitor line due to the influence of the parasitic capacitance existing between the source line and the storage capacitor line. The distortion of the signal appears as the distortion of the waveform of the storage capacitor line voltage. Normally, the source line is inverted every scanning period, and the voltage amplitude also changes according to the data to be written. Therefore, the waveform distortion generated in the storage capacitor line changes depending on the display data. Similarly, since parasitic capacitance exists also between the gate line and the storage capacitor line, the waveform of the storage capacitor line voltage appears even when the gate line rises and falls. These voltage fluctuations of the storage capacitor line affect the pixel voltage via the storage capacitor, and as a result, a desired pixel voltage cannot be obtained, resulting in crosstalk (brightness unevenness) and deterioration of image quality. There was a problem.

  As means for reducing this crosstalk, there are, for example, improvement of process design such as reduction of the parasitic capacitance and reduction of resistance of the wiring, and improvement of power supply capability of the storage capacitor line. There is a problem that the size of the display area (so-called frame area) is increased due to complication or an increase in the buffer size of the storage capacitor driving circuit, and such measures can be taken particularly in a medium-to-small electro-optical device. There was a problem that it was difficult.

  Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to improve display quality and achieve low power consumption without requiring a large size increase. Another object of the present invention is to provide a new and improved electro-optical device driving circuit and driving method.

  In order to solve the above problems, according to an aspect of the present invention, a plurality of gate lines, a plurality of source lines, a plurality of storage capacitor lines provided corresponding to the plurality of gate lines, and the plurality And a common electrode, one end of which is connected to the source line, and the one end and the other end when the gate line is selected. And a plurality of pixels including a pixel switching element that is turned on between the pixel switching element and a pixel capacitor having one end connected to the other end of the pixel switching element and the other end connected to the common electrode. And a gate circuit that selects the plurality of gate lines in a predetermined order and supplies a predetermined voltage to the storage capacitor line, and a pixel corresponding to the one source line, Gradation and pole And a source driver circuit that supplies a data signal having a voltage corresponding to the source line via the source line, and a display area including the plurality of pixels. A storage capacitor driving circuit for supplying a voltage, and the storage capacitor line is supplied with a predetermined voltage for a predetermined period from the gate circuit and the storage capacitor driving circuit, and the gate circuit has an nth gate. A predetermined voltage is supplied to the nth storage capacitor line only in a period from the selection of the line to the selection of the (n + 1) th gate line after the lapse of the selected period. A drive circuit for the electro-optical device is provided.

  The gate circuit supplies a predetermined voltage to the nth storage capacitor line only in a period from the selection of the nth gate line to the selection of the (n + 1) th gate line after the selection period has elapsed. To do.

  The storage capacitor line is electrically disconnected and independently driven from the common electrode connected to one end of the pixel capacitor constituting the pixel, and a predetermined data voltage is applied while the gate line is selected. The pixel potential that is the potential on the opposite side of the common electrode of the pixel is shifted to the high voltage side or the low voltage side by the storage capacitor driving circuit at a timing delayed by a predetermined period after being applied to the pixel. Thus, the final pixel potential is determined.

  The voltage applied from the gate circuit and the storage capacitor drive circuit to the storage capacitor line is equal to the voltage before the pixel potential is shifted by the storage capacitor drive circuit.

  In order to solve the above problem, according to another aspect of the present invention, a plurality of gate lines, a plurality of source lines, and a plurality of storage capacitor lines provided corresponding to the plurality of gate lines, , Provided corresponding to the intersection of the plurality of gate lines and the plurality of source lines, and connected to the common electrode and one end thereof to the source line, and the one end and the other when the gate line is selected. And a pixel switching element that is turned on between the pixel switching element and a pixel capacitor having one end connected to the other end of the pixel switching element and the other end connected to the common electrode. A driving method of an apparatus, comprising: a gate circuit that selects a plurality of gate lines in a predetermined order and supplies a predetermined voltage to the storage capacitor line; and a pixel corresponding to the one source line Tones and poles And a source driver circuit that supplies a data signal having a voltage corresponding to the source line via the source line, and a display area including the plurality of pixels. A storage capacitor driving circuit for supplying a voltage, and the storage capacitor line is supplied with a predetermined voltage in a predetermined period from the gate circuit and the storage capacitor driving circuit, by the driving circuit of the electro-optical device, The gate circuit applies a predetermined voltage to the nth storage capacitor line only during the period from the selection of the nth gate line to the selection of the (n + 1) th gate line after the selected period has elapsed. An electro-optical device driving method is provided.

  As described above, according to the present invention, a novel and improved drive circuit and drive method for an electro-optical device that can improve display quality and achieve low power consumption without requiring a large increase in size. Can be provided.

1 is an explanatory diagram illustrating a configuration of an electro-optical device 100 using a liquid crystal display element according to a first embodiment of the present invention. FIG. 6 is an explanatory diagram illustrating a drive waveform when attention is paid to the pixel of the electro-optical device according to the first embodiment of the present invention. FIG. 6 is an explanatory diagram showing a change in potential of the electro-optical device 100 according to the first embodiment of the present invention. It is explanatory drawing shown about the structure of the electro-optical apparatus 200 using the liquid crystal display element concerning the 2nd Embodiment of this invention. FIG. 10 is an explanatory diagram illustrating a change in potential of an electro-optical device according to a second embodiment of the present invention. It is explanatory drawing shown about the structure of the drive circuit of the conventional electro-optical apparatus. It is explanatory drawing showing the distortion of the waveform of storage capacity | capacitance line C1, C2, ..., Cn. It is explanatory drawing which shows what reflected the parasitic capacitance in the pixel with a circuit diagram. It is explanatory drawing which shows generation | occurrence | production of the brightness nonuniformity in the conventional electro-optical apparatus.

  Exemplary embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In addition, in this specification and drawing, about the component which has the substantially same function structure, duplication description is abbreviate | omitted by attaching | subjecting the same code | symbol.

<1. Conventional Electro-Optical Device Driving Method and Problems>
First, a method of driving an electro-optical device using a conventional liquid crystal display element and its problems will be described with reference to the drawings. FIG. 6 is an explanatory diagram illustrating a configuration of a driving circuit of a conventional electro-optical device.

  As shown in FIG. 6, the conventional electro-optical device 300 includes a gate circuit 301, a storage capacitor driving circuit 302, a source driving circuit 303, and a common driving circuit 304. The electro-optical device 300 includes gate lines G1, G2,... Gn formed by arranging a plurality of electrodes in the horizontal direction and source lines S1, S2,. Sm and storage capacitor lines C1, C2,... Cn formed by arranging a plurality of electrodes in the horizontal direction. The conventional electro-optical device 300 includes a plurality of pixels 306 arranged in a matrix at each intersection of the gate line and the source line in the display region 305, and each pixel 306 includes a TFT switch 311. And a liquid crystal capacitor Clc and a storage capacitor Cst.

  The gate circuit 301 is a circuit for driving the gate lines G1, G2,..., Gn, and includes a shift register 307. The storage capacitor driving circuit 302 is a circuit for driving the storage capacitor lines C1, C2,... Cn. The source drive circuit 303 is a circuit for driving the source lines S1, S2,. The common drive circuit 304 is for driving the common electrode COM commonly connected to one end of the liquid crystal capacitor Clc.

  The gate circuit 301 is supplied with a start pulse STV and clock signals CK1 and CK2. In addition, VGH and VGL are input to the gate circuit 301 as logic voltages for driving the gate circuit 301.

  The storage capacitor driving circuit 302 includes a latch circuit 321, output buffers 322 and 323, an enable TFT 324, and an inverter 325, and between the latch circuit 321 and the inverter 325 in an even-numbered row. An inverter 326 is provided. The storage capacitor drive circuit 302 receives FRM signals for controlling the drive of the storage capacitor lines C1, C2,..., Cn, and VGH and VGL as logic voltages for driving the storage capacitor drive circuit 302. Is done.

  By having such a configuration, the electro-optical device 300 can apply a certain DC voltage to the common electrode COM as compared with a conventional driving method for inverting the common electrode. In addition, since the amplitude of the data voltage can be reduced, the configuration is effective for reducing power consumption.

  However, as described above, the electro-optical device 300 having such a configuration is affected by the parasitic capacitance existing between the source lines S1, S2,..., Sm and the storage capacitor lines C1, C2,. Therefore, the distortion of the source line voltage signal is superimposed on the storage capacitor line, and as a result, the distortion of the source line voltage signal appears as a distortion of the waveform of the storage capacitor line voltage. Similarly, parasitic capacitance exists between the gate lines G1, G2,..., Gn and the storage capacitor lines C1, C2,. It appears as a distortion of the capacitance line voltage waveform.

  7 is an explanatory diagram showing the distortion of the waveform of the storage capacitor lines C1, C2,..., Cn. FIG. 8 shows the parasitic capacitance Csa existing in the pixel 306 between the source line and the storage capacitor line. FIG. 5 is an explanatory diagram showing, in a circuit diagram, a reflection of a parasitic capacitance Cgc existing between a gate line and a storage capacitance line.

  As shown in FIG. 7, when the gate line (here, the gate line Gn) rises and falls, the presence of the parasitic capacitance Cgc causes distortion in the storage capacitance line Cn. Even in the selection period of the source line Sn, the distortion of the source line voltage signal is superimposed on the storage capacitor line due to the presence of the parasitic capacitance Csa, and as a result, a desired pixel voltage cannot be obtained, resulting in crosstalk. It was the cause of the decline. This is particularly noticeable when an image having different luminance is displayed on one line. As shown in FIG. 9, a white image is displayed at the center of the screen, and a gray image is displayed at the periphery of the white image. In such a case, unevenness occurs in the gray image portion.

  Therefore, in the embodiments of the present invention described below, a driving circuit and a driving method thereof for an electro-optical device capable of improving display quality and realizing low power consumption without requiring a large size increase will be described. .

<2. First embodiment of the present invention>
First, the configuration of the electro-optical device using the liquid crystal display element according to the first embodiment of the present invention will be described. FIG. 1 is an explanatory diagram showing a configuration of an electro-optical device 100 using a liquid crystal display element according to the first embodiment of the present invention. The configuration of the electro-optical device 100 according to the first embodiment of the present invention will be described below with reference to FIG.

  As shown in FIG. 1, the electro-optical device 100 according to the first embodiment of the present invention includes a gate circuit 101, a storage capacitor driving circuit 102, a source driving circuit 103, and a common driving circuit 104. Consists of. In addition, the electro-optical device 100 according to the first embodiment of the present invention includes gate lines G1, G2,... Gn formed by arranging a plurality of electrodes in the horizontal direction and a plurality of electrodes in the vertical direction. , Sm and storage capacitor lines C1, C2,... Cn formed by arranging a plurality of electrodes in the horizontal direction.

  The electro-optical device 100 according to the first embodiment of the present invention includes a plurality of pixels 106 arranged in a matrix at each intersection of the gate line and the source line in the display region 105. The pixel 106 includes a TFT switch 111, a liquid crystal capacitor Clc, and a storage capacitor Cst.

  The gate circuit 101 is a circuit for driving the gate lines G1, G2,..., Gn, and includes a shift register 107. The storage capacitor drive circuit 102 is a circuit for driving the storage capacitor lines C1, C2,... Cn. The source drive circuit 103 is a circuit for driving the source lines S1, S2,. The common drive circuit 104 is for driving the common electrode COM commonly connected to one end of the liquid crystal capacitor Clc.

  The gate circuit 101 receives a start pulse STV, clock signals CK1 and CK2, and an FRM signal for controlling driving of the storage capacitor lines C1, C2,... Cn. Further, VGH and VGL are input to the gate circuit 101 as logic voltages for driving the gate circuit 101.

  The gate circuit 101 includes an inverter 131 and TFTs 132, 133, 134, 135, 136, and 137 for each line. The gate circuit 101 further includes an inverter 138 for even rows. By switching on / off the TFTs 132, 133, 134, 135, 136, and 137, one of the voltages V1 and V2 is applied to the storage capacitor lines C1, C2,. The operation of the gate circuit 101 will be described in detail later.

  The storage capacitor driving circuit 102 includes a latch circuit 121, TFTs 122 and 123, an enable TFT 124, and an inverter 125. In an even-numbered row, an inverter 126 is provided between the latch circuit 121 and the inverter 125. Is provided. The storage capacitor drive circuit 102 receives an FRM signal for controlling the drive of the storage capacitor lines C1, C2,..., Cn, and VGH and VGL as logic voltages for driving the storage capacitor drive circuit 102. Is done.

  FIG. 2 is an explanatory diagram showing drive waveforms when focusing on the pixel 106 of the electro-optical device 100 according to the first embodiment of the present invention.

  2, Vg is an output waveform of the gate circuit 101 applied to the gate lines G1, G2,..., Gn, and Vc is applied to the storage capacitor lines C1, C2,. The output waveform of the storage capacitor driving circuit 102 is shown. VCOM is an output waveform of the common drive circuit 104, Vs is an output waveform of the source drive circuit 103, and VPIX is a voltage waveform at the PIX point of the pixel 106 (voltage waveform of the pixel voltage).

  In the N frame period, when the gate voltage Vg becomes VGH at time t1, the TFT switch 111 is turned on, and the source voltage Vsh is written into the liquid crystal capacitor Clc and the storage capacitor Cst. Therefore, the pixel voltage VPIX changes to the potential of Vsh.

  Next, when the gate voltage Vg becomes VGL at time t2, the TFT switch 111 is turned off, and the pixel voltage VPIX decreases by ΔV due to the influence of the parasitic capacitance existing between the gate electrode of the TFT switch 111 and the PIX point. Is held after.

  Next, when the output Vc of the storage capacitor driving circuit 102 changes from V2 to V1 at time t5, the pixel voltage VPIX is pushed up by Va 'through the storage capacitor Cst and held until the next frame. As a result, the liquid crystal driving voltage becomes a difference voltage V + between the common voltage VCOM and the pixel voltage VPIX.

  Normally, since the liquid crystal material needs to be inverted to prevent deterioration, in the next frame N + 1, the TFT switch 111 is turned on at time t1, and the source voltage Vsl is written. When the gate voltage Vg becomes VGL at the time t2, the TFT switch 111 is turned off, and is similarly held by being lowered by ΔV due to parasitic capacitance.

  Next, in the period of N + 1 frame, when the output Vc of the storage capacitor driving circuit 102 changes from V1 to V2 at time t5, the pixel voltage VPIX is pushed down by Vb ′ via the storage capacitor Cst and is held until the next frame. . At this time, the liquid crystal driving voltage is V-. The driving method as described above is also referred to as an independent capacitance driving method, and the source voltage amplitude can be reduced while the common electrode voltage with a large load is always kept at a constant voltage (DC driving). This is an effective driving method.

  The configuration of the electro-optical device 100 according to the first embodiment of the present invention has been described above. Next, details of driving of the electro-optical device 100 according to the first embodiment of the present invention will be described.

  FIG. 3 is an explanatory diagram illustrating a change in potential of the electro-optical device 100 according to the first embodiment of the present invention. The details of driving the electro-optical device 100 according to the first embodiment of the present invention will be described below with reference to FIG.

  3 shows changes in the potentials of Point A, Point B, Point C, and Point D in the configuration of the gate lines G1 and G2, the storage capacitor lines C1 and C2, and the electro-optical device 100 shown in FIG.

  The gate circuit 101 receives a start pulse STV for operating the shift register 107, clock signals CK1, CK2, and an FRM signal for controlling driving of the storage capacitor lines C1, C2,..., Cn. ing. In addition, VGH and VGL are input to the gate circuit 101 as logic voltages for driving the gate circuit 101.

  The VGH and VGL voltages are the same as the output voltages VGH and VGL of the gate lines G1, G2,..., Gn. In the first embodiment of the present invention, the control signal and the drive voltage are defined. However, if the circuit configuration is such that the gate lines G1, G2,. Even if another configuration is adopted, there is no problem in obtaining the effect of the present invention.

  When the start pulse STV is input to the gate circuit 101, pulses are sequentially output from the shift register 107 to the gate lines G1, G2,..., Gn in synchronization with the clock signals CK1 and CK2.

  Referring to FIG. 3, focusing on the gate line G1, when the gate line G1 becomes High (VGH) at the time t1, the TFTs 132 and 133 are turned on, and the FRM signal is input to the gate electrodes 134 and 135, respectively. . Since FRM is H during the N frame period, the TFT 134 is turned off, the TFT 135 is turned on, and the voltage V2 is supplied to the storage capacitor line C1.

  Thereafter, when the gate line G1 becomes Low (VGL) at the time t2, the TFTs 132 and 133 are turned off, and instead, the output of the inverter 131 becomes High, so that the TFTs 137 and 138 are turned on. Further, since the voltages V1 and V2 are applied to the gate electrodes of the TFTs 132 and 133, respectively, the TFTs 134 and 135 are both turned off and are electrically disconnected from the storage capacitor line C1 (become a high impedance state).

  As described above, when the TFTs 132 and 133 are both turned off, and when the gate inputs of the TFTs 134 and 135 are in a high impedance state, the TFTs 136 and 137 give a voltage that is surely turned off, such as noise from the outside. It prevents the TFTs 134 and 135 from malfunctioning due to the mixing factor.

  Next, in the period of N + 1 frame, when the gate line G1 becomes High at time t1, the TFTs 132 and 133 are turned on, and the FRM signal is input to the gates of the TFTs 134 and 135. In the N + 1 frame, since the FRM signal is L, the TFT 134 is turned on, the TFT 135 is turned off, and the voltage V1 is applied to the storage capacitor line C1.

  Thereafter, when the gate line G1 becomes Low at time t2, the TFTs 132 and 133 are turned off, and the output of the inverter 131 becomes H instead, so that the TFTs 136 and 137 are turned on. Thus, the voltage V1 or V2 is supplied from the buffer circuit composed of the TFTs 134 and 135 in the gate circuit 101 during the period when the gate line G1 is selected, and the output from the buffer circuit is high during other periods. It becomes an impedance state and is electrically disconnected from the storage capacitor line C1.

  In each of the N frame and the N + 1 frame, the period from when the gate line G1 becomes Low until the buffer circuit including the TFTs 134 and 135 on the gate circuit 101 side is turned off By appropriately selecting the W / L size of the TFT, a delay corresponding to α in FIG. 2 can be generated. This is because the gate line voltage fluctuates from VGH to VGL at the timing when the gate line G1 is turned off, and noise due to this voltage fluctuation is superimposed on the storage capacitor line C1 via a parasitic capacitance (not shown) or the like. As a result, the display quality deteriorates. By generating the delay of α, it is possible to electrically disconnect the storage capacitor line C1 after the gate line G1 is surely turned off, so that it is possible to prevent the deterioration of display quality as described above. . Therefore, the period during which power is actually supplied from the buffer circuit including the TFTs 134 and 135 to the storage capacitor line C1 in the gate circuit 101 is the period from t1 to t2 + α for both the N frame and the N + 1 frame.

  Next, the operation of the storage capacitor driving circuit 102 will be described. The storage capacitor driving circuit 102 includes a latch circuit 121, TFTs 122 and 123, an inverter 124, and an enable TFT 125. Similar to the gate circuit 101, the storage capacitor drive circuit 102 receives VGH and VGL voltages as logic voltages, and FRM signals for controlling the drive of the storage capacitor lines C1, C2,..., Cn. Is entered.

  Gate outputs G3, G4,..., Gn + 2 from the gate circuit 101 are input to the gate of the enable TFT 125. For example, the gate output G3 is connected to the gate of the enable TFT 125 corresponding to the storage capacitor line C1. Similarly, the gate output Gn + 2 is connected to the storage capacitor line Cn. As shown in FIG. 3, the enable TFT 125 of the storage capacitor line C1 is turned on at time t5 after a predetermined period when the gate line G1 is turned off at time t2, and the latch circuit 121 is updated by the FRM signal. Depending on the output state, one of the TFTs 122 and 123 as the output buffer at the final stage is turned on.

  For example, when the FRM signal is High in N frames, when the gate output G3 becomes High, the enable TFT 125 of the storage capacitor line C1 is turned on, the latch circuit 121 is updated, and the output becomes High. In this case, the buffer circuit 122 is turned on, the V1 voltage is selected and output to the storage capacitor line C1, and this state is maintained until the data of the latch circuit 121 is updated in the next frame.

  In the next N + 1 frame, since the FRM signal becomes L, the buffer circuit 123 is turned on at time t5, and the voltage V2 is supplied to the storage capacitor line C1. Thus, the output of the storage capacitor driving circuit 102 repeats the operation of selecting the voltage V1 or V2 for each frame. Regarding the drive of the storage capacitor line C1, the relationship between the gate circuit 101 and the storage capacitor drive circuit 102 is summarized with reference to FIG. 3. In the N frame, during the period t1 to t2 + α in which the gate line G1 is selected, the gate circuit 101 is driven. The TFT 135 on the side is turned on to supply the V2 voltage, and the V2 voltage is similarly supplied from the storage capacitor driving circuit 102. In the period after t2 + α, the buffer circuit composed of the TFTs 134 and 135 on the gate circuit 101 side is disconnected from the storage capacitor line C1, but the V2 voltage is continuously applied from the storage capacitor driving circuit 102. Thereafter, at time t5, the output of the storage capacitor driving circuit 102 changes from V2 to V1. Next, in the N + 1 frame, the TFT 134 on the gate circuit 101 side is turned on and the V1 voltage is supplied during the period from t1 to t2 + α when the gate line G1 is selected, and the storage capacitor driving circuit 102 also outputs in the previous N frame. The V1 voltage being supplied is continuously supplied. Thereafter, at time t5, the output of the storage capacitor driving circuit 102 changes from V1 to V2.

  Next, focusing on the gate line G2 and the storage capacitor line C2, as shown in FIG. 3, the circuit corresponding to the gate line G2 of the gate circuit 101 includes the inverter 138 in the FRM signal line. In the period from t3 to t4 that is High, the inverted signal Low of FRM is input to the gate electrodes of the TFTs 134 and 135, respectively. In other words, the V2 voltage is supplied to the storage capacitor line C1 in the N frame period, but the V1 voltage is supplied to the storage capacitor line C2 because the TFT 134 is turned on. Similarly, since the storage capacitor driving circuit 102 also has an inverter 126, as a result, the output signal of the storage capacitor driving circuit 102 is sequentially output by inverting the signals of the storage capacitor lines C1, C2,. Will be. That is, the storage capacitor line C2 is also applied with the V1 voltage from the gate circuit 101 side in the period t3 to t4 + α, and in the period after t4 + α, the gate circuit 101 is disconnected from the storage capacitor line C2, but the storage capacitor drive circuit 102 The voltage V1 continues to be applied to the storage capacitor line C2. Then, at time t6, the voltage applied to the storage capacitor line C2 changes to the V2 voltage.

  Here, the periods t1, t2, and t5 shown in FIG. 3 coincide with the periods t1, t2, and t5 in FIG. That is, the TFT switch 111 of the pixel 106 is sequentially selected during a period in which the gate voltage of a certain gate line is selected, and a desired data voltage is written from the source driving circuit 103 to the liquid crystal capacitor Clc. After the data voltage is written into the liquid crystal capacitor Clc, a predetermined voltage (V1 or V2) is superimposed on the storage capacitor line from the storage capacitor driving circuit 102 at a predetermined timing, and then written into the pixel 106 via the storage capacitor Cst. The converted data voltage is converted into a voltage suitable for the optical characteristics of the desired liquid crystal.

  A constant voltage VCOM is always applied to the common electrode COM from the common drive circuit 104, and a final liquid crystal drive voltage is determined between the pixel voltage VPIX after the conversion and the common voltage VCOM. .

  When attention is paid again to the storage capacitor line C1, during the period (t1 to t2) when the gate line G1 is selected, the corresponding storage capacitor line C1 has a predetermined voltage updated one frame before from the storage capacitor drive circuit 102 side. Supplied. In the case of FIG. 3, this predetermined voltage is the V2 voltage in the N frame and the V1 voltage in the N + 1 frame. The electro-optical device 100 supplies the predetermined voltage and the same voltage as the output voltage from the storage capacitor drive circuit 102 to the storage capacitor line C1 from the gate circuit 101 side (V2 voltage in the N frame, V1 in the N + 1 frame). Voltage) is supplied from time t1 to t2 + α.

  More specifically, in the N frame, during the gate selection period t1 to t2, the final liquid crystal application voltage writes a data voltage on the high potential side with respect to the COM voltage, so that the storage capacitor driving circuit 102 and the gate circuit 101 are written. The TFT 135 and the TFT 123 are turned on in both the buffer circuits included in the circuit, and the low voltage V2 is selected and applied to the storage capacitor line C1. Next, in the N + 1 frame, in the gate selection period t1 to t2, the final liquid crystal application voltage writes the data voltage on the low potential side with respect to the COM voltage, so that the TFT 134 and the TFT 122 of both the buffer circuits are turned on. The high voltage V1 is selected and applied to the storage capacitor line C1.

  In this way, the storage capacitor lines C1, C2,..., Cn are driven from the buffer circuit provided in both the storage capacitor driving circuit 102 and the gate circuit 101 only during a predetermined period, thereby making it possible to perform parasitics during data writing. It is possible to suppress the influence of the distortion waveform due to the capacitance Csa and the parasitic capacitances Cgd and Cgc, stabilize the voltage fluctuation of the storage capacitance line, and reduce crosstalk.

  More specifically, after the gate voltage of a certain storage capacitor line is turned on until the gate voltage of the storage capacitor line of the next row is turned on after the gate voltage is turned off (for example, a certain storage capacitor line) The voltage is supplied also from the gate circuit 101 side during the gate selection period + α of the capacitor line). In addition, the storage capacitor drive circuit 102 always selects the voltage V1 or V2 for each storage capacitor line, and a stable voltage is always supplied. As a result of the voltage V1 or V2 being constantly supplied by the storage capacitor driving circuit 102, there is no influence of external noise or the like.

  In addition, a constant DC voltage should always be applied as the common voltage, and even if the liquid crystal mode changes, it is not necessary to reversely drive the common electrode with a large load, which is advantageous for low power consumption. In addition, since the storage capacitor lines C1, C2,..., Cn are fed from both sides of the storage capacitor driving circuit 102 and the gate circuit 101 during the data writing period, the storage capacitor driving circuit is used to stabilize the voltage fluctuation. Since the problem of crosstalk does not occur even if the driving capacity of the buffer 102 is not increased more than necessary, it is possible to reduce the buffer size as compared with the conventional case, and as a result, the size other than the display area of the liquid crystal display device ( It is possible to reduce the frame).

<3. Second embodiment of the present invention>
Next, the configuration of the electro-optical device using the liquid crystal display element according to the second embodiment of the present invention will be described. FIG. 4 is an explanatory diagram showing a configuration of an electro-optical device 200 using the liquid crystal display element according to the second embodiment of the present invention. The configuration of the electro-optical device 200 according to the second embodiment of the present invention will be described below with reference to FIG.

  As shown in FIG. 4, the electro-optical device 200 according to the second embodiment of the present invention includes a gate circuit 201, a storage capacitor driving circuit 202, a source driving circuit 203, and a common driving circuit 204. Consists of. In addition, the electro-optical device 200 according to the second embodiment of the present invention has gate lines G1, G2,... Gn formed by arranging a plurality of electrodes in the horizontal direction and a plurality of electrodes in the vertical direction. , Sm and storage capacitor lines C1, C2,... Cn formed by arranging a plurality of electrodes in the horizontal direction.

  The electro-optical device 200 according to the second embodiment of the present invention includes a plurality of pixels 206 arranged in a matrix at each intersection of the gate line and the source line in the display area 205. The pixel 206 includes a TFT switch 211, a liquid crystal capacitor Clc, and a storage capacitor Cst.

  The gate circuit 201 is a circuit for driving the gate lines G1, G2,..., Gn, and includes a shift register 207. The storage capacitor drive circuit 102 is a circuit for driving the storage capacitor lines C1, C2,... Cn. The source drive circuit 103 is a circuit for driving the source lines S1, S2,. The common drive circuit 104 is for driving the common electrode COM commonly connected to one end of the liquid crystal capacitor Clc.

  The gate circuit 201 receives a start pulse STV, clock signals CK1 and CK2, and an FRM signal for controlling driving of the storage capacitor lines C1, C2,... Cn. In addition, VGH and VGL are input to the gate circuit 201 as logic voltages for driving the gate circuit 201.

  The gate circuit 201 includes an inverter 231 and TFTs 232, 233, 234, 235, 236, and 237 for each line. By switching on / off the TFTs 232, 233, 234, 235, 236, 237, one of the voltages V1, V2 is applied to the storage capacitor lines C1, C2,. The operation of the gate circuit 101 will be described in detail later.

  The storage capacitor drive circuit 202 includes a latch circuit 221, TFTs 222 and 223, an enable TFT 224, and an inverter 225. The storage capacitor drive circuit 202 includes storage capacitor lines C1, C2,. VGH and VGL are input as an FRM signal for controlling driving of Cn and a logic voltage for driving the storage capacitor driving circuit 202.

  The difference from the configuration of the electro-optical device 100 according to the first embodiment of the present invention described above is that the inverters are not provided in even rows in the gate circuit 201 and the storage capacitor driving circuit 202. There is no change and the configuration of the electro-optical device 100 according to the first embodiment of the present invention described above.

  The configuration of the electro-optical device 200 according to the second embodiment of the present invention has been described above. Next, details of driving of the electro-optical device 200 according to the second embodiment of the present invention will be described.

  FIG. 5 is an explanatory diagram showing a change in potential of the electro-optical device 200 according to the second embodiment of the present invention. The details of driving the electro-optical device 200 according to the second embodiment of the present invention will be described below with reference to FIG.

  FIG. 5 shows changes in potentials of the gate lines G1, G2, G3, and G4 and the storage capacitor lines C1, C2, C3, and C4.

  The gate circuit 201 receives a start pulse STV for operating the shift register 207, clock signals CK1, CK2, and an FRM signal for controlling driving of the storage capacitor lines C1, C2,..., Cn. Has been. In addition, VGH and VGL are input to the gate circuit 201 as voltages for driving the gate circuit 201. When the start pulse STV is input to the gate circuit 201, the shift register 207 operates in synchronization with the clock signals CK1 and CK2, and the gate pulses G1, G2,.

  Focusing on the gate line G1 with reference to FIG. 5, at time t1, the gate line G1 is High (VGH), the TFTs 232 and 233 are turned on, and the FRM signal is input to the gates of the TFT 232 and the TFT 233. In the N frame period, since the FRM signal is High (VGH) from t1 to t2, the TFT 234 is turned off and the TFT 235 is turned on. As a result, the V2 voltage is applied to the storage capacitor line C1.

  When the gate line G1 becomes VGL at the time t2, the TFTs 232 and 233 are turned off, and the output of the inverter 231 becomes high instead, so that the TFTs 236 and 237 are turned on. Since the voltages V1 and V2 are applied to the gate electrodes of the TFTs 234 and 235, respectively, the TFTs 234 and 235 are both turned off (high impedance) and disconnected from the storage capacitor line C1.

  The TFTs 236 and 237 prevent the TFTs 234 and 235 from malfunctioning when the TFTs 232 and 233 are both turned off. In other words, the TFTs 234 and 235 have a role of preventing malfunctions of the TFTs 234 and 235 due to factors such as external noises by reliably applying an off voltage so that the gate inputs of the TFTs 234 and 235 do not enter a high impedance state.

  Next, in the period of N + 1 frame, when the gate line G1 becomes High (VGH) at time t1, the TFTs 232 and 233 are turned on, and the FRM signal is input to the gates of the TFTs 234 and 235. Since the FRM signal is in the Low (VGL) state in the period from t1 to t2 of the N + 1 frame, the TFT 234 is turned on and the TFT 235 is turned off. As a result, the V1 voltage is applied to the storage capacitor line C1.

  When the gate line G1 becomes Low (VGL) at the time t2, the TFTs 232 and 233 are turned off, and instead, the output of the inverter 231 becomes High, so that the TFTs 36 and 237 are turned on. From such a circuit configuration of the gate circuit 201, the voltage V1 or V2 is supplied from the buffer circuit including the TFTs 234 and 235 on the gate circuit 201 side in the period when the gate line G1 is selected, and in the other periods. The output of the buffer circuit composed of the TFTs 234 and 235 enters a high impedance state and is disconnected from the storage capacitor line C1.

  Note that in each of the N frame and the N + 1 frame, the period from when the gate line G1 becomes Low until the buffer circuit including the TFTs 234 and 235 on the gate circuit 201 side is turned off By appropriately selecting the TFT W / L size, a delay corresponding to α in FIG. 5 can be generated. This is because the gate line voltage fluctuates from VGH to VGL at the timing when the gate line G1 is turned off, and noise due to this voltage fluctuation is superimposed on the storage capacitor line C1 via a parasitic capacitance (not shown) or the like. As a result, the display quality deteriorates. By generating the delay of α, it is possible to electrically disconnect the storage capacitor line C1 after the gate line G1 is surely turned off, so that it is possible to prevent the deterioration of display quality as described above. . Therefore, the period during which power is supplied from the buffer circuit composed of the TFTs 234 and 235 in the gate circuit 201 to the storage capacitor line C1 is the period from t1 to t2 + α for both the N frame and the N + 1 frame.

  Next, the operation of the storage capacitor driving circuit 202 will be described. The storage capacitor driving circuit 202 includes a latch circuit 221, TFTs 222 and 223, an inverter 224, and an enable TFT 225. Similarly to the gate circuit 201, the storage capacitor drive circuit 202 is supplied with VGH and VGL voltages as circuit drive voltages, and an FRM signal for controlling the drive of the storage capacitor lines C1, C2,. Is entered.

  Gate outputs G3, G4,..., Gn + 2 from the gate circuit 201 are input to the gate of the enable TFT 225. For example, the gate output G3 is connected to the gate of the enable TFT 225 corresponding to the storage capacitor line C1. Similarly, the gate output Gn + 2 is connected to the storage capacitor line Cn. As shown in FIG. 5, the enable TFT 225 of the storage capacitor line C1 is turned on at time t5 after a predetermined period when the gate line G1 is turned off at time t2, and the latch circuit 221 is updated by the FRM signal. Depending on the output state, ON / OFF of any one of the TFTs 222 and 223 which are output buffers in the final stage is selected.

  For example, when the FRM signal is High at time t5 in the N frame period, when the gate output G3 becomes High, the enable TFT 225 is turned on, and the output of the latch circuit 221 becomes High. In this case, the TFT 222 of the output buffer is turned on, the V1 voltage is selected and output to the storage capacitor line C1, and this state is maintained until the data of the latch circuit 221 is updated in the next N + 1 frame.

  At time t5 of the next N + 1 frame, since the FRM signal becomes L, the output buffer TFT 223 is turned on, and the voltage V2 is selected and supplied to the storage capacitor line C1. The difference from the first embodiment of the present invention is that the FRM signal is inverted every 1 HS and further every frame, but even if the FRM signal is an inverted signal, it is fundamental. There is no change in operation.

  Next, regarding the drive of the storage capacitor line C1, the relationship between the gate circuit 201 and the storage capacitor drive circuit 202 will be organized with reference to FIG. In the N frame, during the period t1 to t2 + α when the gate line G1 is selected, the TFT 235 of the buffer circuit on the gate circuit 201 side is turned on to supply the V2 voltage, and the V2 voltage is similarly supplied from the storage capacitor driving circuit 202. Is done. In the period after t2 + α, the buffer circuit composed of the TFTs 234 and 235 on the gate circuit 201 side is disconnected from the storage capacitor line C1, but V2 is continuously applied to the storage capacitor line C1 from the output of the storage capacitor drive circuit 202. Thereafter, the output of the storage capacitor driving circuit 202 changes from V2 to V1 at time t5. Next, in the N + 1 frame, in the period from t1 to t2 + α when the gate line G1 is selected, the TFT 234 of the buffer circuit on the gate circuit 201 side is turned on, the V1 voltage is supplied, and also from the storage capacitor driving circuit 202 The V1 voltage output in the previous N frame is continuously supplied. Thereafter, the output of the storage capacitor driving circuit 202 changes from V1 to V2 at time t5.

  Next, focusing on the gate line G2 and the storage capacitor line C2, as shown in FIG. 5, since the FRM signal is L during the period from t3 to t4 when the gate line G2 becomes High, the TFTs 234, 235 of the buffer circuit. VGL is input to the gate electrode. That is, in the N frame period, the V2 voltage is applied to the aforementioned storage capacitor line C1, but the V1 voltage is applied to the storage capacitor line C2 because the TFT 234 of the buffer circuit is turned on. Similarly, the output of the storage capacitor driving circuit 202 changes from V1 to V2 when the Low FRM signal is taken into the latch circuit 221 at time t7. As a result, the output signal of the storage capacitor drive circuit 202 is sequentially output as an inverted signal for each of the storage capacitor lines C1, C2,..., Cn.

  As described above, the electro-optical device 200 according to the second embodiment of the present invention can output the FRM signal even without the inverter circuits 126 and 138 unlike the electro-optical device 100 according to the first embodiment of the present invention. By replacing the inverted signal for each 1HS, the same driving as that of the electro-optical device 100 according to the first embodiment of the present invention can be realized.

  In the electro-optical device 200 according to the second embodiment of the present invention, the driving of the pixels 206 is the same. That is, during the period when the gate voltage of a certain gate line is selected, the TFT switch 211 of the pixel 206 is sequentially selected, and a desired data voltage is written from the source driving circuit 203 to the liquid crystal capacitor Clc. After the data voltage is written into the liquid crystal capacitor Clc, a predetermined voltage (V1 or V2) is superposed on the storage capacitor line from the storage capacitor driving circuit 202 at a timing delayed by 1 HS, thereby being applied to the pixel 206 via the storage capacitor Cst. The written data voltage is converted into a voltage suitable for the desired optical characteristics of the liquid crystal.

  A constant voltage VCOM is always applied to the common electrode COM from the common drive circuit 204, and a final liquid crystal drive voltage is determined between the pixel voltage VPIX after the conversion and the common voltage VCOM. .

  Looking again at the storage capacitor line C1, during the period (t1 to t2) when the gate line G1 is selected, the corresponding storage capacitor line C1 has a predetermined voltage updated one frame before from the storage capacitor drive circuit 202 side. Supplied. In the case of FIG. 5, this predetermined voltage is the V2 voltage in the N frame and the V1 voltage in the N + 1 frame. The electro-optical device 200 supplies the predetermined voltage and the same voltage as the output voltage from the storage capacitor driving circuit 202 during the period from t1 to t2 + α (V2 in the N frame) from the gate circuit 201 side to the storage capacitor line C1. Voltage, V1 voltage in N + 1 frame).

  More specifically, in the gate selection period t1 to t2 of the N frame, the final liquid crystal application voltage writes a data voltage on the high potential side with respect to the COM voltage, so that the storage capacitor driving circuit 202 and the gate circuit 201 are written. Of both the buffer circuits provided, the TFT 235 and the TFT 223 are turned on, and the low voltage V2 is selected and applied to the storage capacitor line C1. In the gate selection period t1 to t2 of the (N + 1) th frame, since the final liquid crystal application voltage writes the data voltage on the low potential side with respect to the COM voltage, the TFT 234 and the TFT 222 in both the above buffer circuits are turned on, The voltage V1 is selected and applied to the storage capacitor line C1.

  As described above, in the electro-optical device 200 according to the second embodiment of the present invention, the FRM signal is converted into the inverted signal described above without having an inverter in the gate circuit 201 and the storage capacitor driving circuit 202 every other line. By replacing with, it becomes possible to realize the same drive as the electro-optical device 100 according to the first embodiment of the present invention.

  In addition, by driving the storage capacitor lines C1, C2,..., Cn from a buffer circuit provided in both the storage capacitor drive circuit 202 and the gate circuit 201 only for a predetermined period, the parasitic capacitor Csa is written during data writing. In addition, it is possible to suppress the influence of the distortion waveform due to the parasitic capacitances Cgd and Cgc, stabilize the voltage fluctuation of the storage capacitance line, and reduce crosstalk.

  More specifically, after the gate voltage of a certain storage capacitor line is turned on until the gate voltage of the storage capacitor line of the next row is turned on after the gate voltage is turned off (for example, a certain storage capacitor line) The voltage is supplied also from the gate circuit 201 side during the gate selection period of the capacitor line + a period only). In each storage capacitor line, the storage capacitor driving circuit 202 always selects the voltage V1 or V2 in any period and always supplies a stable voltage. As a result of the voltage V1 or V2 being constantly supplied by the storage capacitor driving circuit 202, there is no influence of external noise or the like.

  In addition, a constant DC voltage should always be applied as the common voltage, and even if the liquid crystal mode changes, it is not necessary to reversely drive the common electrode with a large load, which is advantageous for low power consumption. Further, since the storage capacitor lines C1, C2,..., Cn are fed from both sides of the storage capacitor drive circuit 202 and the gate circuit 201 during the data write period, the storage capacitor drive circuit for stabilizing the voltage fluctuation. Since the problem of crosstalk does not occur even if the driving capacity of the buffer 202 is not increased more than necessary, the buffer size can be reduced as compared with the conventional case, and as a result, the size other than the display area of the liquid crystal display device ( It is possible to reduce the frame).

  The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to such examples. It is obvious that a person having ordinary knowledge in the technical field to which the present invention pertains can come up with various changes or modifications within the scope of the technical idea described in the claims. Of course, it is understood that these also belong to the technical scope of the present invention.

100, 200 Electro-optical device 101, 201 Gate circuit 102, 202 Storage capacitor drive circuit 103, 203 Source drive circuit 104, 204 Common drive circuit 105, 205 Display area 106, 206 Pixel 111, 211 TFT switch

Claims (6)

Multiple gate lines,
Multiple source lines,
A plurality of storage capacitor lines provided corresponding to the plurality of gate lines;
Provided corresponding to the intersection of the plurality of gate lines and the plurality of source lines;
A common electrode;
A pixel switching element having one end connected to the source line and turned on between the one end and the other end when the gate line is selected;
A pixel capacitor having one end connected to the other end of the pixel switching element and the other end connected to the common electrode;
A plurality of pixels including a storage capacitor having one end connected to the other end of the pixel switching element and the other end connected to the storage capacitor line ;
A drive circuit for an electro-optical device having:
The plurality of gate lines are selected in a predetermined order, a predetermined voltage is supplied to the storage capacitor line corresponding to the gate line selected during a first period, and the storage is performed in addition to the first period. A gate circuit electrically isolated from the capacitor line ;
A source driving circuit for supplying a data signal of a voltage corresponding to the gradation and polarity of the pixel to the pixel corresponding to the one source line via the source line;
A storage capacitor driving circuit for continuously supplying a predetermined voltage to the storage capacitor line;
A drive circuit for an electro-optical device. The gate circuit supplies a predetermined voltage to the nth storage capacitor line only in a period from the selection of the nth gate line to the selection of the (n + 1) th gate line after the selection period has elapsed. The drive circuit for an electro-optical device according to claim 1, wherein: The storage capacitor line is electrically disconnected and independently driven from the common electrode connected to one end of the pixel capacitor constituting the pixel, and a predetermined data voltage is applied while the gate line is selected. The pixel potential that is the potential on the opposite side of the common electrode of the pixel is shifted to the high voltage side or the low voltage side by the storage capacitor driving circuit at a timing delayed by a predetermined period after being applied to the pixel. The driving circuit of the electro-optical device according to claim 1, wherein the final pixel potential is determined by the following. 2. The drive circuit for an electro-optical device according to claim 1, wherein the first period includes a period in which the gate line is selected and a delay period. 5. The drive circuit for an electro-optical device according to claim 4, wherein the delay period is determined by selecting a W / L size of a transistor constituting the drive circuit. 2. The drive circuit for an electro-optical device according to claim 1, wherein a DC voltage is supplied to the common electrode, and a first voltage or a second voltage is selectively supplied to the storage capacitor line.

Images