JP5686211B2 - Component built-in wiring board - Google Patents

Description

  The present invention relates to a component built-in wiring board in which components are embedded and mounted in an insulating plate, and more particularly, to a component built-in wiring board having a configuration aimed at thinning.

  An example of a component built-in wiring board is described in Japanese Patent Application Laid-Open No. 2003-197849. In the wiring board disclosed in this document, in addition to passive element components such as a chip capacitor (chip capacitor), a semiconductor chip (active element component) is a target component to be embedded.

  In the wiring board in which the semiconductor chip and the passive element component are mixedly mounted as described above, focusing on the thickness of the built-in component, the semiconductor chip usually has a thickness of about 0.5 mm, but the back grinding method The thickness can be reduced by, for example, a thin film having a thickness of about 50 μm can be used. On the other hand, the size of the passive element component is standardized. For example, in the case of relatively small 0603 size and 0402 size, the width is 0.6 mm × length 0.3 mm × thickness 0.3 mm, respectively. Width 0.4 mm × length 0.2 mm × thickness 0.2 mm. Therefore, the thickness is several times that of a thin semiconductor chip.

  Therefore, it is essential to prepare a built-in area in the thickness direction corresponding to the thickness of the passive element component, at least for the component built-in wiring board that incorporates the passive element component. It is a factor of.

JP 2003-197849 A

  The present invention has been made in consideration of the above-described circumstances, and an object of the present invention is to provide a component built-in wiring board that can be thinned in a component built-in wiring board in which components are embedded and mounted in an insulating plate. .

  In order to solve the above-described problem, a component built-in wiring board according to an aspect of the present invention includes a first insulating layer, a second insulating layer positioned in a stacked manner with respect to the first insulating layer, A passive element component having a plurality of terminals embedded in a second insulating layer, and a connection land for the passive element component provided between the first insulating layer and the second insulating layer A connection member that electrically connects the plurality of terminals of the passive element component and the connection land of the first wiring pattern; and immediately adjacent to the first wiring pattern. A second wiring pattern that is an inner layer wiring pattern provided so as to be buried in the second insulating layer as a wiring layer, and the passive element component includes a plate-like inorganic material substrate and And a passive element formed in a layer on one surface of the inorganic material substrate. The plurality of terminals of the passive element component are terminals electrically connected to the passive element and provided on the one surface side of the inorganic material base material, and the second insulating layer is A layered first reinforcing material provided by retracting the position of the passive element component between the first wiring pattern and the second wiring pattern, and the first reinforcing material as viewed from the first reinforcing material And a layered second reinforcing material provided so as to overlap the first reinforcing material and the passive element component on the second wiring pattern side.

  That is, in this component built-in wiring board, at least a passive element component having a terminal is embedded, and this passive element component is composed of a plate-like inorganic material substrate and one surface of the inorganic material substrate. And a passive element formed in a layered manner thereon. And the several terminal of a passive element component is electrically connected to this passive element, and is provided in the one surface side of the inorganic material base material. In other words, the passive element component has a plate-like inorganic material base material like the semiconductor chip, and the passive element is formed in a layer on one surface of the inorganic material base material. The terminal is provided on one surface side of the inorganic material base material.

  Therefore, the built-in passive element component can be made as thin as a component having a semiconductor chip, and the preparation of a built-in region in the thickness direction corresponding to the thickness of the passive element component is thin as a component built-in wiring board. Things are enough. Therefore, it is possible to reduce the thickness of the component built-in wiring board.

  According to the present invention, it is possible to reduce the thickness of a component built-in wiring board in which components are embedded and mounted in an insulating plate.

Sectional drawing which shows typically the structure of the component built-in wiring board which concerns on one Embodiment of this invention. Sectional drawing which shows typically the structural example of the passive element components incorporated in the component built-in wiring board shown in FIG. Process drawing which shows a part of manufacturing process of the component built-in wiring board shown in FIG. Process drawing which shows another part of manufacturing process of the component built-in wiring board shown in FIG. FIG. 9 is a process diagram schematically showing still another part of the manufacturing process of the component built-in wiring board shown in FIG. 1. Sectional drawing which shows typically the modification of the passive element component shown in FIG. FIG. 7 is a circuit diagram showing a configuration example of a passive network that the passive element component shown in FIG. 6 can have. Sectional drawing which shows typically the structure of the component built-in wiring board which concerns on another embodiment of this invention. Process drawing which shows a part of manufacturing process of the component built-in wiring board shown in FIG. Sectional drawing which shows typically the structure of the component built-in wiring board which concerns on another embodiment of this invention. Process drawing which shows a part of manufacturing process of the component built-in wiring board shown in FIG.

  As an embodiment of the present invention, the inorganic material substrate of the passive element component is a kind of conductive substrate selected from the group consisting of stainless alloy (SUS), copper, nickel, and titanium. Can do. These metals are suitable as a base material for inorganic materials used for passive element parts. One is that even if it is thin (for example, several tens of μm thick), it can maintain rigidity as a component, has good availability, and further, there is no problem in forming passive elements in layers on the surface. In particular, SUS can be selected from various types having good rigidity and appropriate thickness. In the case of copper, it is the same material as the wiring pattern used for general wiring boards. By roughening the surface, the adhesion with the wiring board material is improved to obtain a wiring board with less defects such as peeling. be able to.

  Here, the passive element of the passive element component is a capacitor, and the inorganic material base of the passive element component is electrically connected to one terminal of the plurality of terminals, and the passive element It can be said that it is one electrode of the said capacitor | condenser which is an element. In this case, utilizing the fact that the inorganic material substrate is conductive, this is used as one electrode to obtain a capacitor as a passive element. By using the inorganic material substrate as one electrode, a capacitor can be formed with an easier configuration.

  As an embodiment, the inorganic material substrate of the passive element component may be a kind of semiconductor substrate or non-conductive substrate selected from the group consisting of silicon, ceramic, and glass. . These substrates are suitable as the inorganic material substrate used for the passive element component. One is that even if it is thin (for example, several tens of μm thick), it can maintain rigidity as a component, has good availability, and there are many known techniques for forming passive elements in layers on the surface. It is also relatively easy to process thinly by a back grinding method.

  Here, the inorganic material substrate of the passive element component is silicon, and the passive element of the passive element component is a kind selected from the group consisting of a capacitor, a resistor, and an inductor. it can. When the inorganic material substrate is silicon, these passive elements can be formed on the silicon plate by a general semiconductor manufacturing process. By using the semiconductor manufacturing process, many advantages such as cost reduction and productivity improvement can be expected.

  As an embodiment, the inorganic material substrate of the passive element component is silicon, and the passive element component includes a plurality of passive elements formed in layers on the one surface of the inorganic material substrate. The plurality of passive elements constitute a passive network, a part of the plurality of terminals of the passive element component is an input terminal of the passive network component, and the plurality of terminals of the passive element component May be the output terminal of the passive network. When the inorganic material substrate is silicon, it is easy to form a passive network by making a large number of passive elements on the silicon plate. By adding a passive network, added value is improved as a passive element component.

  Further, as an embodiment, the wiring pattern further includes a second connection land for a semiconductor component, further includes a semiconductor chip embedded in the second insulating layer, and has substantially the same thickness as the passive element component. A semiconductor component having a thickness, and a second connection member that electrically connects a terminal of the semiconductor component and the second connection land of the wiring pattern, and is included in the second insulating layer The first reinforcing material is provided so as to be retracted from the position of the semiconductor component, and the second reinforcing material contained in the second insulating layer is viewed from the first reinforcing material. The first reinforcing member, the passive element component, and the semiconductor component may be provided so as to overlap with each other on the second wiring pattern side. This is a mode in which a semiconductor component is built in and mixed with a passive element component. The thickness of the semiconductor component and the passive element component is almost the same, so that the added value is increased by the mixed mounting, and the thinning is realized as the mixed component built-in wiring board.

  Here, the connection member may be made of the same material as the second connection member. When the same material is used in this way, in the manufacturing process, the passive element component and the semiconductor component can be connected to the land at the same time in the same manner. Therefore, the manufacturing efficiency is improved.

  Furthermore, here, the connection member and the second connection member may be solder. When both the passive element component and the semiconductor component are connected to the land by solder, for example, surface mounting technology can be used, and the cost can be reduced particularly.

  Further, here, the semiconductor chip of the semiconductor component has a terminal pad, and the semiconductor component includes a surface-mounting terminal in a grid-like arrangement electrically connected to the terminal pad as the terminal. It can be. According to this, surface mounting technology can be used to connect the semiconductor component to the land, and the cost can be reduced.

  Here, it is assumed that the semiconductor chip of the semiconductor component has a terminal pad, and the second connecting member is a protruding electrode formed on the terminal pad of the semiconductor chip. it can. According to this, a bare semiconductor chip can be used as the semiconductor component, and since it is not necessary to be a package product, various semiconductor components can be used.

  Further, as an embodiment, the conductive layer is sandwiched between a surface of the first wiring pattern and a surface of the second wiring pattern through a part in the stacking direction of the second insulating layer. It is further possible to further include an interlayer connection body having a shape that has an axis that coincides with the stacking direction and has a diameter that changes in the direction of the axis.

  In this aspect, by utilizing the fact that the thickness of the built-in passive element component can be reduced, an interlayer connection body having a dimension higher than that of the passive element component is used to electrically connect the wiring patterns above and below the passive element component. It is a configuration. In other words, the passive element component is located between the wiring patterns that are adjacently stacked on top and bottom, which indicates that the ratio in the thickness direction occupied by the passive element component can be reduced.

  Here, the second interlayer connection has a shape that penetrates the first insulating layer, is made of a conductive composition, has an axis that coincides with the lamination direction, and has a diameter that changes in the direction of the axis. And the interlayer connection body is provided on the opposite side through the second wiring pattern, and is formed of a conductive composition and is laminated. And a third interlayer connector having a shape that has an axis that matches the direction and a diameter that changes in the direction of the axis. These interlayer connection bodies can be provided at a high density in a small region, which can contribute to finer wiring boards.

  Based on the above, embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view schematically showing a configuration of a component built-in wiring board according to an embodiment of the present invention. As shown in FIG. 1, this component built-in wiring board has insulating layers 11, 12, 13, and 14, wiring layers (wiring patterns) 21, 22, 23, and 24 (= four layers in total, Among them, the wiring layers 22 and 23 are inner wiring layers), an interlayer connector 31, 32 and 33, a plate-like passive element component 41, and a connecting member (solder) 51.

  That is, this wiring board has a passive element component 41 configured in a plate shape as a built-in component, and this passive element component 41 has a terminal 41a on one surface of the plate configuration, 41a is located opposite to the connection land formed by the inner wiring layer 22. The terminal 41 a of the passive element component 41 and the connection land of the wiring layer 22 are electrically and mechanically connected by a connection member (solder) 51. A more specific configuration of the passive element component 41 is, for example, as described below with reference to FIG.

  FIG. 2 is a cross-sectional view schematically showing a configuration example of a passive element component built in the component built-in wiring board shown in FIG. As shown in FIG. 2, the passive element component 41 includes a terminal 41a, a plate-like inorganic material substrate (stainless alloy (SUS) plate) 41b, a dielectric layer 41c, a conductor layer (electrode layer) 41d, a via ( Contact) 41e and an interlayer insulating film 41f.

  The passive element component 41 in this example includes one capacitor as a passive element, and the capacitor is formed in a layered manner on one surface of the SUS plate 41b as a base material. Since the SUS plate 41b has conductivity, this is used to function as one electrode as a capacitor. A dielectric layer 41c having a predetermined area and thickness is formed on the SUS plate 41, and a conductor layer (electrode layer) 41d is formed on the dielectric layer 41c so as to cover the entire area on the dielectric layer 41c. ing. The conductor layer 41d may include a portion functioning as a wiring in addition to a portion functioning as an electrode layer. An interlayer insulating film 41f is formed so as to cover the entire region on the dielectric layer 41c and the side surfaces of the dielectric layer 41c and the conductor layer 41d.

  Further, conductive vias 41e and 41e are provided through the interlayer insulating film 41f, one of which is in contact with and conductive with the conductor layer 41d, and the other is in contact with and conductive with the SUS plate 41b. Further, terminals 41a and 41a are provided on and in contact with the via 41e. In this passive element component 41, for example, a thin film formation technique similar to a semiconductor manufacturing process can be used to form the dielectric layer 41c and the conductor layer 41d. For the formation of the interlayer insulating film 41f, the via 41e, and the terminal 41a, for example, surface mounting terminals having an area arrangement (grid-like arrangement) similar to the manufacturing technology of the semiconductor component of the wafer level chip scale package are formed. Technology can be used.

  As this passive element component 41, for example, a SUS plate 41b having a thickness sufficient for securing rigidity, for example, a thickness of about 35 μm is selected, and a dielectric layer 41c, a conductor layer 41d, an interlayer insulating film are formed on one surface thereof. The total thickness of 41f can be used, and it can be manufactured with a thickness of, for example, several μm, which is satisfactory for functioning these as a capacitor. In order to increase the capacitance as a capacitor, the dielectric layer 41c and the conductor layer 41d may be further multi-layered, but even in that case, the total thickness is only slightly increased. In other words, the passive element component 41 including the terminal 41a has a thickness of about 40 μm or less, and can have a thickness that cannot be realized by a general surface mount passive element component.

  That is, the passive element component 41 is significantly thinner than the general surface mount passive element components of 0603 size and 0402 size, and is as thin as a component having a semiconductor chip. Therefore, thinning is achieved as the component built-in wiring board shown in FIG. In other words, the effect of thinning is the configuration in which the built-in passive element component 41 is located between the wiring layers 22 and 23 adjacent to each other in the layer direction in which the interlayer connection 32 derived from screen printing (described later) is conducted. That is, a structure in which the component 41 is built in between the two adjacent wiring layers 22 and 23 is realized. That is, the passive element component 41 is incorporated so as to be included in the height of the interlayer connector 32.

  Returning to the description with reference to FIG. 1, the other structure as the component built-in wiring board is as follows. First, the wiring layers 21 and 24 are wiring layers on both main surfaces as a wiring board, and various components (not shown) can be mounted thereon. On both main surfaces except for the land portions of the wiring layers 21 and 24 on which solder (not shown) is to be mounted, solder melted at the time of solder connection is retained on the land portions and solder resists functioning as protective layers thereafter. A layer can be formed (thickness is, for example, about 20 μm). A Ni / Au plating layer (not shown) having high corrosion resistance may be formed on the surface layer of the land portion.

  Each of the wiring layers 22 and 23 is an inner wiring layer, and in order, the insulating layer 11 is between the wiring layer 21 and the wiring layer 22, and the insulating layers 12 and 13 are between the wiring layer 22 and the wiring layer 23. The insulating layer 14 is located between the wiring layer 23 and the wiring layer 24 and separates the wiring layers 21 to 24. Each of the wiring layers 21 to 24 is made of a metal (copper) foil having a thickness of about 9 μm to 18 μm, for example. On the land formed by the wiring layer 22, the passive element component 41 is mounted via the solder 51 as described above.

  As shown in the drawing, each of the insulating layers 11 to 14 is composed of a rigid insulating resin (for example, epoxy resin) and a reinforcing material (for example, glass cloth) that reinforces the resin. However, the reinforcing material of the insulating layer 12 does not exist in the region where the passive element component 41 is embedded. This is because the position corresponding to the built-in passive element component 41 is originally an opening of the insulating layer 12 and provides a space for embedding the passive element component 41. Thereafter, the insulating layers 12 and 13 are deformed or entered so as to fill the opening for the built-in passive element component 41, and there is no space that becomes a void inside. By providing a reinforcing material to each of the insulating layers 11 to 14, it is possible to obtain sufficient rigidity even though it is thinned as a component built-in wiring board.

  The thicknesses of the insulating layers 11 to 14 are, for example, about 30 μm to 70 μm for the insulating layer 11, about 70 μm to 100 μm for the insulating layer 12, about 40 μm to 50 μm for the insulating layer 13, and about 30 μm to 70 μm for the insulating layer 14. It can be. With the thickness of each of the insulating layers 11 to 14 as described above, the total thickness of the component built-in wiring board in which the passive element component 41 is embedded can be realized to about 250 μm.

  The wiring layer 21 and the wiring layer 22 can be conducted by an interlayer connector 31 that is sandwiched between the surfaces of the patterns and penetrates the insulating layer 11. Similarly, the wiring layer 22 and the wiring layer 23 can be conducted by an interlayer connector 32 that is sandwiched between the surfaces of the patterns and penetrates the insulating layers 12 and 13. The wiring layer 23 and the wiring layer 24 can be conducted by an interlayer connector 33 that is sandwiched between the surfaces of the patterns and penetrates the insulating layer 14.

  The interlayer connectors 31, 32, and 33 are derived from conductive bumps formed by screen printing of a conductive composition, and depend on the manufacturing process in the axial direction (up and down in the illustration of FIG. 1). The diameter changes in the direction of stacking. The diameter is thick, for example, 150 μm for the interlayer connectors 31 and 33 and 220 μm for the interlayer connector 32. These interlayer connectors 31, 32, and 33 can be provided in a small area with high density, and can contribute to finer wiring boards.

  Next, the manufacturing process of the component built-in wiring board shown in FIG. 1 will be described with reference to FIGS. 3 to 5 are process diagrams schematically showing a part of the manufacturing process of the component built-in wiring board shown in FIG. In these figures, the same or equivalent components as those shown in FIG.

  It demonstrates from FIG. FIG. 3 shows a manufacturing process of a portion centering on the insulating layer 11 in each configuration shown in FIG. First, as shown in FIG. 3 (a), a paste-like conductive composition to be the interlayer connector 31 is formed on a metal foil (electrolytic copper foil) 22A having a thickness of, for example, 9 μm (˜18 μm) by screen printing, for example. It is formed in a substantially conical bump shape (bottom diameter, for example, 150 μm, height, for example, 160 μm). This conductive composition is obtained by dispersing fine metal particles such as silver, gold and copper or fine carbon particles in a paste-like resin. For convenience of explanation, printing is performed on the lower surface of the metal foil 22A, but it may be printed on the upper surface (the following drawings are also the same). After the interlayer connector 31 is printed, it is dried and cured.

  Next, as shown in FIG. 3B, a prepreg 11A of FR-4 having a thickness of, for example, 70 μm (˜30 μm) is laminated on the metal foil 22A to penetrate the interlayer connector 31, and the head is Make it exposed. At the time of exposure or thereafter, the tip thereof may be crushed by plastic deformation (in any case, the shape of the interlayer connection body 31 has an axis that coincides with the stacking direction, and the diameter changes in the axial direction). Subsequently, as shown in FIG. 3C, a metal foil (electrolytic copper foil) 21A is laminated on the prepreg 11A, and the whole is integrated by pressing and heating. At this time, the metal foil 21A is in electrical continuity with the interlayer connector 31, and the prepreg 11A is completely cured to become the insulating layer 11.

  Next, as shown in FIG. 3D, patterning by, for example, well-known photolithography is performed on the metal foil 22A on one side, and this is processed into a wiring pattern 22 including connection lands. Then, as shown in FIG. 3E, a cream solder 51A is applied onto the connection lands obtained by processing, for example, by screen printing. Screen printing can be easily and efficiently printed in a predetermined pattern. It can also be applied by a dispenser instead of screen printing.

  Subsequently, the passive element component 41 having the terminal 41a is placed on the connection land via the cream solder 51A by, for example, a mounter. Then, for example, the solder paste 51A is reflowed by heating in a reflow furnace. Thereby, as shown in FIG. 3F, the wiring board material 1 in a state where the passive element component 41 is connected to the connection land of the wiring layer 22 by the solder 51 is obtained. The subsequent process using the wiring board material 1 will be described with reference to FIG.

  Next, a description will be given with reference to FIG. FIG. 4 shows a manufacturing process of a portion around each of the insulating layers 12, 13, and 14 in each configuration shown in FIG. First, what is shown in FIG. 4A is a material obtained by a process similar to that shown in FIGS. 3A to 3D. That is, the metal foil (electrolytic copper foil) 24A, the insulating layer 14, the interlayer connector 33, and the wiring layer 23 correspond to the metal foil 21A, the insulating layer 11, the interlayer connector 31, and the wiring layer 22 in FIG. .

  Next, as shown in FIG. 4B, a paste-like conductive composition that becomes the interlayer connector 32 is formed into a substantially conical bump shape (bottom diameter, for example, bottom surface) by, for example, screen printing at a predetermined position on the wiring layer 23. 220 μm in height, for example 200 μm). This conductive composition may be the same as that used in the interlayer connector 31. After the interlayer connector 32 is printed, it is dried and cured.

  Next, as shown in FIG. 4C, a prepreg 13A of FR-4 with a nominal thickness of 40 μm (˜50 μm) and a prepreg 12A of FR-4 with a nominal 70 μm (˜100 μm) are laminated on the wiring layer 23. Then, the interlayer connector 32 is penetrated so that its head is exposed. At the time of exposure or thereafter, the tip thereof may be crushed by plastic deformation (in any case, the shape of the interlayer connector 32 has an axis that coincides with the stacking direction, and the diameter changes in the axial direction). The wiring board material obtained as described above is referred to as a wiring board material 2.

  In addition, before the prepregs 13A and 12A shown in FIG. 4C are stacked, a component opening 12o having a size to accommodate the passive element component 41 is formed in advance for the prepreg 12A. The reinforcing material included in the prepreg 12A by the formation of the component opening 12o is also removed at the opening 12o as shown in the figure. Such removal of the reinforcing material is preferable in order to avoid the occurrence of stress that would lead to breakage by avoiding hitting when laminating the built-in passive element component 41.

  Next, a description will be given with reference to FIG. FIG. 5 is a diagram showing an arrangement relationship in which the wiring board materials 1 and 2 obtained above are stacked. Wiring board materials 1 and 2 are stacked and arranged in the arrangement as shown in FIG. Thereby, the prepregs 12A and 13A are completely cured, and the whole is laminated and integrated. At this time, due to the fluidity of the prepregs 12 </ b> A and 13 </ b> A obtained by heating, the prepregs 12 </ b> A and 13 </ b> A are deformed or enter the space around the passive element component 41 and no gap is generated. Further, the interlayer connector 32 is electrically connected to the wiring layer 22.

  After the laminating process shown in FIG. 5, the metal foils 24A and 21A on both the upper and lower surfaces are patterned in a predetermined manner using well-known photolithography, whereby the component built-in wiring board as shown in FIG. 1 can be obtained.

  As a modification, for the interlayer connectors 31, 32, 33, in addition to those derived from the conductive bumps obtained by printing the conductive composition described above, for example, metal bumps formed by metal plate etching, conductive composition filling It is also possible to appropriately select and employ a connection body obtained from the above, a conductor bump formed by plating, or the like. Further, the outer wiring layers 21 and 24 are formed at the stage of the respective wiring board materials 1 and 2 (for example, at the stage of FIG. 3D) other than patterning after the last lamination step. May be.

  The embodiment of the present invention has been described above. Next, a modified example of the passive element component 41 to be incorporated will be described. First, FIG. 6 is a cross-sectional view schematically showing a modification of the passive element component shown in FIG. In FIG. 6, the same or equivalent parts as those shown in FIG. Unless there is a matter to be added in particular, explanation of that part is omitted.

  The passive element component 41A includes a terminal 41a, a plate-like inorganic material substrate (silicon plate) 41bA, a dielectric layer 41c, a conductor layer (electrode layer) 41d, a via (contact) 41e, an interlayer insulating film 41f, a conductor It has 41 g of layers (electrode layers).

  The passive element component 41A in this example is provided with one capacitor as a passive element, similar to that shown in FIG. 2, but the capacitor is formed in a layer on one surface of the silicon plate 41bA as a base material. is there. The silicon plate 41bA has a function equivalent to that of a substrate in a semiconductor component, and therefore, a conductive layer 41g that functions as one electrode of a capacitor is newly provided. In the passive element component 41A, for example, a thin film formation technique similar to the semiconductor manufacturing process can be used to form the conductor layer 41g. The method for forming other portions is as already described in FIG.

  The passive element component 41A can be manufactured as follows, for example, by preparing a silicon wafer plate having a general thickness (for example, about 0.5 mm). That is, the total thickness of the conductor layer 41g, the dielectric layer 41c, the conductor layer 41d, and the interlayer insulating film 41f on one surface of the silicon plate is not a problem for causing them to function as a capacitor, for example, several μm After that, the silicon plate is back-ground to a thickness sufficient to ensure rigidity, for example, about 70 μm. That is, the passive element component 41A can be configured to have a thickness of 75 μm or less including the terminal 41a.

  Therefore, the passive element component 41A is significantly thinner than the 0603 size and 0402 size, which are general surface mount passive element components, and is as thin as a component having a semiconductor chip. Therefore, thinning is achieved as the component built-in wiring board shown in FIG.

  Note that, as shown in FIG. 6, in the form of using the silicon plate 41bA as the plate-like inorganic material base material, the process of forming elements on the surface is the process itself used in semiconductor manufacturing, and various passive types are used. It is easy to make a large number of element parts and further to form a passive network. By using the semiconductor manufacturing process, many advantages such as cost reduction and productivity improvement can be expected.

  7 is a circuit diagram showing a configuration example of a passive network that the passive element component 41A shown in FIG. 6 can have. This passive network is a two-terminal pair network, and is an example in which a third-order low-pass filter (LPF) is configured as a function from the input two terminals 41a and 41a to the output two terminals 41a and 41a. Thus, by adding a passive network composed of only passive elements (= R1, R2, L, C1, C2), the added value is improved as a passive element component.

  Various other variations of the configuration of the passive element component to be incorporated can be considered. In FIG. 2, although the case where the SUS board was used as the plate-like inorganic material base material 41b was described, a board made of copper, nickel, titanium or the like can be used as the base material having the same conductivity. Even if these metal plates are thin (for example, several tens of μm thick), they can maintain rigidity as a component, have good availability, and there is no problem in forming passive elements in layers on the surface. In particular, in the case of copper, it is the same material as the wiring pattern used for a general wiring board, and its surface is roughened to improve adhesion with the wiring board material to obtain a wiring board with less defects such as peeling. be able to.

  In FIG. 6, the case where a silicon plate is used as the plate-like inorganic material base 41bA has been described, but a ceramic or glass plate may be used instead. Even in these cases, even if it is thin (for example, several tens of μm thick), it can maintain rigidity as a component, has good availability, and there are many known techniques for forming passive elements in layers on the surface.

  Next, a component built-in wiring board according to another embodiment of the present invention will be described with reference to FIG. FIG. 8 is a longitudinal sectional view schematically showing the structure of a component built-in wiring board according to another embodiment. In the figure, the same or equivalent components as those already described are denoted by the same reference numerals. The description is omitted unless there is a matter to add to that portion.

  This embodiment includes a semiconductor component 42 as a built-in component, in addition to the passive element component 41, which is a different component. The semiconductor component 42 is an element based on a wafer level chip scale package, and includes at least a semiconductor chip and a grid-shaped array of surface mounting terminals 42a formed on the semiconductor chip. The surface mounting terminal 42a is a terminal provided by rearranging its position while being electrically conducted through a rewiring layer from a terminal pad that the semiconductor chip originally has. By such rearrangement, the arrangement density as a terminal is coarser than that of the terminal pad on the semiconductor chip. Thereby, the semiconductor component 42 is mounted on the connection land by the wiring layer 22 via the connection member (solder) 52 by the surface mounting technique.

  The passive element component 41 and the semiconductor component 42 have substantially the same thickness. In other words, the added value is increased by the mixed mounting, and the thinning is realized as the mixed component built-in wiring board. Further, the surface mount technology similar to that of the passive element component 41 can be used to connect the semiconductor component 42 to the land, and the cost can be reduced by efficient mounting.

  FIG. 9 is a process diagram schematically showing a part of the manufacturing process of the component built-in wiring board shown in FIG. 8 and corresponds to the stage of the process shown in FIG. 4 already described. In FIG. 9, the same reference numerals are given to the same or equivalent components as those already described. The description is omitted unless there is a matter to add to that portion.

  The wiring board materials 1A and 2A used in this laminating process are configured as shown. That is, on the wiring board material 1 </ b> A, in addition to the passive element component 41, the semiconductor component 42 is mounted via the solder 51 and the solder 52, respectively. In the process of mounting these, the passive element component 41 and the semiconductor component 42 can be connected to the land at the same time by the same method (printing and reflowing of the solders 51 and 52). Therefore, manufacturing efficiency is good. In the wiring board material 2 </ b> A, an opening 12 o is provided in the prepreg 12 </ b> A corresponding to the semiconductor component 42 in order to avoid hitting when stacked on the semiconductor component 42.

  Next, a component built-in wiring board according to still another embodiment of the present invention will be described with reference to FIG. FIG. 10 is a longitudinal sectional view schematically showing the structure of a component built-in wiring board according to still another embodiment. In the figure, the same or equivalent components as those already described are denoted by the same reference numerals. The description is omitted unless there is a matter to add to that portion.

  In this embodiment, the passive component 41AA that is flip-connected and the semiconductor component 42AA that is also flip-connected are provided as built-in components. Flip connection is generally well known for semiconductor components. In flip connection, since a bare semiconductor chip is used as a semiconductor component, that is, it is not necessary to be a package product, various semiconductor components can be used. The configuration around the semiconductor component 42AA will be described below.

  A bare semiconductor chip included in the semiconductor component 42AA is electrically connected to a connection land formed by the wiring layer 22 via a protruding electrode (conductor bump) 52AA by flip connection. For this connection, a protruding electrode 52AA is formed in advance on a terminal pad (not shown) included in the semiconductor chip of the semiconductor component 42AA, and a land is formed as a part of the wiring layer 22 in alignment with the protruding electrode 52AA. A pattern is formed. The protruding electrode 52AA is made of, for example, Au (gold) as a material, and is previously formed in a stud shape on the terminal pad. An underfill resin 62 is filled between the semiconductor chip and the wiring layer 22 and the insulating layer 11 for mechanical and chemical protection of the flip connection portion.

  In this embodiment, the passive element component 41AA is also mounted on the land of the wiring layer 22 via the protruding electrode 51AA by the same method as the flip connection of the semiconductor component 42AA. Similarly to the semiconductor component 42AA, the passive element component 41AA also has a plate-like inorganic material base material. The passive element is formed in a layer on one surface of the inorganic material base material, and the terminal is inorganic. This is possible because it is provided on one surface of the material substrate.

  Protrusion electrode 51AA is provided on passive element component 41AA, and underfill resin 61 is provided between passive element component 41AA and wiring layer 22 and insulating layer 11 for mechanical and chemical protection of the flip connection portion. Is similar to the semiconductor component 42AA. In this embodiment as well, the added value is increased by mixed mounting, and a thin plate is realized as a mixed component built-in wiring board.

  FIG. 11 is a process diagram schematically showing a part of the manufacturing process of the component built-in wiring board shown in FIG. 10 and corresponds to the stage of the process shown in FIG. 4 already described. In FIG. 11, the same or equivalent components as those already described are denoted by the same reference numerals. The description is omitted unless there is a matter to add to that portion.

  The wiring board material 2A used in this laminating process has the same configuration as that shown in FIG. 9, and the wiring board material 1B has a configuration as shown in the figure. That is, on the wiring board material 1B, in addition to the passive element component 41AA, the semiconductor component 42AA is mounted by flip connection.

  To obtain the wiring board material 1B, for example, the following is performed. First, underfill resins 62 and 61 before curing are applied to a position on the insulating layer 11 where the semiconductor component 42AA and the passive element component 41AA are to be mounted using, for example, a dispenser. Subsequently, the semiconductor component 42AA with the protruding electrode 52AA and the passive element component 41AA with the protruding electrode 51AA are aligned and pressed against the land by the wiring layer 22 using, for example, a flip chip bonder. After the pressure welding, a heating step is performed to improve the connection strength and to cure the underfill resins 62 and 61. Thus, the wiring board material 1B is obtained.

  DESCRIPTION OF SYMBOLS 1,1A, 1B ... Wiring board material, 2, 2A ... Wiring board material, 11, 12, 13, 14 ... Insulating layer with a reinforcing material, 11A, 12A, 13A ... Prepreg with a reinforcing material, 12o ... Opening for parts, 21, 22, 23, 24... Wiring layer (wiring pattern), 21 A, 22 A, 24 A... Metal foil (copper foil), 31, 32, 33 ... interlayer connection (conductive bump by conductive composition printing), 41 , 41A ... passive element parts (plate-like), 41a ... terminals, 41b ... plate-like inorganic material substrate (stainless alloy (SUS) plate), 41bA ... plate-like inorganic material substrate (silicon plate), 41c ... dielectric Body layer, 41d ... conductor layer (electrode layer), 41e ... via (contact), 41f ... interlayer insulating film, 41g ... conductor layer (electrode layer), 41AA ... passive element component (plate-like flip connection), 42 ... Semiconductor parts (wafer level) 42a ... grid array (area arrangement) surface mounting terminals, 42AA ... semiconductor components (bare semiconductor chip), 51,52 ... connecting member (solder), 51A ... cream solder, 51AA, 52AA ... projection electrodes (gold stud bumps), 61, 62 ... underfill resin.

Claims (13)

A first insulating layer;
A second insulating layer positioned in a stack with respect to the first insulating layer;
A passive element component having a plurality of terminals embedded in the second insulating layer;
A first wiring pattern including a connection land for the passive element component provided between the first insulating layer and the second insulating layer;
A connection member for electrically connecting the plurality of terminals of the passive element component and the connection land of the first wiring pattern;
A second wiring pattern that is an inner layer wiring pattern provided so as to be buried in the second insulating layer as a wiring layer immediately adjacent to the first wiring pattern;
The passive element component has a plate-like inorganic material substrate and a passive element formed in a layer on one surface of the inorganic material substrate, and the plurality of terminals of the passive element component are A terminal electrically connected to a passive element and provided on the one surface side of the inorganic material base;
The second insulating layer includes a layered first reinforcing material provided by retracting a position of the passive element component between the first wiring pattern and the second wiring pattern; A layered second reinforcing material provided so as to overlap the first reinforcing material and the passive element component on the second wiring pattern side when viewed from the one reinforcing material. Component built-in wiring board.   2. The component built-in wiring board according to claim 1, wherein the inorganic material substrate of the passive element component is a kind of conductive substrate selected from the group consisting of stainless alloy, copper, nickel, and titanium. . The passive element of the passive element component is a capacitor;
The inorganic material substrate of the passive element component is electrically connected to one of the plurality of terminals and is one electrode of the capacitor that is the passive element. Item 2. The component built-in wiring board according to Item 2.   2. The component built-in according to claim 1, wherein the inorganic material substrate of the passive element component is a kind of semiconductor substrate or non-conductive substrate selected from the group consisting of silicon, ceramic, and glass. Wiring board. The inorganic material substrate of the passive element component is silicon;
The component built-in wiring board according to claim 4, wherein the passive element of the passive element component is a kind selected from the group consisting of a capacitor, a resistor, and an inductor. The inorganic material substrate of the passive element component is silicon;
The passive element component has a plurality of passive elements formed in layers on the one surface of the inorganic material substrate, the plurality of passive elements constitute a passive network, and the passive element component A part of the plurality of terminals is an input terminal of the passive network, and another part of the plurality of terminals of the passive element component is an output terminal of the passive network. Item 1. The component built-in wiring board according to Item 1. The wiring pattern further includes a second connection land for a semiconductor component;
A semiconductor component further embedded in the second insulating layer, having a semiconductor chip and having substantially the same thickness as the passive element component;
A second connection member for electrically connecting the terminal of the semiconductor component and the second connection land of the wiring pattern;
The first reinforcing material contained in the second insulating layer is provided by retracting the position of the semiconductor component, and the second reinforcing material contained in the second insulating layer is The first reinforcing material, the passive element component, and the semiconductor component are provided so as to overlap with each other on the second wiring pattern side as viewed from the first reinforcing material. Item 1. The component built-in wiring board according to Item 1.   The component built-in wiring board according to claim 7, wherein the connection member is made of the same material as the second connection member.   9. The component built-in wiring board according to claim 8, wherein the connection member and the second connection member are solder.   The semiconductor chip of the semiconductor component includes a terminal pad, and the semiconductor component includes, as the terminal, a surface-mounting terminal in a grid-like arrangement that is electrically connected to the terminal pad. Item 7. The component built-in wiring board according to Item 7. The semiconductor chip of the semiconductor component has a terminal pad;
The component built-in wiring board according to claim 7, wherein the second connection member is a protruding electrode formed on the terminal pad of the semiconductor chip. The second insulating layer passes through a part in the stacking direction, is sandwiched between the surface of the first wiring pattern and the surface of the second wiring pattern, is made of a conductive composition, and is stacked 2. The component built-in wiring board according to claim 1, further comprising an interlayer connector having an axis that coincides with the direction and having a shape in which the diameter changes in the direction of the axis. A second interlayer connector having a shape that penetrates the first insulating layer and is made of a conductive composition and has an axis that coincides with the stacking direction and has a diameter that changes in the direction of the axis;
Passing through a part of the second insulating layer in the stacking direction, the interlayer connector is provided on the opposite side through the second wiring pattern, and is made of a conductive composition and coincides with the stacking direction. 13. The component built-in wiring board according to claim 12, further comprising: a third interlayer connector having a shape that has a shaft that changes in diameter in the direction of the shaft.

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