JP5683813B2 - 混合されたタイプのメモリデバイスを動作させるシステムおよび方法 - Google Patents

混合されたタイプのメモリデバイスを動作させるシステムおよび方法 Download PDF

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Publication number
JP5683813B2
JP5683813B2 JP2009539576A JP2009539576A JP5683813B2 JP 5683813 B2 JP5683813 B2 JP 5683813B2 JP 2009539576 A JP2009539576 A JP 2009539576A JP 2009539576 A JP2009539576 A JP 2009539576A JP 5683813 B2 JP5683813 B2 JP 5683813B2
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Japan
Prior art keywords
memory
address
type
serial
command
Prior art date
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Expired - Fee Related
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JP2009539576A
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English (en)
Japanese (ja)
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JP2010511943A5 (enrdf_load_stackoverflow
JP2010511943A (ja
Inventor
ハクジュン・オ
ホン・ボム・ピョン
ジン−キ・キム
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Mosaid Technologies Inc
Original Assignee
Conversant Intellectual Property Management Inc
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Filing date
Publication date
Priority claimed from US11/622,828 external-priority patent/US8271758B2/en
Priority claimed from US11/771,241 external-priority patent/US7925854B2/en
Application filed by Conversant Intellectual Property Management Inc filed Critical Conversant Intellectual Property Management Inc
Publication of JP2010511943A publication Critical patent/JP2010511943A/ja
Publication of JP2010511943A5 publication Critical patent/JP2010511943A5/ja
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Memory System (AREA)
  • Information Transfer Systems (AREA)
JP2009539576A 2006-12-06 2007-12-04 混合されたタイプのメモリデバイスを動作させるシステムおよび方法 Expired - Fee Related JP5683813B2 (ja)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US86877306P 2006-12-06 2006-12-06
US60/868,773 2006-12-06
US87089206P 2006-12-20 2006-12-20
US60/870,892 2006-12-20
US11/622,828 US8271758B2 (en) 2006-12-06 2007-01-12 Apparatus and method for producing IDS for interconnected devices of mixed type
US11/622,828 2007-01-12
US11/771,241 2007-06-29
US11/771,241 US7925854B2 (en) 2006-12-06 2007-06-29 System and method of operating memory devices of mixed type
PCT/CA2007/002182 WO2008067658A1 (en) 2006-12-06 2007-12-04 System and method of operating memory devices of mixed type

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP2010257825A Division JP5351130B2 (ja) 2006-12-06 2010-11-18 混合されたタイプのメモリデバイスを動作させるシステムおよび方法
JP2013257579A Division JP5695724B2 (ja) 2006-12-06 2013-12-13 混合されたタイプのメモリデバイスを動作させるシステムおよび方法

Publications (3)

Publication Number Publication Date
JP2010511943A JP2010511943A (ja) 2010-04-15
JP2010511943A5 JP2010511943A5 (enrdf_load_stackoverflow) 2011-01-20
JP5683813B2 true JP5683813B2 (ja) 2015-03-11

Family

ID=39491613

Family Applications (3)

Application Number Title Priority Date Filing Date
JP2009539576A Expired - Fee Related JP5683813B2 (ja) 2006-12-06 2007-12-04 混合されたタイプのメモリデバイスを動作させるシステムおよび方法
JP2010257825A Expired - Fee Related JP5351130B2 (ja) 2006-12-06 2010-11-18 混合されたタイプのメモリデバイスを動作させるシステムおよび方法
JP2013257579A Expired - Fee Related JP5695724B2 (ja) 2006-12-06 2013-12-13 混合されたタイプのメモリデバイスを動作させるシステムおよび方法

Family Applications After (2)

Application Number Title Priority Date Filing Date
JP2010257825A Expired - Fee Related JP5351130B2 (ja) 2006-12-06 2010-11-18 混合されたタイプのメモリデバイスを動作させるシステムおよび方法
JP2013257579A Expired - Fee Related JP5695724B2 (ja) 2006-12-06 2013-12-13 混合されたタイプのメモリデバイスを動作させるシステムおよび方法

Country Status (5)

Country Link
EP (1) EP2118903A4 (enrdf_load_stackoverflow)
JP (3) JP5683813B2 (enrdf_load_stackoverflow)
KR (3) KR101441280B1 (enrdf_load_stackoverflow)
TW (1) TWI470645B (enrdf_load_stackoverflow)
WO (1) WO2008067658A1 (enrdf_load_stackoverflow)

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US9697872B2 (en) * 2011-12-07 2017-07-04 Cypress Semiconductor Corporation High speed serial peripheral interface memory subsystem
US8614920B2 (en) 2012-04-02 2013-12-24 Winbond Electronics Corporation Method and apparatus for logic read in flash memory
JP5467134B1 (ja) * 2012-09-27 2014-04-09 華邦電子股▲ふん▼有限公司 フラッシュメモリ装置およびメモリ装置の操作方法
KR102366767B1 (ko) * 2015-07-30 2022-02-23 에스케이하이닉스 주식회사 반도체 장치
US10067903B2 (en) 2015-07-30 2018-09-04 SK Hynix Inc. Semiconductor device
KR102358177B1 (ko) 2015-12-24 2022-02-07 에스케이하이닉스 주식회사 제어회로 및 제어회로를 포함하는 메모리 장치
US11755255B2 (en) 2014-10-28 2023-09-12 SK Hynix Inc. Memory device comprising a plurality of memories sharing a resistance for impedance matching
US10146608B2 (en) * 2015-04-06 2018-12-04 Rambus Inc. Memory module register access
FR3041806B1 (fr) * 2015-09-25 2017-10-20 Stmicroelectronics Rousset Dispositif de memoire non volatile, par exemple du type eeprom, ayant une capacite memoire importante, par exemple 16mbits
GB2568724B (en) * 2017-11-24 2021-08-18 Ge Aviat Systems Ltd Method and apparatus for initializing a controller module
GB2568725B (en) 2017-11-24 2021-08-18 Ge Aviat Systems Ltd Method and apparatus for initializing a controller module
CN110413197B (zh) * 2018-04-28 2023-06-27 伊姆西Ip控股有限责任公司 管理存储系统的方法、设备和计算机程序产品
TWI696113B (zh) * 2019-01-02 2020-06-11 慧榮科技股份有限公司 用來進行組態管理之方法以及資料儲存裝置及其控制器
US20210081318A1 (en) 2019-09-17 2021-03-18 Micron Technology, Inc. Flexible provisioning of multi-tier memory
TWI749598B (zh) * 2020-06-18 2021-12-11 華邦電子股份有限公司 一種記憶體裝置及其連續讀寫方法
US11120851B1 (en) 2020-07-12 2021-09-14 Winbond Electronics Corp. Memory apparatus and burst read and burst write method thereof
CN113641595B (zh) * 2021-07-30 2023-08-11 珠海一微半导体股份有限公司 独立块保护模式的spi flash在brom阶段的类型识别方法及系统
US20230153094A1 (en) * 2021-11-18 2023-05-18 Toyota Motor North America, Inc. Robust over the air reprogramming

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Also Published As

Publication number Publication date
KR20090102787A (ko) 2009-09-30
JP5351130B2 (ja) 2013-11-27
EP2118903A1 (en) 2009-11-18
TWI470645B (zh) 2015-01-21
KR101441280B1 (ko) 2014-09-17
JP5695724B2 (ja) 2015-04-08
KR101441225B1 (ko) 2014-09-17
TW200845037A (en) 2008-11-16
KR101441154B1 (ko) 2014-09-17
KR20120135334A (ko) 2012-12-12
WO2008067658A1 (en) 2008-06-12
JP2011054204A (ja) 2011-03-17
KR20140019478A (ko) 2014-02-14
JP2010511943A (ja) 2010-04-15
JP2014063523A (ja) 2014-04-10
EP2118903A4 (en) 2010-01-06

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