JP5665974B2 - 単一のバッファを用いて複数のメモリ素子を同時にリードする方法及び装置 - Google Patents

単一のバッファを用いて複数のメモリ素子を同時にリードする方法及び装置 Download PDF

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Publication number
JP5665974B2
JP5665974B2 JP2013508340A JP2013508340A JP5665974B2 JP 5665974 B2 JP5665974 B2 JP 5665974B2 JP 2013508340 A JP2013508340 A JP 2013508340A JP 2013508340 A JP2013508340 A JP 2013508340A JP 5665974 B2 JP5665974 B2 JP 5665974B2
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data
page buffer
memory
read
ready
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Japanese (ja)
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JP2013525924A (ja
JP2013525924A5 (enExample
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シュエッツ，ローランド
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Mosaid Technologies Inc
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Conversant Intellectual Property Management Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Information Transfer Systems (AREA)
  • Memory System (AREA)
JP2013508340A 2010-05-07 2011-05-06 単一のバッファを用いて複数のメモリ素子を同時にリードする方法及び装置 Expired - Fee Related JP5665974B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US33223210P 2010-05-07 2010-05-07
US61/332,232 2010-05-07
PCT/CA2011/050281 WO2011137541A1 (en) 2010-05-07 2011-05-06 Method and apparatus for concurrently reading a plurality of memory devices using a single buffer

Publications (3)

Publication Number Publication Date
JP2013525924A JP2013525924A (ja) 2013-06-20
JP2013525924A5 JP2013525924A5 (enExample) 2014-04-03
JP5665974B2 true JP5665974B2 (ja) 2015-02-04

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JP2013508340A Expired - Fee Related JP5665974B2 (ja) 2010-05-07 2011-05-06 単一のバッファを用いて複数のメモリ素子を同時にリードする方法及び装置

Country Status (8)

Country Link
US (1) US20110276775A1 (enExample)
EP (1) EP2567379A4 (enExample)
JP (1) JP5665974B2 (enExample)
KR (1) KR20130071436A (enExample)
CN (1) CN102971795A (enExample)
CA (1) CA2798868A1 (enExample)
TW (1) TW201209820A (enExample)
WO (1) WO2011137541A1 (enExample)

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US12164767B2 (en) 2022-03-22 2024-12-10 Kioxia Corporation Semiconductor device

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US12164767B2 (en) 2022-03-22 2024-12-10 Kioxia Corporation Semiconductor device

Also Published As

Publication number Publication date
JP2013525924A (ja) 2013-06-20
CN102971795A (zh) 2013-03-13
CA2798868A1 (en) 2011-11-10
US20110276775A1 (en) 2011-11-10
WO2011137541A1 (en) 2011-11-10
TW201209820A (en) 2012-03-01
KR20130071436A (ko) 2013-06-28
EP2567379A1 (en) 2013-03-13
EP2567379A4 (en) 2014-01-22

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