JP5656647B2 - Icパッケージの製造方法 - Google Patents

Icパッケージの製造方法 Download PDF

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Publication number
JP5656647B2
JP5656647B2 JP2010547689A JP2010547689A JP5656647B2 JP 5656647 B2 JP5656647 B2 JP 5656647B2 JP 2010547689 A JP2010547689 A JP 2010547689A JP 2010547689 A JP2010547689 A JP 2010547689A JP 5656647 B2 JP5656647 B2 JP 5656647B2
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JP
Japan
Prior art keywords
substrate
die
recess
capacitor
package
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Expired - Fee Related
Application number
JP2010547689A
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English (en)
Japanese (ja)
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JP2011513949A (ja
Inventor
スケッテ、オスワルド、エル.
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Intel Corp
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Intel Corp
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Publication date
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Publication of JP2011513949A publication Critical patent/JP2011513949A/ja
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Expired - Fee Related legal-status Critical Current
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/16Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Variable-Direction Aerials And Aerial Arrays (AREA)
JP2010547689A 2008-02-22 2009-02-11 Icパッケージの製造方法 Expired - Fee Related JP5656647B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/036,143 US8035216B2 (en) 2008-02-22 2008-02-22 Integrated circuit package and method of manufacturing same
US12/036,143 2008-02-22
PCT/US2009/033728 WO2009105367A2 (en) 2008-02-22 2009-02-11 Integrated circuit package and method of manufacturing same

Publications (2)

Publication Number Publication Date
JP2011513949A JP2011513949A (ja) 2011-04-28
JP5656647B2 true JP5656647B2 (ja) 2015-01-21

Family

ID=40986134

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010547689A Expired - Fee Related JP5656647B2 (ja) 2008-02-22 2009-02-11 Icパッケージの製造方法

Country Status (6)

Country Link
US (1) US8035216B2 (zh)
JP (1) JP5656647B2 (zh)
KR (1) KR101297536B1 (zh)
CN (1) CN101952959B (zh)
TW (1) TWI411071B (zh)
WO (1) WO2009105367A2 (zh)

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US8535989B2 (en) 2010-04-02 2013-09-17 Intel Corporation Embedded semiconductive chips in reconstituted wafers, and systems containing same
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US8304913B2 (en) 2010-09-24 2012-11-06 Intel Corporation Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby
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Also Published As

Publication number Publication date
TW201005895A (en) 2010-02-01
KR101297536B1 (ko) 2013-08-16
KR20100103712A (ko) 2010-09-27
US20090212416A1 (en) 2009-08-27
WO2009105367A2 (en) 2009-08-27
JP2011513949A (ja) 2011-04-28
WO2009105367A3 (en) 2009-10-29
TWI411071B (zh) 2013-10-01
CN101952959A (zh) 2011-01-19
CN101952959B (zh) 2013-04-24
US8035216B2 (en) 2011-10-11

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