JP2011513949A - Icパッケージおよびその製造方法 - Google Patents
Icパッケージおよびその製造方法 Download PDFInfo
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- JP2011513949A JP2011513949A JP2010547689A JP2010547689A JP2011513949A JP 2011513949 A JP2011513949 A JP 2011513949A JP 2010547689 A JP2010547689 A JP 2010547689A JP 2010547689 A JP2010547689 A JP 2010547689A JP 2011513949 A JP2011513949 A JP 2011513949A
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- substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
【選択図】図1
Description
Claims (20)
- 第1表面および対向する第2表面を有し、かつ凹部を含む基板と、
前記基板の前記第1表面に隣接するダイプラットフォームと、
前記基板の前記凹部に設けられたコンデンサと
を備えるICパッケージ。 - 前記ダイプラットフォームは、ダイと、前記ダイに隣接する複数のビルドアップ層と、前記複数のビルドアップ層に隣接する複数のインターコネクト構造とを含むバンプレスビルドアップ層コンポーネントを有する請求項1に記載のICパッケージ。
- 前記凹部は、前記基板の前記第1表面にある請求項2に記載のICパッケージ。
- 前記コンデンサは、前記ダイプラットフォームに物理的に取り付けられている請求項3に記載のICパッケージ。
- 前記基板の前記第2表面のほとんど全てが複数のインターコネクト構造アレイによって覆われる請求項4に記載のICパッケージ。
- 前記複数のインターコネクト構造は、前記ダイプラットフォームの第1表面に位置し、前記複数のインターコネクト構造は、前記ダイプラットフォームの前記第1表面の一部を覆うアレイを形成する請求項5に記載のICパッケージ。
- 前記凹部は、前記基板の前記第2表面にある請求項2に記載のICパッケージ。
- 前記複数のインターコネクト構造は、前記ダイプラットフォームの第1表面に位置し、前記複数のインターコネクト構造は、前記ダイプラットフォームの前記第1表面のほとんど全てを覆うアレイを形成する請求項7に記載のICパッケージ。
- 前記基板の前記第2表面の一部がインターコネクト構造アレイによって覆われる請求項8に記載のICパッケージ。
- 第1表面および対向する第2表面を有し、凹部を含む基板と、
前記基板の前記第1表面に物理的および電気的に結合したバンプレスビルドアップ層コンポーネントと、
前記基板の前記凹部に設けられた複数のコンデンサと
を備え、
前記バンプレスビルドアップ層コンポーネントは、
ダイと、
前記ダイに隣接する複数のビルドアップ層と、
前記複数のビルドアップ層に隣接するバンプレスビルドアップ層グリッドアレイと
を有するICパッケージ。 - 前記凹部は前記基板の前記第1表面にあり、前記複数のコンデンサは前記バンプレスビルドアップ層コンポーネントに物理的に取り付けられている請求項10に記載のICパッケージ。
- 前記基板の前記第2表面のほとんど全てが複数のインターコネクト構造アレイによって覆われる請求項11に記載のICパッケージ。
- 前記凹部は、前記基板の前記第2表面にあり、前記バンプレスビルドアップ層グリッドアレイは前記バンプレスビルドアップ層コンポーネントの第1表面に位置し、前記バンプレスビルドアップ層グリッドアレイは前記バンプレスビルドアップ層コンポーネントの前記第1表面のほとんど全てを覆う請求項10に記載のICパッケージ。
- 第1表面および対向する第2表面を有し、凹部を含む基板を用意する段階と、
前記基板の前記第1表面にダイプラットフォームを取り付ける段階と、
前記基板の前記凹部にコンデンサを配置する段階と
を備えるICパッケージの製造方法。 - 前記ダイプラットフォームを取り付ける段階は、ダイと、前記ダイに隣接する複数のビルドアップ層と、前記複数のビルドアップ層に隣接する複数のインターコネクト構造とを有するバンプレスビルドアップ層コンポーネントを取り付ける段階を有する請求項14に記載の方法。
- 前記凹部は、前記基板の前記第1表面にある請求項14に記載の方法。
- 前記ダイプラットフォームに前記コンデンサを物理的に取り付ける段階をさらに備える請求項16に記載の方法。
- 前記基板の前記第2表面のほとんど全てが複数のインターコネクト構造アレイによって覆われる請求項17に記載の方法。
- 前記凹部は、前記基板の前記第2表面にある請求項14に記載の方法。
- 前記ダイプラットフォームを取り付ける段階は、
ダイと、前記ダイに隣接する複数のビルドアップ層と、前記複数のビルドアップ層に隣接する複数のインターコネクト構造とを含むバンプレスビルドアップ層コンポーネントを取り付ける段階を有し、
前記複数のインターコネクト構造は、前記ダイプラットフォームの第1表面に位置し、
前記複数のインターコネクト構造は、前記ダイプラットフォームの前記第1表面のほとんど全てを覆うアレイを形成する請求項19に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/036,143 US8035216B2 (en) | 2008-02-22 | 2008-02-22 | Integrated circuit package and method of manufacturing same |
US12/036,143 | 2008-02-22 | ||
PCT/US2009/033728 WO2009105367A2 (en) | 2008-02-22 | 2009-02-11 | Integrated circuit package and method of manufacturing same |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011513949A true JP2011513949A (ja) | 2011-04-28 |
JP5656647B2 JP5656647B2 (ja) | 2015-01-21 |
Family
ID=40986134
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010547689A Expired - Fee Related JP5656647B2 (ja) | 2008-02-22 | 2009-02-11 | Icパッケージの製造方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US8035216B2 (ja) |
JP (1) | JP5656647B2 (ja) |
KR (1) | KR101297536B1 (ja) |
CN (1) | CN101952959B (ja) |
TW (1) | TWI411071B (ja) |
WO (1) | WO2009105367A2 (ja) |
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2008
- 2008-02-22 US US12/036,143 patent/US8035216B2/en not_active Expired - Fee Related
-
2009
- 2009-02-11 WO PCT/US2009/033728 patent/WO2009105367A2/en active Application Filing
- 2009-02-11 CN CN200980105803.0A patent/CN101952959B/zh active Active
- 2009-02-11 JP JP2010547689A patent/JP5656647B2/ja not_active Expired - Fee Related
- 2009-02-11 KR KR1020107018559A patent/KR101297536B1/ko active IP Right Grant
- 2009-02-13 TW TW098104692A patent/TWI411071B/zh active
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JP2005129899A (ja) * | 2003-08-28 | 2005-05-19 | Kyocera Corp | 配線基板および半導体装置 |
JP2006203079A (ja) * | 2005-01-21 | 2006-08-03 | Sharp Corp | 半導体装置および半導体装置の製造方法 |
Cited By (1)
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JP2018520507A (ja) * | 2015-06-25 | 2018-07-26 | インテル コーポレイション | リセスを有するインターポーザを用いた集積回路構造 |
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JP5656647B2 (ja) | 2015-01-21 |
TWI411071B (zh) | 2013-10-01 |
US20090212416A1 (en) | 2009-08-27 |
CN101952959A (zh) | 2011-01-19 |
TW201005895A (en) | 2010-02-01 |
US8035216B2 (en) | 2011-10-11 |
KR20100103712A (ko) | 2010-09-27 |
WO2009105367A2 (en) | 2009-08-27 |
KR101297536B1 (ko) | 2013-08-16 |
WO2009105367A3 (en) | 2009-10-29 |
CN101952959B (zh) | 2013-04-24 |
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