JP5590605B2 - セルフリフレッシュ・モードのためのメモリ・デバイス制御 - Google Patents

セルフリフレッシュ・モードのためのメモリ・デバイス制御 Download PDF

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Publication number
JP5590605B2
JP5590605B2 JP2010100474A JP2010100474A JP5590605B2 JP 5590605 B2 JP5590605 B2 JP 5590605B2 JP 2010100474 A JP2010100474 A JP 2010100474A JP 2010100474 A JP2010100474 A JP 2010100474A JP 5590605 B2 JP5590605 B2 JP 5590605B2
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Japan
Prior art keywords
cke
power module
memory controller
memory
memory device
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Expired - Fee Related
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JP2010100474A
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English (en)
Japanese (ja)
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JP2010262645A (ja
JP2010262645A5 (enExample
Inventor
エヌ． バクタ ダーメッシュクマー
シー． クリッツ ジョン
デー． パーソン エリック
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LSI Corp
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LSI Logic Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • G06F1/3225—Monitoring of peripheral devices of memory devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G11C5/144—Detection of predetermined disconnection or reduction of power supply, e.g. power down or power standby
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4067—Refresh in standby or low power modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Power Sources (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
JP2010100474A 2009-04-29 2010-04-26 セルフリフレッシュ・モードのためのメモリ・デバイス制御 Expired - Fee Related JP5590605B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/431,876 US7869300B2 (en) 2009-04-29 2009-04-29 Memory device control for self-refresh mode
US12/431,876 2009-04-29

Publications (3)

Publication Number Publication Date
JP2010262645A JP2010262645A (ja) 2010-11-18
JP2010262645A5 JP2010262645A5 (enExample) 2013-05-23
JP5590605B2 true JP5590605B2 (ja) 2014-09-17

Family

ID=42226108

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010100474A Expired - Fee Related JP5590605B2 (ja) 2009-04-29 2010-04-26 セルフリフレッシュ・モードのためのメモリ・デバイス制御

Country Status (6)

Country Link
US (1) US7869300B2 (enExample)
EP (1) EP2246769A1 (enExample)
JP (1) JP5590605B2 (enExample)
KR (1) KR20100118950A (enExample)
CN (1) CN101882464B (enExample)
TW (1) TWI527030B (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012115839A1 (en) 2011-02-23 2012-08-30 Rambus Inc. Protocol for memory power-mode control
US9159397B2 (en) 2012-12-04 2015-10-13 Micron Technology, Inc. Methods and apparatuses for refreshing memory
JP2014146115A (ja) * 2013-01-28 2014-08-14 Canon Inc データ処理装置およびその制御方法
US10055370B2 (en) * 2014-07-09 2018-08-21 Advanced Micro Devices, Inc. Method and apparatis for processor standby
US9142280B1 (en) 2014-08-06 2015-09-22 Freescale Semiconducotr, Inc. Circuit for configuring external memory
CA3034395A1 (en) * 2015-08-24 2017-03-02 Src Labs, Llc System and method for retaining dram data when reprogramming reconfigurable devices with dram memory controllers incorporating a data maintenance block colocated with a memory module or subsystem
JP6516630B2 (ja) * 2015-08-26 2019-05-22 キヤノン株式会社 メモリ制御回路及びその制御方法
KR102535182B1 (ko) 2016-07-27 2023-05-23 에스케이하이닉스 주식회사 반도체 장치
US11176986B2 (en) * 2019-12-30 2021-11-16 Advanced Micro Devices, Inc. Memory context restore, reduction of boot time of a system on a chip by reducing double data rate memory training

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5831467A (en) * 1991-11-05 1998-11-03 Monolithic System Technology, Inc. Termination circuit with power-down mode for use in circuit module architecture
US6564329B1 (en) * 1999-03-16 2003-05-13 Linkup Systems Corporation System and method for dynamic clock generation
US6829677B1 (en) * 2000-05-18 2004-12-07 International Business Machines Corporation Method and apparatus for preserving the contents of synchronous DRAM through system reset
TW588235B (en) * 2001-04-02 2004-05-21 Via Tech Inc Motherboard with less power consumption
JP3799251B2 (ja) * 2001-08-24 2006-07-19 エルピーダメモリ株式会社 メモリデバイス及びメモリシステム
KR100502664B1 (ko) * 2003-04-29 2005-07-20 주식회사 하이닉스반도체 온 다이 터미네이션 모드 전환 회로 및 그방법
KR100529033B1 (ko) * 2003-05-23 2005-11-17 주식회사 하이닉스반도체 동기식 반도체 메모리 소자
KR100528164B1 (ko) * 2004-02-13 2005-11-15 주식회사 하이닉스반도체 반도체 기억 소자에서의 온 다이 터미네이션 모드 전환회로 및 그 방법
JP4298610B2 (ja) * 2004-08-31 2009-07-22 キヤノン株式会社 データ記憶装置
US7164611B2 (en) * 2004-10-26 2007-01-16 Micron Technology, Inc. Data retention kill function
JP4775141B2 (ja) * 2005-09-29 2011-09-21 株式会社ハイニックスセミコンダクター 遅延固定ループ回路
DE102006036822A1 (de) * 2006-08-07 2008-02-14 Qimonda Ag Verfahren zum Betrieb eines Speichermoduls und Speichermodul
KR100866601B1 (ko) * 2006-12-04 2008-11-03 삼성전자주식회사 반도체 장치의 종단 저항을 제어할 수 있는 장치 및 방법
JP2008217890A (ja) * 2007-03-02 2008-09-18 Ricoh Co Ltd 電子装置、画像処理装置及び電源供給制御方法
US7729191B2 (en) * 2007-09-06 2010-06-01 Micron Technology, Inc. Memory device command decoding system and memory device and processor-based system using same
JP5200692B2 (ja) * 2007-09-14 2013-06-05 株式会社リコー データ処理装置、データ処理装置の電圧制御方法及び画像形成装置
US7715264B2 (en) * 2008-06-24 2010-05-11 Qimonda North America Corp. Method and apparatus for selectively disabling termination circuitry

Also Published As

Publication number Publication date
US7869300B2 (en) 2011-01-11
TWI527030B (zh) 2016-03-21
JP2010262645A (ja) 2010-11-18
CN101882464A (zh) 2010-11-10
EP2246769A1 (en) 2010-11-03
CN101882464B (zh) 2013-10-30
KR20100118950A (ko) 2010-11-08
TW201044391A (en) 2010-12-16
US20100278000A1 (en) 2010-11-04

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