JP2010262645A5 - - Google Patents

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Publication number
JP2010262645A5
JP2010262645A5 JP2010100474A JP2010100474A JP2010262645A5 JP 2010262645 A5 JP2010262645 A5 JP 2010262645A5 JP 2010100474 A JP2010100474 A JP 2010100474A JP 2010100474 A JP2010100474 A JP 2010100474A JP 2010262645 A5 JP2010262645 A5 JP 2010262645A5
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JP
Japan
Prior art keywords
cke
power module
memory controller
memory device
applies
Prior art date
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Granted
Application number
JP2010100474A
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English (en)
Japanese (ja)
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JP2010262645A (ja
JP5590605B2 (ja
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Publication date
Priority claimed from US12/431,876 external-priority patent/US7869300B2/en
Application filed filed Critical
Publication of JP2010262645A publication Critical patent/JP2010262645A/ja
Publication of JP2010262645A5 publication Critical patent/JP2010262645A5/ja
Application granted granted Critical
Publication of JP5590605B2 publication Critical patent/JP5590605B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2010100474A 2009-04-29 2010-04-26 セルフリフレッシュ・モードのためのメモリ・デバイス制御 Expired - Fee Related JP5590605B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/431,876 2009-04-29
US12/431,876 US7869300B2 (en) 2009-04-29 2009-04-29 Memory device control for self-refresh mode

Publications (3)

Publication Number Publication Date
JP2010262645A JP2010262645A (ja) 2010-11-18
JP2010262645A5 true JP2010262645A5 (enExample) 2013-05-23
JP5590605B2 JP5590605B2 (ja) 2014-09-17

Family

ID=42226108

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010100474A Expired - Fee Related JP5590605B2 (ja) 2009-04-29 2010-04-26 セルフリフレッシュ・モードのためのメモリ・デバイス制御

Country Status (6)

Country Link
US (1) US7869300B2 (enExample)
EP (1) EP2246769A1 (enExample)
JP (1) JP5590605B2 (enExample)
KR (1) KR20100118950A (enExample)
CN (1) CN101882464B (enExample)
TW (1) TWI527030B (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8942056B2 (en) 2011-02-23 2015-01-27 Rambus Inc. Protocol for memory power-mode control
US9159397B2 (en) 2012-12-04 2015-10-13 Micron Technology, Inc. Methods and apparatuses for refreshing memory
JP2014146115A (ja) * 2013-01-28 2014-08-14 Canon Inc データ処理装置およびその制御方法
US10055370B2 (en) * 2014-07-09 2018-08-21 Advanced Micro Devices, Inc. Method and apparatis for processor standby
US9142280B1 (en) 2014-08-06 2015-09-22 Freescale Semiconducotr, Inc. Circuit for configuring external memory
CA3034395A1 (en) * 2015-08-24 2017-03-02 Src Labs, Llc System and method for retaining dram data when reprogramming reconfigurable devices with dram memory controllers incorporating a data maintenance block colocated with a memory module or subsystem
JP6516630B2 (ja) 2015-08-26 2019-05-22 キヤノン株式会社 メモリ制御回路及びその制御方法
KR102535182B1 (ko) 2016-07-27 2023-05-23 에스케이하이닉스 주식회사 반도체 장치
US11176986B2 (en) * 2019-12-30 2021-11-16 Advanced Micro Devices, Inc. Memory context restore, reduction of boot time of a system on a chip by reducing double data rate memory training

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5831467A (en) * 1991-11-05 1998-11-03 Monolithic System Technology, Inc. Termination circuit with power-down mode for use in circuit module architecture
US6564329B1 (en) * 1999-03-16 2003-05-13 Linkup Systems Corporation System and method for dynamic clock generation
US6829677B1 (en) * 2000-05-18 2004-12-07 International Business Machines Corporation Method and apparatus for preserving the contents of synchronous DRAM through system reset
TW588235B (en) 2001-04-02 2004-05-21 Via Tech Inc Motherboard with less power consumption
JP3799251B2 (ja) * 2001-08-24 2006-07-19 エルピーダメモリ株式会社 メモリデバイス及びメモリシステム
KR100502664B1 (ko) * 2003-04-29 2005-07-20 주식회사 하이닉스반도체 온 다이 터미네이션 모드 전환 회로 및 그방법
KR100529033B1 (ko) * 2003-05-23 2005-11-17 주식회사 하이닉스반도체 동기식 반도체 메모리 소자
KR100528164B1 (ko) * 2004-02-13 2005-11-15 주식회사 하이닉스반도체 반도체 기억 소자에서의 온 다이 터미네이션 모드 전환회로 및 그 방법
JP4298610B2 (ja) * 2004-08-31 2009-07-22 キヤノン株式会社 データ記憶装置
US7164611B2 (en) * 2004-10-26 2007-01-16 Micron Technology, Inc. Data retention kill function
JP4775141B2 (ja) * 2005-09-29 2011-09-21 株式会社ハイニックスセミコンダクター 遅延固定ループ回路
DE102006036822A1 (de) * 2006-08-07 2008-02-14 Qimonda Ag Verfahren zum Betrieb eines Speichermoduls und Speichermodul
KR100866601B1 (ko) * 2006-12-04 2008-11-03 삼성전자주식회사 반도체 장치의 종단 저항을 제어할 수 있는 장치 및 방법
JP2008217890A (ja) * 2007-03-02 2008-09-18 Ricoh Co Ltd 電子装置、画像処理装置及び電源供給制御方法
US7729191B2 (en) * 2007-09-06 2010-06-01 Micron Technology, Inc. Memory device command decoding system and memory device and processor-based system using same
JP5200692B2 (ja) * 2007-09-14 2013-06-05 株式会社リコー データ処理装置、データ処理装置の電圧制御方法及び画像形成装置
US7715264B2 (en) * 2008-06-24 2010-05-11 Qimonda North America Corp. Method and apparatus for selectively disabling termination circuitry

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