JP5539618B2 - 超高真空管のための半導体取り付け - Google Patents
超高真空管のための半導体取り付け Download PDFInfo
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- JP5539618B2 JP5539618B2 JP2007513190A JP2007513190A JP5539618B2 JP 5539618 B2 JP5539618 B2 JP 5539618B2 JP 2007513190 A JP2007513190 A JP 2007513190A JP 2007513190 A JP2007513190 A JP 2007513190A JP 5539618 B2 JP5539618 B2 JP 5539618B2
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Description
SiOxNy−3000オングストローム(この層の厚さおよびx/y比は重要ではない。)
クロム−2000オングストローム
金−500オングストローム
SiOxNy−3000オングストローム(この層の厚さおよびx/y比は重要ではない。)
チタニウム−200オングストローム
プラチナ−5000オングストローム
金−500オングストローム
Claims (27)
- 超高真空(UHV)管の製造の際に半導体ダイを異なる材料のパッケージの内面に結合する方法であって、
複数の結合パッドをダイの表面に形成する工程と、
複数の整合結合パッドをパッケージの前記内面に形成する工程と、
前記結合パッドと前記整合結合パッドとのそれぞれの間に、200℃以下の融点をもつろう付け材を設ける工程と、
前記結合パッドと前記整合結合パッドの表面を互いに位置合わせする工程と、
前記ダイを前記パッケージに結合するためのろう付けサイクルを通して、そして次の前記ろう付け材を再溶融させ、前記パッケージ内の圧力を10-7Pa以下にする超高真空処理サイクルを通して、互いに位置合わせされた前記表面を維持する工程と、
を含む方法。 - 超高真空(UHV)管の製造の際に半導体ダイを異なる材料のパッケージの内面に結合する方法であって、
複数の結合パッドをダイの表面に形成する工程と、
複数の整合結合パッドをパッケージの前記内面に形成する工程と、
前記結合パッドと前記整合結合パッドとのそれぞれの組み合わせのうちの一方の組み合わせの間に、200℃を超える超高真空処理の間、溶解しないろう付け材を設ける工程と、
前記結合パッドと前記整合結合パッドとのそれぞれの組み合わせのうちの他方の組み合わせの間に、200℃以下の融点をもつろう付け材を設ける工程と、
前記結合パッドと前記整合結合パッドの表面を互いに位置合わせする工程と、
前記ダイを前記パッケージに結合するためのろう付けサイクルを通して、そして次の前記パッケージ内の圧力を10-7Pa以下にする超高真空処理サイクルを通して、互いに位置合わせされた前記表面を維持する工程と、
を含む方法。 - イメージング素子としての超高真空(UHV)管であって、
半導体ダイと、
当該真空管のためのセラミック製ハウジングと、
を有し、
前記ダイは、前記セラミック製ハウジング内の結合パッドにより、前記ダイ内の対応する結合パッドにより、そしてパッドのそれぞれの組み合わせのものの間にある、ハウジング内を超高真空とする真空処理の間、再溶融する200℃以下の融点をもつろう付け材により、前記セラミック製ハウジングに電気的に接続する複数の接続子を有し、前記対応する結合パッドは、前記ハウジングにあるピンのそれぞれに結びつけられ、前記ハウジング内は10-7Pa以下の超高真空である、
ことを特徴とする超高真空管。 - 前記ハウジング内の超高真空中に光電陰極を有する、請求項3に記載の超高真空管。
- 前記半導体ダイが電荷結合素子からなり、前記電荷結合素子が近接イメージングのために、前記光電陰極と整合する、ことを特徴とする請求項4に記載の超高真空管。
- 前記半導体ダイがCMOS素子からなり、該CMOS素子は近接イメージングのために、前記光電陰極と整合する、ことを特徴とする請求項4に記載の超高真空管。
- 前記半導体ダイが、支持基板に結合された背面薄化シリコンイメージングセンサーからなり、該センサーは近接イメージングのために、前記光電陰極と整合する、ことを特徴とする請求項4に記載の超高真空管。
- 前記パッドがSiOxNy、クロムおよび金からなる、請求項4に記載の超高真空管。
- 前記パッドがSiOxNy、チタニウム、プラチナおよび金からなる、請求項4に記載の超高真空管。
- 前記ろう付け材が、低融点の金属または合金からなる、請求項3に記載の超高真空管。
- 前記CMOS素子が、当該超高真空管内で前記光電陰極が電子衝撃を受けるように、前記超高真空管内で前記光電陰極と整合するAPS素子からなる、請求項8に記載の超高真空管。
- 前記ろう付け材が低融点の金属または合金からなる、請求項9に記載の超高真空管。
- 前記ろう付け材がインジウムからなる、請求項6または12に記載の超高真空管。
- イメージング素子としての超高真空(UHV)管であって、
半導体ダイと、
当該真空管のための異なる材料のハウジングと、
を有し、
前記ダイは、前記ハウジング内の結合パッドにより、前記ダイ内にある電気的に絶縁された結合パッドにより、そして前記結合パッドの間にあり、200℃以下の融点をもつろう付け材により、前記セラミック製ハウジングに電気的に接続され、前記ハウジング内は10-7Pa以下の超高真空であり、前記ハウジングはさらに前記ハウジングにあるピンのそれぞれに結びつけられる対応する相互接続パッドを有する、
ことを特徴とする超高真空管。 - 前記ろう付け材がインジウムからなる、請求項3または14に記載の超高真空管。
- 前記ハウジング内の前記結合パッドが互いに電気的に接続される、請求項3または14に記載の超高真空管。
- 前記真空内に前記半導体ダイと位置合わせされるMCPを有し、
該MCPへの入力イメージに対応して前記半導体ダイの入力部にイメージが形成される、請求項3または14に記載の超高真空管。 - イメージセンサーを製造する方法であって、
セラミック製パッケージの内面に半導体ダイを結合する工程と、
前記パッケージ内で前記半導体ダイに隣接して光電陰極を配置する工程と、
シリコン製ダイの表面に電気的に絶縁された複数の結合パッドを形成する工程と、
前記セラミック材からなるパッケージの前記内面に複数の整合係合パッドを形成する工程と、
前記結合パッドと前記整合結合パッドとのそれぞれの組み合わせのものの間にろう付け材を設ける工程と、
前記結合パッドと前記整合結合パッドの表面を互いに位置合わせする工程と、
前記ダイを前記セラミック製パッケージに結合するためのろう付けサイクルを通して、そして次の前記ろう付け材を再溶融させ、前記パッケージ内の圧力を10-7Pa以下にする超高真空処理サイクルを通して、互いに位置合わせされた前記表面を維持する工程と、
を含む方法。 - インジウムが前記ろう付け材として使用される、請求項18に記載の方法。
- 近接焦点化イメージが前記半導体ダイの入力部で形成されるように、前記光電陰極と前記半導体ダイとが配置される、請求項18に記載の方法。
- 超高真空(UHV)管の製造の際に半導体ダイをパッケージの内面に結合する方法であって、
ダイの表面に複数の結合パッドおよび複数の相互接続パッドを形成する工程と、
パッケージの前記内面に複数の整合結合パッドおよび複数の整合相互接続パッドを形成する工程と、
前記結合パッドと前記相互接続パッドとのそれぞれの間に、200℃以下の融点をもつろう付け材を設ける工程と、
前記結合パッドと前記整合結合パッドの表面を互いに位置合わせする工程と、
前記ダイを前記パッケージに結合させるためのろう付けサイクルを通して、そして次の前記ろう付け材を再溶融させ、前記パッケージ内の圧力を10-7Pa以下にする超高真空処理サイクルを通して、互いに位置合わせされた前記表面を維持する工程と、
を含む方法。 - 超高真空(UHV)管の製造の際に半導体ダイを異なる材料のパッケージの内面に結合する方法であって、
ダイの表面に複数の結合パッドを形成する工程と、
パッケージの前記内面に複数の整合結合パッドを形成する工程と、
前記結合パッドと前記整合結合パッドとのそれぞれの間に、200℃以下の融点をもつろう付け材を設ける工程と、
前記結合パッドと前記整合結合パッドの表面を互いに位置合わせする工程と、
前記ダイを前記パッケージに結合するためのろう付けサイクルを通して、そして次の前記ろう付け材を再溶融させ、前記パッケージ内の圧力を10−7Pa以下にする超高真空処理サイクルを通して、互いに位置合わせされた前記表面を維持する工程と、
を含み、位置合わせを維持する力がろう付け材の表面張力により形成される方法。 - イメージング素子としての超高真空(UHV)管であって、
半導体ダイと、
当該真空管のためのハウジングと、
を有し、
前記ダイは、前記ハウジング内のパッドにより、前記ダイ内のパッドにより、そしてパッドのそれぞれの組み合わせのものの間にある、前記ハウジング内を超高真空とする真空処理の間、再溶融する200℃以下の融点をもつろう付け材により、前記ハウジングに接続する複数の接続子を有し、前記ハウジング内は10−7Pa以下の超高真空であり、前記半導体ダイと前記ダイと向かい合う前記ハウジングとの間の間隙は、前記半導体ダイを前記ハウジングに結合するために使用される前記ろう付けの直径の一倍よりも大きくない、ことを特徴とする超高真空管。 - 前記真空内で前記半導体ダイと位置合わせされるMCPおよび光電陰極を有し、
光電陰極により形成される電位イメージから形成される、前記MCPへの入力イメージに対応して前記半導体ダイの入力部にイメージが形成される、請求項3に記載の超高真空管。 - 前記半導体ダイが基板に支持される背面薄化されたCMOS素子からなる、請求項24に記載の超高真空管。
- 前記半導体ダイが基板に支持される背面薄化された電荷結合素子からなる、請求項24に記載の超高真空管。
- 前記半導体ダイがROICからなる、請求項24に記載の超高真空管。
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US10/846,060 US7012328B2 (en) | 2004-05-14 | 2004-05-14 | Semiconductor die attachment for high vacuum tubes |
US10/846,060 | 2004-05-14 | ||
PCT/US2005/015086 WO2005114727A2 (en) | 2004-05-14 | 2005-05-02 | Semiconductor die attachment for high vaccum tubes |
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2005
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- 2005-05-02 JP JP2007513190A patent/JP5539618B2/ja not_active Expired - Fee Related
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US20060113655A1 (en) | 2006-06-01 |
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US7608533B2 (en) | 2009-10-27 |
WO2005114727A2 (en) | 2005-12-01 |
US7012328B2 (en) | 2006-03-14 |
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