JP5528906B2 - 表示装置 - Google Patents
表示装置 Download PDFInfo
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- JP5528906B2 JP5528906B2 JP2010123023A JP2010123023A JP5528906B2 JP 5528906 B2 JP5528906 B2 JP 5528906B2 JP 2010123023 A JP2010123023 A JP 2010123023A JP 2010123023 A JP2010123023 A JP 2010123023A JP 5528906 B2 JP5528906 B2 JP 5528906B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- terminal
- film transistor
- thin film
- wiring portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000000758 substrate Substances 0.000 claims description 119
- 239000010409 thin film Substances 0.000 claims description 63
- 239000004065 semiconductor Substances 0.000 claims description 25
- 238000013459 approach Methods 0.000 claims description 2
- 102100036464 Activated RNA polymerase II transcriptional coactivator p15 Human genes 0.000 description 31
- 101000713904 Homo sapiens Activated RNA polymerase II transcriptional coactivator p15 Proteins 0.000 description 31
- 229910004444 SUB1 Inorganic materials 0.000 description 31
- 239000004973 liquid crystal related substance Substances 0.000 description 22
- 239000013256 coordination polymer Substances 0.000 description 13
- 239000010408 film Substances 0.000 description 13
- 238000010586 diagram Methods 0.000 description 6
- 230000005684 electric field Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 229910004438 SUB2 Inorganic materials 0.000 description 5
- 101100311330 Schizosaccharomyces pombe (strain 972 / ATCC 24843) uap56 gene Proteins 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 101150018444 sub2 gene Proteins 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000003566 sealing material Substances 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4092—Integral conductive tabs, i.e. conductive parts partly detached from the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10128—Display
- H05K2201/10136—Liquid Crystal display [LCD]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/361—Assembling flexible printed circuits with other printed circuits
- H05K3/363—Assembling flexible printed circuits with other printed circuits by soldering
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Nonlinear Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Manufacturing & Machinery (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
- Wire Bonding (AREA)
Description
図1は、本実施形態に係る表示装置の概略平面図である。本実施形態における表示装置は、液晶表示装置であって、液晶表示パネルPNLは、液晶(図示せず)を介在させて対向配置される薄膜トランジスタ基板SUB1および対向基板SUB2を含んで構成されている。
Claims (4)
- 複数の端子を含む端子部を薄膜トランジスタ基板上に備えた表示パネルと、
前記端子部に接続される駆動回路と、を有する表示装置であって、
前記駆動回路は、
フレキシブル基板と、当該フレキシブル基板に搭載される半導体チップと、を有し、
前記フレキシブル基板は、前記半導体チップ及び前記複数の端子の間をそれぞれ接続する複数の配線を備え、
前記配線は、
前記端子に重なる第1配線部分と、
前記第1配線部分と前記半導体チップとの間に位置する第2配線部分と、を有し、
前記第1配線部分は、前記第2配線部分よりも細く、
前記薄膜トランジスタ基板上における前記端子は、前記薄膜トランジスタ基板の端部から離れて内側に配置され、
前記第1配線部分は、前記薄膜トランジスタ基板の前記端部と前記端子との間の領域まで延在し、前記第2配線部分は、前記端子との重複を避けつつ、当該領域の一部および前記端部と重複する、
ことを特徴とする表示装置。 - 複数の端子を含む端子部を薄膜トランジスタ基板上に備えた表示パネルと、
前記端子部に接続される駆動回路と、を有する表示装置であって、
前記駆動回路は、
フレキシブル基板と、当該フレキシブル基板に搭載される半導体チップと、を有し、
前記フレキシブル基板は、前記半導体チップ及び前記複数の端子の間をそれぞれ接続する複数の配線を備え、
前記複数の端子は、前記薄膜トランジスタ基板の端部から離れて内側に配置され、
前記フレキシブル基板の一部は、前記端子部を含む前記薄膜トランジスタ基板の一部と
重なり、
前記配線は、
前記端子に重なる第1配線部分と、
前記第1配線部分と前記半導体チップとの間に位置する第2配線部分と、
前記第1配線部分と前記第2配線部分の間に位置する第3配線部分と、を有し、
前記第1配線部分は、前記第2配線部分よりも細く、
前記第3配線部分は、前記薄膜トランジスタ基板の前記端部と前記端子との間の領域と
重なるとともに、前記第2配線部分に近づくにつれて徐々に線幅が太くなる、
ことを特徴とする表示装置。 - 請求項1又は2に記載された表示装置であって、
前記複数の端子は、所定のピッチで配置されて、
前記配線は、断面が矩形状に形成されて、
前記第1配線部分は、前記ピッチの0.3倍以上であって0.4倍以下の線幅となる、
ことを特徴とする表示装置。 - 請求項1又は2に記載された表示装置であって、
前記複数の端子は、前記薄膜トランジスタ基板の端部に沿って所定のピッチで配置されて、
前記複数の配線のそれぞれは、前記薄膜トランジスタ基板の前記端部とほぼ垂直に交差して、前記複数の端子のそれぞれと重なる、
ことを特徴とする表示装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010123023A JP5528906B2 (ja) | 2010-05-28 | 2010-05-28 | 表示装置 |
US13/115,131 US8902394B2 (en) | 2010-05-28 | 2011-05-25 | Display device comprising a flexible board including a first wiring portion that is narrower than a second wiring portion and wherein the second wiring portion does not overlap a terminal portion |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010123023A JP5528906B2 (ja) | 2010-05-28 | 2010-05-28 | 表示装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011248222A JP2011248222A (ja) | 2011-12-08 |
JP5528906B2 true JP5528906B2 (ja) | 2014-06-25 |
Family
ID=45021839
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010123023A Active JP5528906B2 (ja) | 2010-05-28 | 2010-05-28 | 表示装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8902394B2 (ja) |
JP (1) | JP5528906B2 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6732562B2 (ja) | 2016-06-24 | 2020-07-29 | 株式会社ジャパンディスプレイ | 表示装置 |
JP2018049193A (ja) * | 2016-09-23 | 2018-03-29 | 株式会社ジャパンディスプレイ | 表示装置 |
KR102578051B1 (ko) | 2018-06-01 | 2023-09-14 | 삼성전자주식회사 | 필름형 패키지 및 이를 구비한 디스플레이 장치 |
CN115866879A (zh) | 2019-09-10 | 2023-03-28 | 群创光电股份有限公司 | 电子装置 |
KR20210060718A (ko) * | 2019-11-18 | 2021-05-27 | 삼성디스플레이 주식회사 | 표시 장치 및 표시 장치의 제조 방법 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000259091A (ja) * | 1999-03-04 | 2000-09-22 | Casio Comput Co Ltd | 表示パネル、フレキシブル配線基板及びそれらを備えた表示装置 |
KR100324283B1 (ko) * | 2000-02-23 | 2002-02-21 | 구본준, 론 위라하디락사 | 테이프 캐리어 패키지 및 그 제조방법 |
JP3708467B2 (ja) * | 2001-09-26 | 2005-10-19 | 株式会社日立製作所 | 表示装置 |
JP2002236458A (ja) * | 2001-11-20 | 2002-08-23 | Sharp Corp | 表示装置の実装構造 |
JP3985634B2 (ja) * | 2002-08-28 | 2007-10-03 | セイコーエプソン株式会社 | 電子部品の実装基板、電気光学装置、電気光学装置の製造方法及び電子機器 |
JP2004212506A (ja) * | 2002-12-27 | 2004-07-29 | Optrex Corp | 液晶表示素子 |
JP4443324B2 (ja) * | 2004-06-28 | 2010-03-31 | 東北パイオニア株式会社 | フレキシブル配線基板及びその製造方法、半導体チップ実装フレキシブル配線基板、電子機器 |
KR100737590B1 (ko) * | 2005-05-30 | 2007-07-10 | 엘지전자 주식회사 | 테이프 캐리어 패키지용 탭 테이프 |
JP3802044B2 (ja) * | 2005-08-01 | 2006-07-26 | 株式会社 日立ディスプレイズ | 液晶表示装置 |
JP5260912B2 (ja) | 2007-07-31 | 2013-08-14 | パナソニック液晶ディスプレイ株式会社 | 表示装置 |
TWI376020B (en) * | 2007-12-12 | 2012-11-01 | Au Optronics Corp | Chip on film structure |
US8446556B2 (en) * | 2008-07-08 | 2013-05-21 | Sharp Kabushiki Kaisha | Flexible printed circuit and electric circuit structure |
-
2010
- 2010-05-28 JP JP2010123023A patent/JP5528906B2/ja active Active
-
2011
- 2011-05-25 US US13/115,131 patent/US8902394B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20110292313A1 (en) | 2011-12-01 |
JP2011248222A (ja) | 2011-12-08 |
US8902394B2 (en) | 2014-12-02 |
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