JP5507063B2 - 半導体装置の作製方法 - Google Patents

半導体装置の作製方法 Download PDF

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Publication number
JP5507063B2
JP5507063B2 JP2008175550A JP2008175550A JP5507063B2 JP 5507063 B2 JP5507063 B2 JP 5507063B2 JP 2008175550 A JP2008175550 A JP 2008175550A JP 2008175550 A JP2008175550 A JP 2008175550A JP 5507063 B2 JP5507063 B2 JP 5507063B2
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Japan
Prior art keywords
substrate
semiconductor
bond
semiconductor film
bond substrate
Prior art date
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Expired - Fee Related
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JP2008175550A
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English (en)
Japanese (ja)
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JP2009038358A (ja
JP2009038358A5 (https=
Inventor
明久 下村
達也 溝井
秀和 宮入
幸一郎 田中
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Publication date
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Priority to JP2008175550A priority Critical patent/JP5507063B2/ja
Publication of JP2009038358A publication Critical patent/JP2009038358A/ja
Publication of JP2009038358A5 publication Critical patent/JP2009038358A5/ja
Application granted granted Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1902—Preparing horizontally inhomogeneous wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2101/00—Properties of the organic materials covered by group H10K85/00
    • H10K2101/50—Oxidation-reduction potentials, e.g. excited state redox potentials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers

Landscapes

  • Thin Film Transistor (AREA)
JP2008175550A 2007-07-09 2008-07-04 半導体装置の作製方法 Expired - Fee Related JP5507063B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008175550A JP5507063B2 (ja) 2007-07-09 2008-07-04 半導体装置の作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007179241 2007-07-09
JP2007179241 2007-07-09
JP2008175550A JP5507063B2 (ja) 2007-07-09 2008-07-04 半導体装置の作製方法

Publications (3)

Publication Number Publication Date
JP2009038358A JP2009038358A (ja) 2009-02-19
JP2009038358A5 JP2009038358A5 (https=) 2011-07-21
JP5507063B2 true JP5507063B2 (ja) 2014-05-28

Family

ID=40253498

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008175550A Expired - Fee Related JP5507063B2 (ja) 2007-07-09 2008-07-04 半導体装置の作製方法

Country Status (2)

Country Link
US (3) US7745310B2 (https=)
JP (1) JP5507063B2 (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2174343A1 (en) * 2007-06-28 2010-04-14 Semiconductor Energy Laboratory Co, Ltd. Manufacturing method of semiconductor device
US8431451B2 (en) 2007-06-29 2013-04-30 Semicondutor Energy Laboratory Co., Ltd. Display device and method for manufacturing the same
US8236668B2 (en) 2007-10-10 2012-08-07 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
TWI493609B (zh) * 2007-10-23 2015-07-21 半導體能源研究所股份有限公司 半導體基板、顯示面板及顯示裝置的製造方法
GB0914251D0 (en) * 2009-08-14 2009-09-30 Nat Univ Ireland Cork A hybrid substrate
EP2520202B1 (fr) * 2011-05-02 2014-07-23 Mocoffee AG Dispositif et capsule pour la préparation d'une boisson
KR101968637B1 (ko) * 2012-12-07 2019-04-12 삼성전자주식회사 유연성 반도체소자 및 그 제조방법
CN105874571B (zh) * 2013-12-18 2019-12-17 英特尔公司 局部层转移的系统和方法
JP7242220B2 (ja) * 2018-09-03 2023-03-20 キヤノン株式会社 接合ウェハ及びその製造方法、並びにスルーホール形成方法
GB2591096B (en) 2020-01-14 2024-09-04 Dawsongroup Plc An inflatable structure and method of transporting an inflatable structure
FR3131978B1 (fr) * 2022-01-17 2023-12-08 Soitec Silicon On Insulator Procede de fabrication d’une structure comprenant au moins deux paves sur un substrat

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09252100A (ja) 1996-03-18 1997-09-22 Shin Etsu Handotai Co Ltd 結合ウェーハの製造方法及びこの方法により製造される結合ウェーハ
JPH1145862A (ja) * 1997-07-24 1999-02-16 Denso Corp 半導体基板の製造方法
JP2000012864A (ja) 1998-06-22 2000-01-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
AU4510801A (en) * 1999-12-02 2001-06-18 Teraconnect, Inc. Method of making optoelectronic devices using sacrificial devices
FR2842651B1 (fr) 2002-07-17 2005-07-08 Procede de lissage du contour d'une couche utile de materiau reportee sur un substrat support
US6818529B2 (en) 2002-09-12 2004-11-16 Applied Materials, Inc. Apparatus and method for forming a silicon film across the surface of a glass substrate
US7176528B2 (en) * 2003-02-18 2007-02-13 Corning Incorporated Glass-based SOI structures
US6767802B1 (en) 2003-09-19 2004-07-27 Sharp Laboratories Of America, Inc. Methods of making relaxed silicon-germanium on insulator via layer transfer
FR2860842B1 (fr) * 2003-10-14 2007-11-02 Tracit Technologies Procede de preparation et d'assemblage de substrats
US20100112780A1 (en) 2005-07-12 2010-05-06 The Arizona Board Of Regents, A Body Corporate Acting On Behalf Of Arizona State University Microwave-Induced Ion Cleaving and Patternless Transfer of Semiconductor Films
US7674687B2 (en) 2005-07-27 2010-03-09 Silicon Genesis Corporation Method and structure for fabricating multiple tiled regions onto a plate using a controlled cleaving process
US7288458B2 (en) 2005-12-14 2007-10-30 Freescale Semiconductor, Inc. SOI active layer with different surface orientation
KR101443580B1 (ko) 2007-05-11 2014-10-30 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Soi구조를 갖는 기판
WO2008156040A1 (en) * 2007-06-20 2008-12-24 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
US7795111B2 (en) * 2007-06-27 2010-09-14 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate and manufacturing method of semiconductor device
EP2174343A1 (en) * 2007-06-28 2010-04-14 Semiconductor Energy Laboratory Co, Ltd. Manufacturing method of semiconductor device

Also Published As

Publication number Publication date
US20110300690A1 (en) 2011-12-08
JP2009038358A (ja) 2009-02-19
US20090017598A1 (en) 2009-01-15
US20100267216A1 (en) 2010-10-21
US7989316B2 (en) 2011-08-02
US7745310B2 (en) 2010-06-29
US8349705B2 (en) 2013-01-08

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