JP5494455B2 - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
- Publication number
- JP5494455B2 JP5494455B2 JP2010274447A JP2010274447A JP5494455B2 JP 5494455 B2 JP5494455 B2 JP 5494455B2 JP 2010274447 A JP2010274447 A JP 2010274447A JP 2010274447 A JP2010274447 A JP 2010274447A JP 5494455 B2 JP5494455 B2 JP 5494455B2
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- semiconductor memory
- memory device
- array
- redundant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/702—Masking faults in memories by using spares or by reconfiguring by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010274447A JP5494455B2 (ja) | 2010-12-09 | 2010-12-09 | 半導体記憶装置 |
| US13/279,425 US8675430B2 (en) | 2010-12-09 | 2011-10-24 | Semiconductor storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010274447A JP5494455B2 (ja) | 2010-12-09 | 2010-12-09 | 半導体記憶装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2012123876A JP2012123876A (ja) | 2012-06-28 |
| JP2012123876A5 JP2012123876A5 (https=) | 2013-10-17 |
| JP5494455B2 true JP5494455B2 (ja) | 2014-05-14 |
Family
ID=46199264
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2010274447A Expired - Fee Related JP5494455B2 (ja) | 2010-12-09 | 2010-12-09 | 半導体記憶装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US8675430B2 (https=) |
| JP (1) | JP5494455B2 (https=) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2020166346A (ja) * | 2019-03-28 | 2020-10-08 | ラピスセミコンダクタ株式会社 | 半導体記憶装置 |
| KR20230091244A (ko) | 2021-12-15 | 2023-06-23 | 삼성전자주식회사 | 반도체 장치 |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0676595A (ja) * | 1992-08-26 | 1994-03-18 | Hitachi Ltd | 半導体メモリ |
| KR0172333B1 (ko) * | 1995-01-16 | 1999-03-30 | 김광호 | 반도체 메모리 장치의 전원 승압 회로 |
| JP2953345B2 (ja) * | 1995-06-08 | 1999-09-27 | 日本電気株式会社 | 半導体記憶装置 |
| JP3036411B2 (ja) * | 1995-10-18 | 2000-04-24 | 日本電気株式会社 | 半導体記憶集積回路装置 |
| JP2000067595A (ja) * | 1998-06-09 | 2000-03-03 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JP4427847B2 (ja) | 1999-11-04 | 2010-03-10 | エルピーダメモリ株式会社 | ダイナミック型ramと半導体装置 |
| JP3863410B2 (ja) * | 2001-11-12 | 2006-12-27 | 富士通株式会社 | 半導体メモリ |
| JP3983048B2 (ja) * | 2001-12-18 | 2007-09-26 | シャープ株式会社 | 半導体記憶装置および情報機器 |
| JP2004342260A (ja) | 2003-05-16 | 2004-12-02 | Hitachi Ltd | 半導体記憶装置 |
| JP2006252708A (ja) * | 2005-03-11 | 2006-09-21 | Elpida Memory Inc | 半導体記憶装置における電圧発生方法及び半導体記憶装置 |
| JP5449670B2 (ja) * | 2007-12-25 | 2014-03-19 | ピーエスフォー ルクスコ エスエイアールエル | 半導体記憶装置、および冗長領域のリフレッシュ方法 |
| JP4949451B2 (ja) | 2009-10-29 | 2012-06-06 | エルピーダメモリ株式会社 | ダイナミック型ramと半導体装置 |
-
2010
- 2010-12-09 JP JP2010274447A patent/JP5494455B2/ja not_active Expired - Fee Related
-
2011
- 2011-10-24 US US13/279,425 patent/US8675430B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2012123876A (ja) | 2012-06-28 |
| US8675430B2 (en) | 2014-03-18 |
| US20120147685A1 (en) | 2012-06-14 |
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