JP5489132B2 - 薄型基板による電子素子のパッケージ方法 - Google Patents
薄型基板による電子素子のパッケージ方法 Download PDFInfo
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- JP5489132B2 JP5489132B2 JP2012283103A JP2012283103A JP5489132B2 JP 5489132 B2 JP5489132 B2 JP 5489132B2 JP 2012283103 A JP2012283103 A JP 2012283103A JP 2012283103 A JP2012283103 A JP 2012283103A JP 5489132 B2 JP5489132 B2 JP 5489132B2
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- 239000000758 substrate Substances 0.000 title claims description 245
- 238000000034 method Methods 0.000 title claims description 107
- 238000004806 packaging method and process Methods 0.000 title claims description 55
- 238000000465 moulding Methods 0.000 claims description 54
- 239000002184 metal Substances 0.000 claims description 51
- 229910052751 metal Inorganic materials 0.000 claims description 51
- 229910000679 solder Inorganic materials 0.000 claims description 46
- 239000003795 chemical substances by application Substances 0.000 claims description 17
- 238000005476 soldering Methods 0.000 claims description 17
- 230000002950 deficient Effects 0.000 claims description 16
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 16
- 239000010931 gold Substances 0.000 claims description 16
- 229910052737 gold Inorganic materials 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 238000001721 transfer moulding Methods 0.000 claims description 11
- 238000007639 printing Methods 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 107
- 238000012360 testing method Methods 0.000 description 51
- 238000012858 packaging process Methods 0.000 description 18
- 238000005304 joining Methods 0.000 description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 15
- 229910052802 copper Inorganic materials 0.000 description 15
- 239000010949 copper Substances 0.000 description 15
- 239000000523 sample Substances 0.000 description 13
- 239000000463 material Substances 0.000 description 10
- 238000012536 packaging technology Methods 0.000 description 9
- 230000007547 defect Effects 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 239000004642 Polyimide Substances 0.000 description 6
- 230000010354 integration Effects 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 6
- 238000004528 spin coating Methods 0.000 description 5
- 238000010998 test method Methods 0.000 description 5
- 238000013100 final test Methods 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- 238000000748 compression moulding Methods 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
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- 239000004744 fabric Substances 0.000 description 2
- 230000002427 irreversible effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000027455 binding Effects 0.000 description 1
- 238000009739 binding Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011796 hollow space material Substances 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H01L2224/13147—Copper [Cu] as principal constituent
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Automation & Control Theory (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
メモリチップに対してボンディング(bonding)を行う。
全体のウェハーに対してウェハーモールディング(wafer molding)を行う。
ウェハーを除去する。
中間層(Feed-Through Interposer:FTI)により、システムオンチップ(System-On-a-Chip:SoC)またはロジックチップ(Logic Chip)をに対してボンディングを行う。全体のパッケージした製品(パッケージしたメモリチップ及びシステムオンチップやロジックチップ)は、ボールグリッドアレイによって外部のシステム回路基板(PCB)と接続する。
100、200 キャリア
102、106、202、206 金属層
104、204 誘電層
108、210 パッド層
112 パッケージ
114 ボールマウンティング
150 チップ
208 ビア金属
300、301、302 クランプシステム
310 外周部
311、314 下保持板
312、315 上保持板
313 吸引孔
320 クランプ部
330 調整スプリング
340、341 固定ネジ
Claims (16)
- 薄型基板による電子素子のパッケージ方法であって、
キャリアを提供する工程を行い、
その後、前記薄型基板は少なくとも1つのチップと接続するための少なくとも1つのパッケージユニットを含み、前記薄型基板を製造するために、少なくとも1つの金属層及び少なくとも1つの誘電層を前記キャリアに形成する工程を行い、
その後、少なくとも1つのパッド層を前記薄型基板の表面に形成する工程を行い、
その後、前記薄型基板を前記キャリアから分離する工程を行い、
その後、前記薄型基板を検査して、欠陥があるパッケージユニットを取り除き、前記チップと接続するための前記パッケージユニットを選択する工程を行い、
その後、前記チップと接続する前記パッケージユニットを選択するために、モールディングパネルのサイズに応じて前記薄型基板を切り離す工程を行い、
その後、フリップチップボンディングにより、各選択された前記パッケージユニットと前記チップとを接続する工程を行い、
その後、フリップチップで前記モールディングパネルに接合される前記チップ全体を覆うようなモールディングを行って、前記電子素子を構築する工程を行い、
前記薄型基板を検査する工程において、クランプシステムにより前記薄型基板をクランプし、前記薄型基板の上表面及び底面に前記パッド層を露出させる工程を行い、
前記薄型基板をクランプする工程において、前記薄型基板への張力及び前記薄型基板の接触抵抗を所定の数値に制御する工程を行う、
ことを特徴とするパッケージ方法。 - 前記パッケージユニットはフリップチップボンディングにより前記パッド層で前記チップと接続されることを特徴とする請求項1に記載のパッケージ方法。
- 前記モールディングはトランスファー成形であることを特徴とする請求項1に記載のパッケージ方法。
- 前記モールディングを行う工程の後に、複数の半田ボールを前記パッケージユニットと接続してボールグリッドアレイを形成し、前記電子素子を得ることを特徴とする請求項3に記載のパッケージ方法。
- 前記ボールグリッドアレイを形成する工程の後に、前記パッケージユニットのサイズに応じて前記電子素子を切り離す工程をさらに含むことを特徴とする請求項4に記載のパッケージ方法。
- 前記モールディングを行う工程の前に、前記パッケージユニットをフリップチップボンディングにより前記チップと接続する表面に、各前記パッケージユニットをボールグリッドアレイ素子と接続する工程をさらに含むことを特徴とする請求項1に記載のパッケージ方法。
- 各前記パッケージユニットを前記ボールグリッドアレイ素子と接続する工程の前に、前記パッケージユニットにソルダペースト或いは半田付剤を印刷する工程をさらに含むことを特徴とする請求項6に記載のパッケージ方法。
- 前記各選択された前記パッケージユニットをフリップチップボンディングにより前記チップと接続する工程の前に、各前記パッケージユニットをボールグリッドアレイ素子と接続する工程をさらに含むことを特徴とする請求項1に記載のパッケージ方法。
- 各前記パッケージユニットを前記ボールグリッドアレイ素子と接続する工程は、前記パッケージユニットをフリップチップボンディングにより前記チップと接続する表面に実行されることを特徴とする請求項8に記載のパッケージ方法。
- 各選択された前記パッケージユニットをフリップチップボンディングにより前記チップと接続する工程において、各前記パッケージユニットをボールグリッドアレイ素子と接続する工程をさらに含み、前記ボールグリッドアレイ素子と接続する工程は前記パッケージユニットをフリップチップボンディングにより前記チップと接続する表面に実行されることを特徴とする請求項1に記載のパッケージ方法。
- 薄型基板による電子素子のパッケージ方法であって、
キャリアを提供する工程を行い、
その後、前記薄型基板は少なくとも1つのチップと接続するための少なくとも1つのパッケージユニットを含み、前記薄型基板を製造するために、少なくとも1つの金属層及び少なくとも1つの誘電層を前記キャリアに形成する工程を行い、
その後、少なくとも1つのパッド層を前記薄型基板の表面に形成する工程を行い、
その後、前記薄型基板を前記キャリアから分離する工程を行い、
その後、前記薄型基板を検査して、欠陥があるパッケージユニットを取り除き、前記チップと接続するための前記パッケージユニットを選択する工程を行い、
その後、フリップチップボンディングにより、各選択された前記パッケージユニットと前記チップとを接続する工程を行い、
その後、複数の半田ボールを前記パッケージユニットと接続してボールグリッドアレイを形成し、前記電子素子を得る工程を行い、
前記薄型基板を検査する工程において、クランプシステムにより前記薄型基板をクランプし、前記薄型基板の上表面及び底面に前記パッド層を露出させる工程を行い、
前記薄型基板をクランプする工程において、前記薄型基板への張力及び前記薄型基板の接触抵抗を所定の数値に制御する工程を行う、
ことを特徴とするパッケージ方法。 - 前記パッケージユニットはフリップチップボンディングにより前記パッド層で前記チップと接続されることを特徴とする請求項11に記載のパッケージ方法。
- 各選択された前記パッケージユニットを前記チップと接続する工程において、前記フリップチップボンディングは金バンプで実行されることを特徴とする請求項11に記載のパッケージ方法。
- 各選択された前記パッケージユニットをフリップチップボンディングにより前記チップと接続する工程の前に、前記チップと接続する前記パッケージユニットを選択するために、モールディングパネル又は前記パッケージユニットのサイズに応じて前記薄型基板を切り離す工程をさらに含むことを特徴とする請求項11に記載のパッケージ方法。
- 各選択された前記パッケージユニットをフリップチップボンディングにより前記チップと接続する工程の後に、前記チップと接続する前記パッケージユニットを選択するために、モールディングパネル又は前記パッケージユニットのサイズに応じて前記薄型基板を切り離す工程をさらに含むことを特徴とする請求項11に記載のパッケージ方法。
- 複数の半田ボールを前記パッケージユニットと接続する工程の後に、前記チップと接続する前記パッケージユニットを選択するために、モールディングパネル又は前記パッケージユニットのサイズに応じて前記薄型基板を切り離す工程をさらに含むことを特徴とする請求項11に記載のパッケージ方法。
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