JP5475818B2 - Manufacturing method of semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit, a manufacturing method thereof, and a mask used for manufacturing the semiconductor integrated circuit.

  A test pattern for process evaluation of a general semiconductor integrated circuit will be described. FIG. 7 shows an overall view of a general process evaluation test chip layout. In general, the maximum values of the horizontal width d1 and the vertical width d2 of the test chip size are defined by the maximum field size d3 of the lithographic apparatus. In this example, the maximum field size is 25 mm. The evaluation pattern is composed of a collection of evaluation blocks called subchips 404. The size of this sub chip is uniform within the test block. The reason is that in the measurement program, the program can be shared and the measurement needle can be shared by making the arrangement and movement amount of the measurement needle constant.

  A wiring chain process evaluation pattern includes a via chain, an electromigration (EM) evaluation pattern, a leak measurement pattern, and the like. In a via chain, the pattern scale generally changes according to the length of wiring to be evaluated and the number of vias. The defect density can also be evaluated by changing the pattern scale.

  Next, a process for forming a general multilayer wiring will be described by taking a two-layer wiring as an example. Here, FIG. 8 to FIG. 10 are cross-sectional views showing the same process. 11 to 13 are plan views showing the process. First, an interlayer insulating film 502 made of a silicon oxide film or the like is formed on the substrate 501 by a CVD method or the like (FIGS. 8A and 11A). An element (not shown) such as a transistor is formed on the substrate 501. Note that the fine region R1 and the rough region R2 in FIG. 8A correspond to the left side and the right side in FIG. 11A, respectively. The same applies to the other drawings in FIGS.

Next, a resist 503 for F ₂ lithography is formed on the interlayer insulating film 502. Thereafter, the resist 503 is patterned by a photolithographic method of F ₂ wavelength using a mask having a pattern of 0.1 μm or less (FIGS. 8B and 11B). Further, the resist pattern is transferred to the interlayer insulating film 502 by a dry etching technique, thereby forming a wiring groove 504 having a thickness of 0.1 μm or less at a desired position. Thereafter, the remaining resist 503 is removed (FIGS. 9A and 12A).

  Subsequently, a resist 505 for ArF lithography is formed on the interlayer insulating film 502. Thereafter, the resist 505 is patterned by a photolithographic method using an ArF wavelength by using a mask having a pattern larger than 0.1 μm (FIGS. 9B and 12B). Further, the resist pattern is transferred to the interlayer insulating film 502 by a dry etching technique, thereby forming a wiring groove 506 larger than 0.1 μm at a desired position. Thereafter, the remaining resist 505 is removed (FIGS. 10A and 13A).

  Next, a conductor film 507 such as a Cu film or an Al film is formed on the entire surface of the interlayer insulating film 502 in which the wiring grooves 504 and 506 are formed by the CVD method or the like (FIGS. 10B and 13B). )). Thereafter, the conductor film 507 is polished by CMP until the interlayer insulating film 502 is exposed. As a result, damascene wiring 508 is formed at a desired position in the interlayer insulating film 502 (FIGS. 10C and 13C).

  FIG. 14 is a plan view showing an outline of a general logic product. A conventional configuration of a general CPU logic circuit will be described with reference to FIG. This product has four macro functions of an I / O block 701, a RAM block 702, a logic block 703, and a PLL block 704.

  The I / O block 701 is an area composed only of wiring having a wiring width of 1 μm or more. There is basically no need for fine wiring in this area. In addition, this area is an area that determines the allowable large current limit, and the maximum wiring width and via are determined by this area. The wiring connecting the circuit blocks of the I / O block is composed of two wirings, a wiring connected to the pad electrode (input wiring) and a wiring connected to the internal circuit (output wiring). In the conventional structure, an operation check transistor or the like is mounted in this area, and a device having the same minimum dimensions as the RAM block 702 can be mounted.

  The RAM block 702 generally has a memory of about 1 megabyte. For the wiring in this area, miniaturization is given priority over speed. Therefore, this area has the highest need for thin wiring. In this area, there are relatively few wide wirings, and the power supply and the GND wiring are periodically arranged in units of the memory cell size.

  The logic block 703 is a cell in which drive capability is required, and is a block in which power supply wiring is reinforced. The configuration of this area is basically close to the configuration of the standard cell of the gate array. Although the wiring configuration is similar to that of the RAM, the power supply wiring is generally more reinforced than the RAM. Unlike a PLL, there are generally a plurality of connections between macro circuits.

  In the PLL block 704, priority is given to stable operation of the power supply, GND, and the capacitive element. Therefore, although the wiring density is low, the wiring width is generally the second largest after the I / O region. The PLL amplifies a signal input from an external transmitter (for example, amplifies 4 times or 5 times), and configures a clock tree for each macro. A PLL basically has only two input / output wirings.

  Patent Document 1 is given as a prior art document related to the present invention.

JP-A-6-89839

  For the purpose of improving the performance and cost of semiconductor integrated circuits, the miniaturization is rapidly progressing. In order to manufacture a finer integrated circuit, the wavelength of light used in a lithography apparatus has been shortened. However, in the lithography process in the manufacturing process of the semiconductor integrated circuit, as a result of the shortening of the wavelength, there has been a problem that the light intensity of the short wavelength lithography apparatus is insufficient. Further, as the wavelength of the photolithography apparatus becomes shorter, damage to the lens becomes more serious as the wavelength becomes shorter. On the other hand, despite the progress of integration of circuit elements, the die size itself of the semiconductor integrated circuit has not been reduced but rather increased as the circuit scale has increased. Therefore, since it is necessary to set a wide field size, it is difficult to achieve both a wide field size and a high resolving power in a short wavelength lithography apparatus in which sufficient light intensity is difficult to obtain compared to a long wavelength lithography apparatus. In addition, there is a problem that flare occurs when a large pattern that allows light to pass is nearby, and the resolution of the fine pattern deteriorates. There is a difference in the amount of exposure for forming fine wiring. Furthermore, since proximity effect correction becomes large, there is a problem that if the area difference is large, the correction amount increases and the optimization man-hour for the correction amount increases.

  A semiconductor integrated circuit according to the present invention includes a first wiring provided in a first region on a substrate, a second wiring provided in a second region surrounding the first region on the substrate, The minimum design dimension of the wiring width of the first wiring is smaller than the minimum design dimension of the wiring width of the second wiring.

  In this semiconductor integrated circuit, the minimum design dimension of the wiring width of the first wiring is relatively small, and the minimum design dimension of the wiring width of the second wiring is relatively large. Therefore, in the manufacture of this semiconductor integrated circuit, lithography using light of the first wavelength (hereinafter referred to as short wavelength lithography) is used to form the wiring pattern of the first wiring, and the wiring pattern of the second wiring is formed. In addition, lithography using light having a second wavelength longer than the first wavelength (hereinafter referred to as long wavelength lithography) can be used. Here, the second region in which the second wiring is provided is a region surrounding the first region in which the first wiring is provided. Therefore, the field size in short wavelength lithography is smaller than the field size in long wavelength lithography. Thereby, sufficient light intensity can be obtained in short wavelength lithography. This contributes to an improvement in the resolution of short wavelength lithography and, in turn, miniaturization of the first wiring.

  The mask according to the present invention is a mask used for manufacturing the semiconductor integrated circuit, and is formed in the first portion of the mask, corresponding to the wiring pattern of the first wiring, and having a first wavelength. A first mask pattern transferred to the first region on the substrate by lithography with light and a wiring pattern of the second wiring formed on a second portion surrounding the first portion of the mask And a second mask pattern transferred to the second region on the substrate by lithography with light having a second wavelength longer than the first wavelength.

  According to this mask, the first mask pattern formed in the first portion is transferred to the first region on the substrate by short wavelength lithography, and the second mask pattern formed in the second portion. Is transferred to a second region on the substrate by long wavelength lithography. Here, the second part is a part surrounding the first part. Therefore, the field size in short wavelength lithography is smaller than the field size in long wavelength lithography. Thereby, sufficient light intensity can be obtained in short wavelength lithography.

  A method for manufacturing a semiconductor integrated circuit according to the present invention is a method for manufacturing a semiconductor integrated circuit using the mask, wherein the first region on the substrate is formed by lithography using light of the first wavelength. Transferring the first mask pattern; and transferring the second mask pattern to the second region on the substrate by lithography using light of the second wavelength. And

  In this manufacturing method, short-wavelength lithography and long-wavelength lithography are used for transferring the first and second mask patterns, respectively. Here, the second part is a part surrounding the first part. Therefore, the field size in short wavelength lithography is smaller than the field size in long wavelength lithography. Thereby, sufficient light intensity can be obtained in short wavelength lithography.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor integrated circuit which can obtain sufficient light intensity in short wavelength lithography, its manufacturing method, and a mask are implement | achieved.

It is a top view which shows one Embodiment of the semiconductor integrated circuit by this invention. It is a top view which shows the example of arrangement | positioning of TEG for process evaluation. It is a top view which shows one Embodiment of the mask by this invention. It is a graph which shows the dependence with respect to the field size of a scan area size. It is a graph which shows the dependence with respect to the field size of light intensity efficiency. It is a top view which shows the CPU logic circuit which can apply this invention. It is a top view which shows the layout of the test chip for general process evaluation. (A) And (b) is sectional drawing for demonstrating the process for forming a general two-layer wiring. (A) And (b) is sectional drawing for demonstrating the process for forming a general two-layer wiring. (A)-(c) is sectional drawing for demonstrating the process for forming a general two-layer wiring. (A) And (b) is a top view for demonstrating the process for forming a general two-layer wiring. (A) And (b) is a top view for demonstrating the process for forming a general two-layer wiring. (A)-(c) is a top view for demonstrating the process for forming a general two-layer wiring. It is a top view which shows the outline | summary of a general logic product.

  Hereinafter, preferred embodiments of a semiconductor integrated circuit, a manufacturing method thereof, and a mask according to the present invention will be described in detail with reference to the drawings. In the description of the drawings, the same reference numerals are assigned to the same elements, and duplicate descriptions are omitted.

  FIG. 1 is a plan view showing an embodiment of a semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit 1 includes a substrate, a first wiring provided in a region 11 (first region) on the substrate, and a second wiring provided in a region 12 (second region) on the substrate. It is equipped with. In the figure, the substrate and the first and second wirings are not shown. The substrate may be a semiconductor substrate or a substrate other than the semiconductor substrate.

  The region 12 is a region surrounding the region 11. Therefore, the field size of the region 11 is smaller than that of the region 12. The region 11 is symmetrical in the vertical and horizontal directions with the central portion of the semiconductor integrated circuit as the center. These regions 11 and 12 are regions for short wavelength lithography and long wavelength lithography, respectively.

In short wavelength lithography and long wavelength lithography, for example, excimer laser light can be used. Specifically, for example, F ₂ excimer laser light can be used in short wavelength lithography, and ArF excimer laser light can be used in long wavelength lithography. In this example, the first and second wavelengths are 157 nm and 193 nm, respectively.

  The minimum design dimension of the wiring width of the first wiring is smaller than the minimum design dimension of the wiring width of the second wiring. The minimum design dimension of the wiring width of the first wiring is, for example, 0.1 μm or less. Further, the region 11 and the region 12 are separated from each other. There is no wiring pattern in the region 13 (pattern prohibited region) between the region 11 and the region 12. The width of the region 13 is, for example, about 10 μm. The region 12 is, for example, an input / output circuit region of the semiconductor integrated circuit 1.

  FIG. 2 is a plan view showing an arrangement example of the process evaluation TEGs. The miniaturization process areas are symmetrically arranged on the left, right, and upper and lower sides with the field center as the center. In the central area 21, a process evaluation pattern mainly composed of wiring evaluation of 0.1 μm or less is arranged. The height and width of the central region 21, i.e. the height h1 and the width h2 of the field of the short wavelength lithography are 10 mm and 5 mm, respectively.

  Rough patterns other than the fine wiring pattern evaluation are arranged in the outer peripheral region 22. Specifically, the wiring is larger than 0.1 μm. In the case of the back-end process evaluation TEG, a wiring having a wide wiring width is arranged in the outer peripheral region 22. This is because when the wiring area is large, flare occurs, which causes a great hindrance to the formation of fine wiring. In order to prevent this, a fine pattern is collected in the central region. A pattern having a large wiring area is arranged on the outer periphery. Examples of patterns in which a TEG with a large wiring area is used include an SIV (Stress Induced Void) pattern in which a defect is generated at a via to wiring area ratio, a pattern for evaluating wiring width dependency, a capacitance measurement pattern, and the like. These patterns are arranged only in the outer peripheral region 22. Flares are likely to occur in blocks having a large wiring area. Therefore, by arranging the wiring area having a large area on the outside, there is an effect of eliminating the influence on the patterning of the fine wiring in the central portion. The height and width of the outer peripheral region 22, that is, the height h3 and the width h4 of the long wavelength lithography field are 25 mm and 20 mm, respectively.

  Between the central region 21 and the outer peripheral region 22, there is a prohibited region 23 where no TEG is arranged. The prohibited area 23 is composed of a sub chip 26. The size of the sub chip 26 is 2380 μm in the X direction (left and right direction in the figure) and 1580 μm in the Y direction (up and down direction in the figure). These central region 21, outer peripheral region 22, and forbidden region 23 correspond to region 11, region 12, and region 13 in FIG. 1, respectively.

  FIG. 3 is a plan view showing an embodiment of a mask according to the present invention. The mask 3 is a photomask used for manufacturing the semiconductor integrated circuit 1, and includes a first mask pattern formed on a portion 31 (first portion) of the mask 3 and a portion 32 (first portion) of the mask 3. 2), a second mask pattern formed on the second portion. In the figure, the first and second mask patterns are not shown.

  The first mask pattern corresponds to the wiring pattern of the first wiring, and is transferred to the region 11 on the substrate by short wavelength lithography. On the other hand, the second mask pattern corresponds to the wiring pattern of the second wiring, and is transferred to the region 12 on the substrate by long wavelength lithography. Therefore, also in the mask 3, the portion 32 corresponding to the region 12 surrounds the portion 31 corresponding to the region 11. Further, the portion 31 and the portion 32 are separated from each other, and there is no mask pattern in the portion 33 (pattern prohibited portion) between them.

  One embodiment of a method of manufacturing a semiconductor integrated circuit according to the present invention is a method of manufacturing a semiconductor integrated circuit 1 using a mask 3, and the first mask pattern is formed on the region 11 on the substrate by short wavelength lithography. And a step of transferring the second mask pattern to the region 12 on the substrate by long-wavelength lithography.

  The effect of this embodiment will be described. In the semiconductor integrated circuit 1, the minimum design dimension of the wiring width of the first wiring is relatively small, and the minimum design dimension of the wiring width of the second wiring is relatively large. Accordingly, in manufacturing the semiconductor integrated circuit 1, relatively short wavelength lithography is used for forming the wiring pattern of the first wiring, and relatively long wavelength lithography is used for forming the wiring pattern of the second wiring. Can do. In fact, in the manufacturing method described above, relatively short wavelength lithography and relatively long wavelength lithography are used to form the first and second wiring patterns, respectively.

  Here, the region 12 in which the second wiring is provided is a region surrounding the region 11 in which the first wiring is provided. Therefore, the field size in short wavelength lithography is smaller than the field size in long wavelength lithography. Thereby, sufficient light intensity can be obtained in short wavelength lithography. This contributes to an improvement in the resolution of short wavelength lithography and, in turn, miniaturization of the first wiring.

  Also, according to the mask 3, the first mask pattern formed in the first portion is transferred to the region 11 on the substrate by short wavelength lithography, and the second mask pattern formed in the second portion. Is transferred to region 12 on the substrate by long wavelength lithography. Here, the second part is a part surrounding the first part. Therefore, the field size in short wavelength lithography is smaller than the field size in long wavelength lithography. Thereby, sufficient light intensity can be obtained in short wavelength lithography.

  Between the region 11 and the region 12, a region 13 where no wiring pattern exists is provided. This region 13 is a region where desired pattern formation is not guaranteed due to data blur around the mask. Therefore, by not providing a wiring pattern in this region 13, it is possible to prevent an unintended pattern from being formed.

  When the minimum design dimension of the wiring width of the first wiring is 0.1 μm or less, it is necessary to use light having a particularly short wavelength in short wavelength lithography. Then, the subject mentioned above about a prior art, ie, the subject that it is difficult to obtain sufficient light intensity, becomes remarkable. Therefore, in this case, the present invention capable of obtaining sufficient light intensity even in short wavelength lithography is particularly useful.

  When both the first and second wavelength lights are excimer laser lights, both the short wavelength lithography and the long wavelength lithography can be executed with a simple apparatus. On the other hand, for example, when at least one of the first and second wavelengths of light is X-rays, a large-scale apparatus called an X-ray lithography apparatus must be used.

  As described above, Patent Document 1 describes that a resist on a semiconductor wafer is double exposed by X-rays and ultraviolet rays. It is described that such double exposure is performed in order to compensate for insufficient exposure in X-ray exposure by ultraviolet exposure. However, such a method cannot compensate for the shortage of UV exposure.

  FIG. 4 is a graph showing the dependence of the scan area size on the field size. FIG. 5 is a graph showing the dependence of the light intensity efficiency on the field size. The vertical axis in FIG. 5 represents the light intensity efficiency (%) when the light intensity efficiency when the field size is 25 mm is 100%. In this example, there is an offset scan area of 15 mm in addition to the effective scan area. In this state, when the scan area as the device exposure area is simply reduced from 25 mm, the scan area decreases linearly. Light intensity efficiency increases linearly with decreasing scan area size. For example, as can be seen from FIG. 5, when the field size is about 10 to 15 mm, the efficiency of light intensity is increased by about 30% compared to the case of 25 mm.

  In this regard, from the viewpoint of obtaining a device-like improvement effect, it is preferable that an increase of 20% or more is observed in the light intensity efficiency. Therefore, as can be seen from FIG. 5, by setting the field size to 20 mm or less, a remarkable effect can be expected for miniaturization. That is, the first region is preferably a region that fits within a square region having a side of 20 mm. For example, when the first region is a square having a side of 20 mm or less, a rectangle having a long side of 20 mm or less, or a circle having a diameter of 20 mm or less, the first region is within a square region having a side of 20 mm. Fits in. On the other hand, when the first region is a square having one side of more than 20 mm, a rectangle having a longer side of more than 20 mm, or a circle having a diameter of more than 20 mm, the first region is within a square region having one side of 20 mm. Does not fit in.

  The present invention can be applied to, for example, the CPU logic circuit shown in FIG. The CPU logic circuit shown in FIG. 1 has an I / O block (interface block) 61, a RAM block 62, a high-performance logic block 63, and a PLL block 64. The I / O block 61 is called peripheral I · O, and corresponds to the region 12 (see FIG. 1). The RAM block 62, the high-performance logic block 63, and the PLL block 64 are miniaturized areas including wiring of 0.1 μm or less, and correspond to the area 11.

  The wiring of the I / O block 61 is limited to wiring larger than 0.1 μm. The I / O block 61 is patterned by long wavelength lithography. Thus, by limiting the minimum design dimension of the wiring of the I / O block 61, the field area of the short wavelength lithography can be reduced by the area of the I / O block 61.

  By deleting the fine wiring data of the I / O block 61, the data area can be reduced and the light intensity can be improved. Thereby, since the field size of short wavelength lithography becomes small, there exists a merit that a resolution improves. In addition, by making an arrangement linked to the aperture structure of lithography, it is possible to obtain a semiconductor integrated circuit having a fine pattern by applying field-limited exposure.

  The semiconductor integrated circuit, the manufacturing method thereof, and the mask according to the present invention are not limited to the above-described embodiments, and various modifications are possible. For example, in the above-described embodiment, an example in which two regions of the first region and the second region are provided as the region in which the wiring pattern is formed has been described. However, three or more regions in which the wiring pattern is formed are illustrated. An area may be provided. For example, a third region surrounding the second region may be provided. Even in the case where three or more regions are provided in this way, the first wiring formed in the first region located on the innermost side is compared with the wiring in any other region. The minimum design dimension of the wiring width is small.

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit 3 Mask 11 area | region (1st area | region)
12 regions (second region)
13 area (pattern prohibited area)
21 Central area 22 Outer peripheral area 23 Forbidden area 26 Subchip 31 part (first part)
32 parts (second part)
33 part (pattern prohibited part)
61 I / O block 62 RAM block 63 High-performance logic block 64 PLL block

Claims (6)

  A first mask pattern formed in the first portion and corresponding to the wiring pattern of the first wiring, and formed in a second portion surrounding the first portion, and more wired than the first wiring Preparing a mask comprising: a second mask pattern corresponding to a wiring pattern of a second wiring having a large minimum design dimension of width;
  Transferring the first mask pattern to a first region on the substrate by lithography with light of a first wavelength;
  Transferring the second mask pattern to a second region surrounding the first region on the substrate by lithography with light having a second wavelength longer than the first wavelength;
  A method for manufacturing a semiconductor integrated circuit, comprising:   The method of manufacturing a semiconductor integrated circuit according to claim 1,
  The first part and the second part are separated from each other with a third part interposed therebetween,
  A method of manufacturing a semiconductor integrated circuit in which no mask pattern exists between the third portions. In the manufacturing method of the semiconductor integrated circuit according to claim 1 or 2,
The method of manufacturing a semiconductor integrated circuit , wherein the second region is an input / output circuit region of the semiconductor integrated circuit. In the manufacturing method of the semiconductor integrated circuit according to any one of claims 1 to 3,
A method of manufacturing a semiconductor integrated circuit , wherein a minimum design dimension of a wiring width of the first wiring is 0.1 μm or less. The method for manufacturing a semiconductor integrated circuit according to claim 1,
The method of manufacturing a semiconductor integrated circuit , wherein the first region is a region that fits in a square region having a side of 20 mm. In the manufacturing method of the semiconductor integrated circuit according to claim 1 ,
The method for manufacturing a semiconductor integrated circuit, wherein the light beams having the first and second wavelengths are both excimer laser beams.

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