JPH04287908A - Aligner and exposure method - Google Patents

Abstract

PURPOSE:To exposure an IC chip of a large size at a high throughput by a method wherein the patterns of first and second reticles are provided in such a way that they are transferred on the surface of a substrate to be exposed and an aligner is provided with lighting and projection optical systems for emitting light on the above first and second reticles. CONSTITUTION:A stage 2 which is moved on a rail is arranged on a pedestal and a substrate 1 to be exposed is placed on this stage 2. Lighting optical systems 3 are provided in such a way as to this substrate 1 and reduction projection lenses are provided between these systems 3 and the substrate 1. First and second reticles 10 and 20 are arranged between these lenses and the systems 3. A pattern of the first reticle is printed on the surface of the substrate 1. Then, after a fine adjustment of the stage is performed, a pattern of the second rericle is printed on the surface of the substrate 1 adjoining the pattern already formed on the substrate surface in such a way that the patterns are made to connect to each other.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Conventional technology (Figures 5 and 6) Problems to be solved by the invention Means for solving the problems (Figure 1) Effect No. 1 Example (Fig. 1) Second Example (Fig. 2) Third Example (Fig. 1, Fig. 2) Fourth Example (Fig. 3, Fig. 4) Fifth Example Example Sixth embodiment (FIGS. 5 to 8) Seventh embodiment Eighth embodiment (FIG. 9) Effects of the invention [Summary] Exposure apparatus and exposure used for forming a semiconductor integrated circuit pattern using photoresist Regarding the method, large chip
The purpose of the present invention is to provide an exposure apparatus and an exposure method that can pattern C and expose IC chips as large as possible with high throughput. a stage that can arbitrarily move laterally and rotate the substrate to be exposed; and a first position facing the substrate placed on the stage so as to be able to expose and form a pattern on the surface of the substrate to be exposed. a first reticle placed at a position opposite to the substrate to be exposed placed on the stage and at a position different from the first position so as to be able to form a pattern on the surface of the substrate to be exposed by exposure; and a second reticle configured to transfer the pattern of the first reticle and the pattern of the second reticle onto the surface of the substrate to be exposed;
The second reticle is configured to include an illumination and projection optical system that irradiates light onto the reticle and the second reticle.

[Industrial application field]

The present invention relates to an exposure apparatus and an exposure method used for forming a semiconductor integrated circuit pattern using photoresist.

2. Description of the Related Art In recent years, semiconductor integrated circuits (ICs) are required to be compact and highly functional, and are becoming increasingly highly integrated. At the same time, chip area is also gradually increasing. There is an urgent need to mass-produce such large-sized IC chips with high throughput.

In manufacturing this semiconductor IC (7), in the exposure process, that is, the light irradiation process used to form a mask pattern on the photoresist when etching a conductive layer, an insulating layer, etc. using photolithography, It has become necessary to be able to irradiate light over as wide a range as possible at once. On the other hand, a device called a reduction projection exposure device (stepper) is usually used in this exposure process. In the reduction projection exposure performed with this apparatus, a pattern that is, for example, five times larger than the pattern that is actually transferred to the surface of the substrate to be exposed is drawn on a transparent substrate called a reticle, and this reticle is used with a reduction lens, for example. The image is reduced to one-fifth and transferred to the photoresist on the surface of the substrate to be exposed.

However, in order to simply irradiate a wide area with light,
A fairly large lens is required. For example 2
The reduction lens for forming a 0 mm square chip pattern is made by stacking about 20 lenses each having a diameter of about 25 cm. With such a large lens, for example, the minimum line width is 0.3
Even if we tried to use it to draw patterns as fine as 5 μm, the processing accuracy of this lens surface was close to the technical limit.
Moreover, the speed at which IC chips are increasing in size is even now exceeding the speed at which lens exposure areas are increasing in size, and we are approaching the stage where it is no longer possible to draw even finer patterns. For example, 256 Mbit DRAM (Dy
namic Random Access Memory
It is extremely difficult to realize an apparatus that can pattern y) on two chips at the same time.

As described above, new technology is eagerly awaited in order to expose IC chips as large as possible with high throughput.

[Conventional technology]

In the past, attempts have been made to solve the technical difficulties of such optical systems using other methods. For example, a technique called stitching uses one I
The C pattern is divided into two reticles, for example, and the reticle patterns are connected to each other at the exposure stage. Specifically, the pattern of a large chip is divided into N pieces, a reticle for each pattern is manufactured and prepared, and when printing onto the actual wafer or mask, the N reticles are exchanged and exposed. It is something.

FIG. 10 is an explanatory diagram (perspective view) of the surface level of the exposed substrate, and FIG. 11 is a numerical graph of the surface level difference of the exposed substrate. Referring to these, it is clear that even in an area of at most 20 mm square, a step on the surface is sufficient to defocus during fine pattern exposure. Needless to say, the more you try to expose a wide area at once, the more this problem of defocus will become more serious. A technique that uses stitching to focus on each small area seems to be effective in solving this problem.

[Problems to be Solved by the Invention] However, with the conventional exposure method described above, the current circuit pattern is too difficult to simply connect patterns using this method due to the difficulty in alignment accuracy before and after replacing the reticle. are also minute, and it is technically extremely difficult to connect the patterns neatly at the connecting parts of the two. For example, in order to divide the main circuit part of an IC pattern, during actual exposure, it is difficult to There is a possibility that the position of the connecting part of the main circuit will be shifted beyond the design margin.

For this reason, there are many problems such as having to make the pattern thicker in consideration of the margin at this connection part, or imposing restrictions on circuit design in order to minimize this connection. In addition, there is also the problem that the probability of particles adhering to the reticle increases due to the disturbance of the atmosphere around the reticle before and after the reticle is replaced, which leads to a decrease in yield. In reality, this appears as an impact on throughput. That is, it is necessary to inspect the reticle for dust every time the reticle is replaced with respect to one wafer, and in terms of throughput, it cannot be used for mass production, and is limited to experimental use at best.

Therefore, in view of the above points, the present invention has been developed to realize a large-chip IC without dividing the main circuit portion composed of fine patterns.
An object of the present invention is to provide an exposure apparatus and an exposure method that can pattern an IC chip as large as possible and expose it with high throughput.

[Means to solve the problem]

In order to solve the above problems, the present invention has the following configuration as main means.

(1) A stage on which a substrate to be exposed is mounted, which can be arbitrarily moved vertically and horizontally on a plane and can rotate the substrate to be exposed; a first reticle placed at a first position facing the substrate to be exposed placed on a stage; and a first reticle placed at a first position facing the substrate to be exposed placed on the stage; a second reticle facing the exposed substrate and placed at a position different from the first position; and transferring a pattern of the first reticle and a pattern of the second reticle onto the surface of the exposed substrate. 1. An exposure apparatus characterized by having an illumination and projection optical system configured to irradiate the first reticle and the second reticle with light. or (2) a reticle stocker that stores the third reticle; and a transport device that takes out the third reticle from the reticle stocker and replaces it with the first reticle. exposure equipment. 3. The exposure apparatus according to claim 2, wherein the transport device operates simultaneously when transferring the pattern of the second reticle onto the surface of the substrate to be exposed. Alternatively, (4) using the exposure apparatus according to claim 1, transferring a pattern of the first reticle to a first position on the surface of the substrate to be exposed; An exposure method comprising the step of transferring a pattern of the second reticle to the position. Alternatively, (5) using the exposure apparatus according to claim 2, transferring a pattern of the first reticle to a first position on the surface of the substrate to be exposed; and a step of transferring a pattern of the first reticle to a second position of the substrate to be exposed. To,
An exposure method comprising the steps of transferring a pattern of the second reticle, and replacing the third reticle with the first reticle. or (6) using the exposure apparatus according to claim 3, transferring a pattern of the first reticle to a first position on the surface of the substrate to be exposed; and a step of transferring a pattern of the first reticle to a second position of the substrate to be exposed. To,
An exposure method comprising the steps of transferring a pattern of the second reticle and replacing the third reticle with the first reticle. Alternatively, (7) the large pattern is divided into two, each of the divided patterns is provided in the first reticle and the second reticle, and the first pattern is to be transferred by the first reticle. 7. The exposure method according to claim 4, wherein the second pattern to be transferred by the second reticle is transferred so as to be connected to each other on the surface of the exposed substrate.

Or, (8) Divide the large pattern into n parts (n≧3, n is an integer),
having each divided pattern on the first reticle, the second reticle, and the n-th reticle,
All of the n-th reticles are included in the reticle stocker or the transport device, and a first pattern to be transferred by the first reticle and a second pattern to be transferred by the second reticle are included in the n-th reticle. 7. The exposure method according to claim 5, wherein the pattern and the n-th pattern to be transferred by the n-th reticle are transferred so as to be connected to each other on the surface of the exposed substrate. (9) An exposure method characterized in that a desired pattern is obtained after development by overlapping exposure of different reticle patterns on the same exposure area on a wafer.

In this case, in the case of a dense pattern, if it is divided into a plurality of patterns, each part becomes a coarse pattern, the optical interference effect between patterns can be reduced, and a fine pattern can be formed.

Furthermore, when it is desired to form a pattern on a chip having large steps, the patterns can be classified according to each step and exposed separately under optimal conditions, making it possible to form a desired pattern at each step.

Alternatively, (10) a step of transferring a first pattern consisting of a plurality of linear patterns that are not connected to each other to a first position on the surface of the substrate to be exposed using a first reticle; With the second reticle, a second pattern consisting of a plurality of linear patterns that are not connected to each other is printed on the first reticle.
10. The exposure method according to claim 9, further comprising the step of transferring the pattern so as not to overlap the pattern. in this case,
This can be carried out using the exposure apparatus according to claims 1 to 3.

Alternatively, (11) when forming a circuit pattern of a semiconductor device, the pattern corresponding to the first density area and the pattern corresponding to the second density area are divided, and the first reticle Claim 9 characterized in that the second reticle has:
Exposure method described. In this case, it can be carried out using the exposure apparatus according to claims 1 to 3. Alternatively, (12) the first reticle and the second reticle have the same reticle pattern, and using the first reticle,
A claim characterized by comprising the steps of transferring a pattern to a first region on the surface of the substrate to be exposed, and using a second reticle to transfer the pattern to the first region of the surface of the substrate to be exposed. 9. The exposure method according to 9. In this case, the exposure apparatus described in claim 1 can be used. Or (13) IC with large and small pattern sizes in the same layer.
An exposure method for exposing a chip, characterized in that exposure is performed by using exposure apparatuses with different resolutions depending on the pattern size. (14) The exposure method according to claim 12, characterized in that the main circuit portion of the IC chip, the dicing line portion, and the bonding pad portion are separately exposed.

Or, (15) without developing the wafer exposed with the projection optical system,
The exposure method according to claim 12 is characterized in that the wafer is exposed again to a different pattern.

[Effect]

In the present invention, as shown in FIG. 1, after each reticle is set and aligned and exposed using the exposure system A,
The stage can be moved while the wafer is being sucked, and then the exposure system B can be used to expose a desired position relative to the area exposed in A, which is advantageous in the following points.

■It becomes possible to share the exposure pattern between two projection lenses. Therefore, a large chip that does not fit within the effective exposure area of one projection lens can be divided into two parts and exposed using each exposure system.

■In the case of a 1-chip reticle, the same reticle can be set on both sides to inspect foreign objects on the reticle, so if one reticle is judged to have no foreign objects in the inspection, the reticle with no foreign objects will be placed on the reticle. Exposure can be started immediately using only the exposure system that is available.

■It is possible to assign functions to each reticle, such as one reticle containing only the IC pattern and the other reticle containing only alignment marks, so even if the model of exposure equipment used changes, one reticle may only contain the IC pattern. Only the reticle that contains the alignment marks needs to be remade.

(2) Also, in relation to (2) above, with the latter reticle, alignment marks can be made in the area where normal chips are formed, so the number of patterns in the dicing line can be significantly reduced.

■Since reticles with different patterns can be set on multiple projection lenses, it is ideal for pattern exposure of small-volume, high-mix ASICs and wafer scale LSIs, eliminating the need to change reticles midway through, and eliminating the need for extra alignment. This improves throughput.

Furthermore, in the present invention, the main circuit section is exposed with an exposure device with high resolution and a small effective exposure area, and the pad section and dicing line section are exposed with an exposure device with low resolution and a large effective exposure area. It becomes possible to expose large chip ICs. Details will be explained in the sixth to eighth embodiments.

[First Embodiment] A first embodiment of the present invention will be described below with reference to FIG. 1. FIG. 1 is a schematic explanatory diagram of an exposure apparatus according to a first embodiment of the present invention. In FIG. 1, a stage 2 movable on a rail is arranged on a pedestal. A substrate to be exposed (semiconductor wafer) 1 is placed. An illumination optical system 3 is arranged so as to face the substrate 1 to be exposed.
That is, a light source is provided, and a reduction projection lens is provided between the illumination optical system 3 and the substrate 1 to be exposed.

A first reticle 10 and a second reticle 20 are arranged between the reduction projection lens and the illumination optical system 3.

The exposure apparatus shown in FIG. 1 will be described in more detail.

First, before the substrate 1 to be exposed is placed on this exposure apparatus, a photoresist is uniformly formed on the surface by, for example, spin coating. The exposed substrate 1 on which the photoresist is formed is placed on the stage 2 by a known robot arm. This stage 2 has a rail in the Y direction on the pedestal,
It consists of a Y stage that moves on this rail, a rail provided on this Y stage, an X stage that moves on this rail, and a rotatable θ stage that is provided on this X stage. The structure is such that the above-described substrate 1 to be exposed is placed on a stage. In addition,
Instead of the configuration in which the X stage is placed on the Y stage, a configuration in which the Y stage is placed on the X stage may be used. In addition, when two reduction projection lenses placed apart from each other so as to face the stage 2 form a pattern each having a size of 20 mm x 20 mm on the substrate to be exposed,
Approximately 20 lenses with a diameter of approximately 25 cm are stacked in series.

Next, before exposing the actual product wafer, a foreign matter inspection is usually performed on the reticle.
Sometimes it is developed and inspected using a separate inspection device.

After the substrate 1 to be exposed is placed on such a stage 2, if it is confirmed as a result of inspection that there is no foreign matter on the reticle, the exposure (patterning) process of the substrate 1 to be exposed is started. First, the relative position of one of the two reduction projection lenses (the first reduction projection lens) arranged at the top of the apparatus is finely adjusted. This fine adjustment may be performed using alignment marks formed on the X stage.

On the other hand, in order to reduce the image with the reduction projection lens before this, a first
The reticle is patterned with half of one large pattern.

The pattern of this first reticle is printed onto the surface of the substrate 1 to be exposed, and then, after fine adjustment of the stage similar to that described above, the pattern of the second reticle is printed on the surface of the substrate 1 to be exposed. The patterns are printed on the surfaces adjacent to each other so that the patterns connect to each other. In addition, 2
The same procedure is followed for subsequent wafers, but in the present invention, since the reticle remains set on the projection lens, there is no possibility of dust adhering to the reticle, so for the second and subsequent wafers, There is no need to inspect foreign matter (dust) on the reticle.

With such a procedure, a large pattern can be printed onto the surface of the substrate to be exposed without the trouble of frequently replacing the reticle and without the accompanying particle attachment.

The exposure technique described above can also be applied as follows.

FIG. 3 shows an embodiment of the invention. For example, the size of each IC to be exposed (or patterned) is 10 mm.
x 24mm, and the exposure area of the projection lens is 20m.
If the size is m x 20 mm, the chips are made horizontally long as shown in FIG. 3, and two chips are configured vertically, and two types of reticles are created by dividing the chips vertically. In addition, when manufacturing a long IC such as a CCD (charge-coupled device), for example, the reticle is divided into three parts, and an exposure device with three units shown in Figure 1 is used to separate the reticle into three parts. It can also be manufactured as a set.

[Second example] Next, a second embodiment of the present invention will be described.

FIG. 2 is a schematic explanatory diagram of an exposure apparatus according to a second embodiment of the present invention. In FIG. 2, the same numbers as in FIG. 1 indicate the same items as in FIG.

The exposure apparatus shown in FIG. 2 differs from that shown in FIG. 1 in that it is equipped with a reticle stocker 4. The exposure apparatus shown in FIG.

Explain in detail.

This reticle stocker 4 is configured to store a third reticle 30, from which a third reticle is appropriately selected.
The reticle 30 is sent to a predetermined position in the A unit by the transport device and is replaced with the first reticle 10.

In this way, if the first reticle 10 or the second reticle 20 is replaced as appropriate, three or more types of patterns can be formed without preparing three or more units. For example, it is particularly convenient for the production of ASICs (application-specific integrated circuits), which are often produced in small quantities and in a wide variety of products.

First, in exposing the circuit pattern of the first type of ASIC, the first reticle 10 is set in the A unit, and the second reticle 20 is set in the B unit. Next, in order to expose the circuit pattern of the second type of ASIC, the first reticle 10 is transported to and stored in the reticle stocker 4 by the robot arm. Next, a necessary third reticle 30 is retrieved from the reticle stocker 4, and the robot arm transports this third reticle 30 to the A unit and places it there.

This transfer by the robot arm is performed by the second reticle 20.
If this is done during patterning, the process time can be shortened. In the second embodiment of the present invention described above, a case has been described in which there is one reticle stocker 4 for two reduction projection lenses (two units), but these numbers may be changed as appropriate. This is easily possible.

[Third Embodiment] The exposure technique of the present invention is not only used for divided exposure of large patterns as described above. Other application examples will be explained below.

For example, it can be used to inspect foreign matter on the surface of a pattern. That is, using the exposure apparatus of the present invention described in FIGS. 1 and 2, which have already been described, a reticle on which the same reticle pattern is formed is set in each of a plurality of units. Patterns are separately exposed on the surface of the substrate to be exposed, and only the reticle with a normal pattern is adopted.
Subsequent exposure is performed.

In other words, the reticle (chip A) set in unit A
1, A2) and the reticle (chips B1, B2) set in the B unit, if the results are as shown below, it is sufficient to expose the product wafer using only the B unit.

By doing this, it is possible to save the effort of replacing the reticle when pattern defects occur due to particles (fine foreign matter) on the reticle surface, and to avoid generation of particles when replacing the reticle.

Alternatively, by setting the same reticle in multiple units in this way, different pattern exposures can be performed. Although it is necessary that the alignment accuracy sufficiently exceeds the fineness of the circuit pattern, the surface of the substrate 1 to be exposed is half-baked using the first reticle 10. In other words, a certain amount of exposure is temporarily performed, even if it is not sufficient for exposure. Next, the stage 2 is moved, and the same area on the surface of the substrate 1 to be exposed is half-baked using the second reticle 20. Since it is considered that particles will not be splashed at the exact same position on the surface of the first reticle 10 and the surface of the second reticle 20, if the exposure is finally completed by a series of half-baking operations,
Even if particles are present on the first reticle 10 or the second reticle 20, it is possible to minimize the possibility that the particles will cause pattern defects after exposure.

Alternatively, for example, a rectangular pattern may be half-baked, and then the rectangular patterns are overlapped perpendicularly to the rectangular pattern and half-baked, so that only the overlapping portions are exposed as a square pattern.

[Fourth Embodiment] For example, in the case of alignment marks that use only a few points on the wafer, or when you want to expose a monitor chip,
Create a reticle as shown.

Reticle AAA consists only of product IC chips, and reticle BBB consists of a monitor chip and a chip containing alignment marks.

This reticle can be set in each of the exposure units A and B shown in FIG. 1 to expose a wafer in a layout as shown in FIG. 4.

In this case, the number of monitor chips occupying one wafer can be kept to the minimum necessary, and the number of marks on the dicing line can also be reduced.

[Fifth Example] Although similar to the fourth example, a special case will be described.

IC pattern projection exposure lenses with higher resolution are more expensive, but in most cases the alignment mark is 1 μm.
It is composed of a pattern that is larger than the front and back widths, and a projection lens with low resolution performance can be used to expose this mark. Therefore, if only the alignment marks are to be exposed using the reticle BBB described in the third embodiment, the projection lens used in the B unit in FIG. 1 may be replaced with an inexpensive low-resolution lens. .

Alternatively, a unit with variable optical system performance may be used as at least one of the two units. By making the numerical aperture NA (Numerical Aperture) of the lens variable, the resolving power can be changed, or partial . Partial Coherency
If cy) is made variable, it is also possible to change the fidelity of the pattern shape and the depth of focus.

Also, if you use multiple units, you can change the specifications of the unit itself so that the first wavelength handled by one unit is different from the second wavelength handled by the other unit. It is also possible to form a positive pattern by exposure and form a negative pattern by exposure with a second wavelength.

[Sixth Embodiment] In the present invention, in an exposure method for exposing an IC chip having large and small pattern sizes in the same layer, there is a case where exposure is performed by sharing the exposure with exposure apparatuses having different resolutions depending on the pattern size. It's okay. That is, the main circuit section consisting of a fine pattern and the pad section and dicing line section consisting of a relatively coarse pattern are divided into separate reticles or masks, and each is exposed using a separate projection exposure apparatus.

There is a contradictory relationship between the resolution and effective exposure area of an exposure device, and exposure devices with low resolution generally have a wide effective exposure area, such as Canon's MPA (product name: resolution = approximately 2 μm
, effective exposure area = 150 mmφ), NSR manufactured by Nikon Corporation
3025HT (trade name: resolution=approximately 2 μm, effective exposure area=30 mm□). On the other hand, there are many exposure apparatuses with high resolution, but their resolution is about 0.65 μm and the effective exposure area is about 20 mm square at most. Therefore, it is recommended that the main circuit section, which is made up of fine patterns, be exposed with a high-resolution exposure device, and the pad section and dicing line section, which are made up of coarse patterns, are exposed with an exposure device that has low resolution and a large effective exposure area. .

The exposure method will be specifically described below with reference to the drawings.

FIG. 5 is a diagram showing the IC chip 51 to be exposed. Here, the size of the IC chip 51 to be exposed is set to 17 mm.
Furthermore, the exclusive area of the main circuit section 52 consisting of the fine pattern section is 14 mm square. In addition, 53 is a pad part,
54 is a dicing line portion, and the pad portion 53 and the dicing line portion 54 are 17 mm square.

In this case, assuming that the fine pattern of the main circuit section 52 is made up of approximately 0.5 μm, and the pad section 53 and the dicing line section 54 are formed of a 1 μm rule, the exposure apparatus is, for example, You can use .

Next, as shown in FIGS. 6(a) and (b), the reticle is
Reticle A for main circuit stepper A (Fig. 6(a)),
A reticle B (FIG. 6(b)) for the pad portion and dicing line portion stepper B is formed. Note that 55 is a light shielding portion made of Cr or the like.

Then, as shown in FIG. 7, the main circuit section 52 is laid out by exposing the wafer 56 using reticle A and stepper A, and as shown in FIG. A desired IC resist pattern can be obtained by exposing the top to light to lay out the pad portion 53 and the dicing line portion 54 and then developing it. Note that the main circuit section 52, the pad section 53, and the dicing line section 54 may be formed in any order.

That is, in the above embodiment, the main circuit section 52 has high resolution and
Since the pad portion 53 and the dicing line portion 54 are exposed using an exposure device with a small effective exposure area, and the pad portion 53 and the dicing line portion 54 are exposed with an exposure device with a low resolution and a large effective exposure area, it is possible to expose a large chip IC with a high degree of integration.

[Seventh Embodiment] As an exposure method in which exposure apparatuses having different resolutions are assigned to perform exposure according to the pattern size, the exposure apparatus shown in FIG. 1 may be used.

As shown in FIG. 1, the exposure method is to first expose the pattern of the first reticle 10 onto the substrate 1 to be exposed using the projection lens 3 on the left side of the figure, and then move the stage 2 on which the substrate 1 to be exposed is placed. The second reticle 20 is moved directly under the projection lens 3 on the right side, and the pattern of the second reticle 20 is exposed onto the substrate 1 to be exposed.

In this embodiment, in addition to being able to obtain the same effects as in the sixth embodiment, the exposed substrate 1 exposed (first time) by the projection optical system is moved while being adsorbed to the stage 2 without being developed. Since it is possible to expose a different pattern again, it is not necessary to once remove the substrate to be exposed and align it when exposing the substrate again, so that the process time can be shortened.

In this example, the case where separate projection lens systems are used has been explained, but the case where the same projection lens system is used
Exposure may be performed by changing A. Of course, we also exchange reticles.

Note that the wafer is continuously exposed to light while being attracted.

In this case, there is an advantage that the same lens can be used and the optimum NA can be selected.

[Eighth Embodiment] In the sixth and seventh embodiments, the case where the dicing part and the pad part and the main circuit part are manufactured separately was explained, but the pattern within the effective exposure area of the lens used for each was explained. It may also be possible to manufacture a mixture of materials. That is, the main circuit section may be located at the periphery of the wafer, and the peripheral circuit section may be located at the center of the wafer.

For example, when using the reticles shown in FIGS. 9(a) and 9(b), the pattern group in the area 61 that becomes the main circuit section uses the reticles shown in FIGS. 9(a) and 9(b), respectively. If both are exposed, they will be exposed together. That is, in the center of the wafer, fine patterns that form the main circuit and rough patterns that form the peripheral circuit coexist.

In this embodiment, the same effects as in the sixth and seventh embodiments can be obtained. For example, when a fine pattern that becomes the main circuit and a rough pattern that becomes the peripheral circuit are mixed in the center part ( (The same applies when fine patterns and coarse patterns are mixed in the peripheral area), and when fine patterns and coarse patterns are close to each other, they are exposed separately, which prevents the proximity effect caused by light interference and enables faithful exposure to the reticle pattern. There is an advantage.

In addition, although each of the above embodiments describes the case where only a light exposure device is used, the present invention is not limited to this.
It can be applied to optical exposure equipment, electron beam exposure equipment, X-ray exposure equipment, etc.

As a combination example, etc.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to pattern a large chip IC without dividing the main circuit section, which is composed of fine patterns, as in the case of conventional stitching, and the projection exposure lens can be effectively used. Even if the chip is larger in size than the exposure area, it can be easily and stably exposed.

[Brief explanation of the drawing]

FIG. 1 is a schematic explanatory diagram of an exposure apparatus according to a first embodiment of the present invention, FIG. 2 is a schematic explanatory diagram of an exposure apparatus according to a second embodiment of the present invention, and FIG. 3 is a schematic explanatory diagram of an exposure apparatus according to a second embodiment of the present invention. FIG. 4 is a schematic illustration of a substrate to be exposed after exposure by an exposure method according to a fourth embodiment of the present invention, and FIG. 5 is a schematic diagram of a reticle according to a sixth embodiment of the present invention. FIG. 6 is a diagram showing each reticle according to the sixth embodiment of the present invention, and FIG. 7 is a diagram showing a stepper A using reticle A according to the sixth embodiment of the present invention. 8 is a diagram showing a wafer exposed and laid out by stepper B using reticle B according to the sixth embodiment of the present invention; FIG. 9 is a diagram showing a wafer exposed and laid out by stepper B according to the sixth embodiment of the present invention. FIG. 10 is an explanatory diagram of the surface level difference of the exposed substrate, and FIG. 11 is a numerical graph of the surface level difference of the exposed substrate. DESCRIPTION OF SYMBOLS 1... Substrate to be exposed, 2... Stage, 3... Illumination optical system, 4... Reticle stocker, 10... First reticle, 20... Second reticle, 30... Third reticle.

Claims (15)

[Claims] 1. A stage (2) on which a substrate to be exposed (1) is placed, and which can arbitrarily move vertically and horizontally on a plane and rotate the substrate to be exposed (1); (1) The exposed substrate (1) placed on the stage (2) so that a pattern can be formed on the surface by exposure.
a first reticle (
10), and a position opposite to the substrate to be exposed (1) placed on the stage (2) and different from the first position so that a pattern can be formed by exposure on the surface of the substrate to be exposed (1). a second reticle (20) disposed on the surface of the exposed substrate (1) so as to transfer the pattern of the first reticle (10) and the pattern of the second reticle (20) onto the surface of the exposed substrate (1); An exposure apparatus characterized in that it has an illumination and projection optical system (3) that is provided and irradiates the first reticle (10) and the second reticle (20) with light. 2. A reticle stocker (4) for storing a third reticle (30); and a reticle stocker (4) for storing the third reticle (30).
2. The exposure apparatus according to claim 1, further comprising a transport device for taking out the reticle from the reticle and replacing it with the first reticle. 3. The transport device operates simultaneously when transferring the pattern of the second reticle (20) onto the surface of the exposed substrate (1).
The exposure apparatus described. 4. Using the exposure apparatus according to claim 1, the first reticle (
10); and then, transferring the pattern of the second reticle (20) to a second position of the exposed substrate (1). Exposure method. 5. Transferring a pattern of the first reticle (10) to a first position on the surface of the substrate (1) to be exposed using the exposure apparatus according to claim 2; transferring the pattern of the second reticle (20) to a second position of the substrate (1); and transferring the third reticle (30) to the first reticle (10).
). 6. A step of transferring a pattern of the first reticle (10) to a first position on the surface of the substrate (1) to be exposed using the exposure apparatus according to claim 3; transferring the pattern of the second reticle (20) to a second position of the substrate (1), and replacing the third reticle (30) with the first reticle (10). An exposure method characterized by: 7. A large pattern is divided into two, and each divided pattern is provided in the first reticle (10) and the second reticle (20), the first reticle (10) The first to be transcribed by
and the second pattern to be transferred by the second reticle (20) are transferred so as to be connected to each other on the surface of the exposed substrate (1). Exposure method described. [Claim 8] Divide the large pattern into n (n≧3, n is an integer)
and each of the divided patterns is included in the first reticle (10), the second reticle (20), and the n-th reticle, and all of the n-th reticles are stored in the reticle stocker ( 4)
or the first reticle (1
0) and the second pattern to be transferred by
a second pattern to be transferred by the n-th reticle (20); and an n-th pattern to be transferred by the n-th reticle (20).
6. The pattern is transferred so as to be connected to each other on the surface of the exposed substrate (1).
Exposure method described. 9. An exposure method characterized in that a desired pattern is obtained after development by overlapping exposure of different reticle patterns on the same exposure area on a wafer. 10. At a first position on the surface of the exposed substrate (1),
Transferring a first pattern consisting of a plurality of linear patterns that are not connected to each other using a first reticle (10); Transferring a plurality of linear patterns that are not connected to each other to the first position using a second reticle (20); 10. The exposure method according to claim 9, further comprising the step of transferring a second pattern consisting of a linear pattern of a book so as not to overlap with the first pattern. 11. When forming a circuit pattern of a semiconductor device, a pattern corresponding to a first density area and a pattern corresponding to a second density area are divided, and each pattern is formed on the first reticle ( 10) The exposure method according to claim 9, wherein the second reticle (20) includes: 10). 12. The first reticle (10) and the second reticle (20) have the same reticle pattern, and the first reticle (10) is used to measure the surface of the substrate (1) to be exposed. a step of transferring a pattern to a region of the exposed substrate (1) using the second reticle (20);
10. The exposure method according to claim 9, further comprising the step of transferring a pattern to the first region of the surface. 13. An exposure method for exposing an IC chip having large and small pattern sizes in the same layer, characterized in that the exposure is performed by using exposure apparatuses having different resolutions depending on the pattern size. . 14. The exposure method according to claim 12, wherein the main circuit portion, the dicing line portion and the bonding pad portion of the IC chip are exposed separately. 15. The exposure method according to claim 12, wherein the wafer exposed by the projection optical system is exposed again to a different pattern without developing the wafer.