JPS62125620A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS62125620A
JPS62125620A JP60266409A JP26640985A JPS62125620A JP S62125620 A JPS62125620 A JP S62125620A JP 60266409 A JP60266409 A JP 60266409A JP 26640985 A JP26640985 A JP 26640985A JP S62125620 A JPS62125620 A JP S62125620A
Authority
JP
Japan
Prior art keywords
pattern
exposure
patterns
photomask
exposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60266409A
Other languages
Japanese (ja)
Inventor
Tsuneaki Isozaki
磯崎 常明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60266409A priority Critical patent/JPS62125620A/en
Publication of JPS62125620A publication Critical patent/JPS62125620A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain the manufacturing method of a semiconductor device in which the size of a semiconductor chip is not limited by an exposed area of an exposure unit by providing the step of contraction-exposing dividing patterns of a photomask on a photoresist film formed on a semiconductor substrate while sequentially disposing adjacently to form the contracted patterns of a predetermined pattern on the photoresist film. CONSTITUTION:When a pattern 1 formed on one semiconductor chip is larger than an exposing range 2 of a contraction projecting exposure unit at a mask side, the pattern is split to form 2 photomasks 3A, 3B to be contained in the range 2. Predetermined portions on a photoresist film 6 formed on a silicon substrate 4 is repeatedly exposed with the photomask 3A to form exposure patterns 5A, and adjacent portions of the patterns 5A are repeatedly exposed with the photomask 3B to form exposure patterns 5B. Accordingly, the patterns 5A exposed by the photomask 3A and the exposure patterns 5B exposed by the photomask 3B are connected on the substrate 4 to form one pattern. Thus, many functions are provided on the chip, and a limit in size of the chip can be eliminated in the step of designing a semiconductor device.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device.

〔従来の技術] 半導体集積回路の集積度が向上するにつれて、内部パタ
ーンの微細化および半導体チップの大型化が進んでいる
[Prior Art] As the degree of integration of semiconductor integrated circuits improves, internal patterns become finer and semiconductor chips become larger.

半導体基板]−にポ1〜レジス1−の緻細パターンを形
成するためには解像力の高い露光装置がe要となる。現
在、最も多く使用されている露光装置はホI・マスク」
二のパターンを17′5に縮小投影してホトレジス1〜
膜」−に露光する縮小投影型露光装置である。
In order to form a fine pattern of resists 1 to 1 on a semiconductor substrate, an exposure device with high resolution is essential. Currently, the most commonly used exposure equipment is the photo mask.
The second pattern is reduced and projected onto 17'5, and photoresist 1~
This is a reduction projection type exposure device that exposes a film.

この縮小投影型露光装置は1回の露光で露光できる露光
面積が15mmX15+*m程度である。この為、露光
面積を大きくするためにレンスを大きくすると、トング
のゆがみが大きくなり露光パターンの位置精度が悪くな
る。従って縮小投影型露光装置の露光面積を現状よりも
大きく広げることは困難である。
This reduction projection type exposure apparatus has an exposure area of about 15 mm x 15+*m in one exposure. For this reason, if the lens is made larger in order to increase the exposure area, the distortion of the tongue becomes large and the positional accuracy of the exposure pattern deteriorates. Therefore, it is difficult to increase the exposure area of the reduction projection type exposure apparatus to a greater extent than it currently is.

1発明が解決しようとする問題点、l 半導体チップの大きさは現状でも一辺10+s+++以
上のものがあり、今後も大きくなっていく方向にある。
1. Problems to be Solved by the Invention: 1 The size of semiconductor chips is currently larger than 10+s+++ on a side, and the size of semiconductor chips is expected to continue to increase in the future.

従って、縮小投影型露光装置を使用して半導体装置を製
造する場合、従来のように1回の露光で1チツプ又は複
数チップ分の露光を行っている限り半導体チップの大き
さは露光面積に制限されてしまうという問題点がある。
Therefore, when manufacturing semiconductor devices using a reduction projection exposure system, the size of the semiconductor chip is limited to the exposed area, as long as one chip or multiple chips are exposed in one exposure as in the past. There is a problem that it can be done.

本発明の目的は、半導体チ・・ノブの大きさが露光装置
の露光面積に制限されることのない半導体装置の製造方
法を提イ1(することにある。
An object of the present invention is to provide a method for manufacturing a semiconductor device in which the size of a semiconductor chip is not limited by the exposure area of an exposure device.

1、問題点を解決するための手段〕 本発明の半導体装置の製造方法は、所定のパターンを複
数個に分割して各分割パターン毎にホ1〜マスクを形成
する工程と、半導体基板−1−に形成されたホ1〜レジ
ス1〜膜トに前記ホトマスクのパターンを順次隣接させ
ながら縮小露光し7て[)1f記所定のパターンの縮小
パターンを前記ポ)・ト・シスh膜に形成する工程とを
含むものである。
1. Means for Solving the Problems] The method for manufacturing a semiconductor device of the present invention includes the steps of dividing a predetermined pattern into a plurality of parts and forming a mask for each divided pattern; The pattern of the photomask is sequentially adjacent to the holes formed on the holes 1 through 1 through the resist 1 through the film 7 and reduced exposure is carried out to form a reduced pattern of the predetermined pattern described in 1f on the film 7. The method includes the step of:

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例に用いられるパターン、第2
図は第1図に示したパターンを2分割して形成した2枚
のポ)ヘマスクの平面]Aである。尚見易くする為にパ
ターン領域1Aには斜線を施しである。
Fig. 1 shows a pattern used in one embodiment of the present invention;
The figure shows a plane of two masks formed by dividing the pattern shown in FIG. 1 into two. Note that the pattern area 1A is shaded for ease of viewing.

第1図に示したように、1個の゛V導体チップに形成さ
れるパターン1か、縮小投影露光装置のマスク側の露光
範囲2よりも大きい場合、そのパターンを2分割し、露
光範囲2に収まる2枚のホトマスク3A、3Bを形成し
て露光に用いる7第3図(a、)、(b)は本発明の一
実施例を説明する為の製造工程順に示したシリコン基板
の平面図である。
As shown in FIG. 1, if the pattern 1 formed on one V-conductor chip is larger than the exposure range 2 on the mask side of the reduction projection exposure device, the pattern is divided into two and the exposure range 2 is Two photomasks 3A and 3B are formed and used for exposure. Figures 3 (a,) and 3 (b) are plan views of a silicon substrate shown in the order of manufacturing steps to explain an embodiment of the present invention. It is.

まず、第3図(a)に示すようにシリコン基板4」−に
形成されたホ1〜レジスト膜6−にの所定部分に、第2
図に示したホトマスク3Aを用いて繰り返し露光を行な
い露光パターン5Aを形成する。
First, as shown in FIG.
Exposure patterns 5A are formed by repeatedly performing exposure using the photomask 3A shown in the figure.

次に、第3図(1))に示すように、ホ1ヘマスク3B
を用いて露光パターン5Aの隣接した部分に繰り返し露
光を行ない露光パターン5 +3を形成する。
Next, as shown in FIG. 3 (1)), go to the mask 3B.
Adjacent portions of the exposure pattern 5A are repeatedly exposed using the exposure pattern 5A to form an exposure pattern 5+3.

このように露光することにより、ホトマスク3八で露光
された露光パターン5Δとホトマクス3Bで露光された
露光パターン5Bはシリコン基板4の一ヒてつながって
1つのパターンを形成する。
By exposing in this manner, the exposure pattern 5Δ exposed by the photomask 38 and the exposure pattern 5B exposed by the photomask 3B are connected to each other on the silicon substrate 4 to form one pattern.

これは第1図のパターン1をシリコン基板4の上に縮小
投影露光したものと同じになる。
This is the same as the pattern 1 shown in FIG. 1 which is subjected to reduction projection exposure onto the silicon substrate 4.

このように本実施例に、1:れば、1回の露光で1個の
半導体チップのパターンを露光するという、従来の方法
ではイζ可能であった縮小投影露光装置の最大露光範囲
よりも大きいパターンの露光が可能となる。
In this way, in this embodiment, if 1: is used, the maximum exposure range of the reduction projection exposure apparatus, which was possible with the conventional method of exposing one semiconductor chip pattern in one exposure, was set. Exposure of large patterns becomes possible.

なお、」二記実施例では、元のパターン1を2つに分割
して2枚のポ1−マスクを形成し、2度の露光に分けて
パターンを露光した場合について説明したが、パターン
の分割は2分割に限らず3分割以上でもよく、また分割
の大きさ及び形状は最大露光範囲に入る限り任意の大き
さでもよいことは言うまでもない、 1発明の効果〕 以上説明したように本発明は、1−)のパターンを2枚
以上のホトマスクを用いて露光することによって、寸法
の大きい半導体チップのパターンを形成することができ
るので、1つの半導体チ・ツブにより多くの機能を持た
せることかでき、また半導体装置の設計段階で、半導体
チ・・ノブの大きさに関する制限がなくなるという効果
かある。
In addition, in Example 2, the case was explained in which the original pattern 1 was divided into two to form two PO 1-masks, and the pattern was exposed in two exposures. It goes without saying that the division is not limited to two, but may be three or more, and the size and shape of the division may be any size as long as it falls within the maximum exposure range. 1. Effects of the Invention As explained above, the present invention By exposing the pattern 1-) using two or more photomasks, a large-sized semiconductor chip pattern can be formed, so one semiconductor chip can have more functions. This also has the effect of eliminating restrictions on the size of semiconductor chips at the design stage of semiconductor devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例に用いられるパターン、第2
図は第1図に示したパターンを2分割して形成した2枚
のホトマスクの平面図、第3図(a、)、(b)は本発
明の一実施例を説明する為の製造]二程順に示したシリ
コン基板の平面図である。 1・・パターン、2・・露光範囲、3A、3B・・・ポ
1へマスク、4・・・シリコン基板、5A、5B・・・
露光パターン、6・ポトレジス1〜膜。
Fig. 1 shows a pattern used in one embodiment of the present invention;
The figure is a plan view of two photomasks formed by dividing the pattern shown in FIG. FIG. 3 is a plan view of a silicon substrate shown in order of steps. 1...Pattern, 2...Exposure range, 3A, 3B...Mask to point 1, 4...Silicon substrate, 5A, 5B...
Exposure pattern, 6. Potregis 1-film.

Claims (1)

【特許請求の範囲】[Claims] 所定のパターンを複数個に分割して各分割パターン毎に
ホトマスクを形成する工程と、半導体基板上に形成され
たホトレジスト膜上に前記ホトマスクのパターンを順次
隣接させながら縮小露光して前記所定のパターンの縮小
パターンを前記ホトレジスト膜に形成する工程とを含む
ことを特徴とする半導体装置の製造方法。
a step of dividing a predetermined pattern into a plurality of parts and forming a photomask for each divided pattern; and reducing and exposing the photomask patterns while sequentially adjoining them on a photoresist film formed on a semiconductor substrate to form the predetermined pattern. A method for manufacturing a semiconductor device, comprising the step of forming a reduced pattern of on the photoresist film.
JP60266409A 1985-11-26 1985-11-26 Manufacture of semiconductor device Pending JPS62125620A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60266409A JPS62125620A (en) 1985-11-26 1985-11-26 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60266409A JPS62125620A (en) 1985-11-26 1985-11-26 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS62125620A true JPS62125620A (en) 1987-06-06

Family

ID=17430531

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60266409A Pending JPS62125620A (en) 1985-11-26 1985-11-26 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62125620A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5731131A (en) * 1990-08-24 1998-03-24 Canon Kabushiki Kaisha Method of manufacturing semiconductor devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5731131A (en) * 1990-08-24 1998-03-24 Canon Kabushiki Kaisha Method of manufacturing semiconductor devices

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