JPH065508A - Manufacture equipment of semiconductor - Google Patents

Manufacture equipment of semiconductor

Info

Publication number
JPH065508A
JPH065508A JP16518092A JP16518092A JPH065508A JP H065508 A JPH065508 A JP H065508A JP 16518092 A JP16518092 A JP 16518092A JP 16518092 A JP16518092 A JP 16518092A JP H065508 A JPH065508 A JP H065508A
Authority
JP
Japan
Prior art keywords
exposed
wafer
exposure
shot
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16518092A
Other languages
Japanese (ja)
Inventor
Makoto Kai
真 甲斐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP16518092A priority Critical patent/JPH065508A/en
Publication of JPH065508A publication Critical patent/JPH065508A/en
Pending legal-status Critical Current

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  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To improve the yield of a semiconductor element by a method wherein the whole area on a wafer having a part wherefrom a good element can be obtained is exposed by one shot and a part in the shot wherefrom the good element cannot be obtained is not exposed, when a plurality of patterns are exposed at once by one shot by a stepper or the like. CONSTITUTION:An exposure shield cover 109 is fitted to a part outside the limit on a wafer 105 on a stepper device inside of which a good element can be obtained. Thereby shot exposure is conducted for the whole part on the wafer 105 which needs to be exposed, and an area not to be exposed is prepared only in the outer peripheral end of the wafer 105 which is not desired to be exposed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体集積回路などのパ
ターンを半導体基板(以下ウェハーと称す)上の光感光
性有機膜へ露光し転写する半導体の製造装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing apparatus for exposing and transferring a pattern of a semiconductor integrated circuit or the like onto a photosensitive organic film on a semiconductor substrate (hereinafter referred to as a wafer).

【0002】[0002]

【従来の技術】半導体集積回路の製造は、近年ますます
高集積化、微細化が進んでおり、超LSIと呼ばれる高
密度記憶回路装置が作られている。超LSI回路パター
ンをウェハー上に形成するためには、微細パターンを正
確に形成する必要があり、このため、縮小投影露光装
置、いわゆるステッパーが用いられている。
2. Description of the Related Art In recent years, semiconductor integrated circuits have been highly integrated and miniaturized, and high-density memory circuit devices called VLSIs have been manufactured. In order to form a VLSI circuit pattern on a wafer, it is necessary to form a fine pattern accurately. Therefore, a reduction projection exposure apparatus, so-called stepper is used.

【0003】図3は従来のステッパーの一例の基本構成
図である。防震台108上にX−Y2方向に移動可能な
ステージ107が設置されている。光源101から発生
した光100はコンデンサレンズ102で平行光束とな
り、半導体集積回路パターンが実寸よりもn倍に拡大さ
れているレチクル103を通過する。レチクル像は縮小
投影レンズ104によって1/n、即ち実寸に縮小さ
れ、ウェハー105に結像露光される。
FIG. 3 is a basic configuration diagram of an example of a conventional stepper. A stage 107 that is movable in the X-Y2 directions is installed on the earthquake-proof table 108. The light 100 generated from the light source 101 becomes a parallel light flux by the condenser lens 102, and passes through the reticle 103 in which the semiconductor integrated circuit pattern is magnified n times the actual size. The reticle image is reduced to 1 / n, that is, an actual size by the reduction projection lens 104, and image-wise exposed on the wafer 105.

【0004】ところで縮小投影レンズ104を用いて一
度に露光可能な面積は通常5〜15mm角程度であり、
それに対し用いられるウェハーは直径100〜200m
m程度で、ウェハー全面に一度に露光することは不可能
である。そこで、1ショット分の領域を露光した後、ス
テージ107を移動し、他の領域を露光し、再びステー
ジの移動,露光をくりすことによってウェハー全面が露
光される(ステップ・アンド・リピート露光)。
By the way, the area which can be exposed at one time by using the reduction projection lens 104 is usually about 5 to 15 mm square,
The wafer used for this is 100-200 m in diameter
It is impossible to expose the entire surface of the wafer at a time in the range of m. Therefore, after exposing the area for one shot, the stage 107 is moved, the other area is exposed, and the entire surface of the wafer is exposed by repeating the movement and exposure of the stage (step-and-repeat exposure). .

【0005】また、半導体集積回路1個分のパターンの
面積が、1ショット分の露光領域に対して1/mの場
合、1ショットにつきm個分の半導体集積回路を収容し
たパターンのレチクルを使用し、ステッパーの露光回数
のショット数を減らす方法も用いられている。
When the area of the pattern for one semiconductor integrated circuit is 1 / m with respect to the exposure area for one shot, a reticle having a pattern containing m semiconductor integrated circuits for one shot is used. However, a method of reducing the number of shots of the exposure number of the stepper is also used.

【0006】[0006]

【発明が解決しようとする課題】この従来のステッパー
においては、1ショットについて1個の半導体集積回路
のパターンを露光する場合(以降「一面付け露光」と称
す)、半導体集積回路のとれる部分のみショットを打つ
とすれば、図2のウェハーの平面図に示すように、露光
部201のエリアのみに露光することになる。有効とな
る半導体集積回路を増やすために露光部203のエリア
に露光した場合、多面付け露光(図2は6面付けの例)
であるために露光部202にまで露光されてしまう。
In this conventional stepper, when a pattern of one semiconductor integrated circuit is exposed for one shot (hereinafter referred to as "single-sided exposure"), only a portion of the semiconductor integrated circuit which can be taken is shot. If, is hit, only the area of the exposure unit 201 is exposed as shown in the plan view of the wafer in FIG. When the area of the exposure unit 203 is exposed in order to increase the number of effective semiconductor integrated circuits, multiple-sided exposure (FIG. 2 shows an example of six-sided attachment)
Therefore, even the exposure unit 202 is exposed.

【0007】ウェハー外周端204にまで露光してある
場合、次の処理工程のエッチング工程において、最外周
端にパターニングされた部分はエッチングで異常が発生
し易いため、ショットを打つことを禁止されている。こ
のため、多面付け露光をする場合には、有効となる半導
体集積回路をとることができる露光部があるにもかかわ
らず、ショットを打てないという欠点があった。
When the wafer outer peripheral edge 204 is also exposed, in the etching process of the next processing step, the portion patterned at the outermost peripheral edge is likely to cause an abnormality in the etching, and therefore shots are prohibited. There is. For this reason, in the case of performing multiple exposure, there is a drawback in that shots cannot be shot even though there is an exposed portion capable of taking an effective semiconductor integrated circuit.

【0008】ウェハー外周部の良品素子がとれる限界ラ
イン205より外側の光感光性有機膜を除去するには光
感光性有機膜を塗布後、溶剤を用いているが、この光感
光性有機膜が次のエッチング処理においてエッチングの
反応に寄与する場合があるため、除去してしまうことも
問題となり、光感光性有機膜を残さなければならない。
In order to remove the photo-sensitive organic film outside the limit line 205 where the non-defective element on the outer periphery of the wafer can be taken, a solvent is used after applying the photo-sensitive organic film. Since it may contribute to the etching reaction in the next etching process, it also becomes a problem to remove it, and the photosensitive organic film must be left.

【0009】[0009]

【課題を解決するための手段】本発明のステッパーは、
ウェハー上の良品素子がとれる限界ラインより外側が露
光されない様に、ウェハー周縁上に露光遮蔽カバーを有
している。
The stepper of the present invention comprises:
An exposure shield cover is provided on the peripheral edge of the wafer so that the area outside the limit line on which the non-defective device on the wafer can be taken is not exposed.

【0010】[0010]

【実施例】次に本発明について図面を参照して説明す
る。
The present invention will be described below with reference to the drawings.

【0011】図1は本発明の一実施例の構成図である。
防震台108上にX−Y2方向に移動可能なステージ1
07が設置されている。光源101から発光した光10
0は、コンデンサレンズ102で平行光束となり、半導
体集積回路パターン実寸よりもn倍に拡大されているレ
チクル103を通過する。レチクル像は縮小投影レンズ
104によって1/n、即ち実寸に縮小され、ウェハー
105上に結像露光される。
FIG. 1 is a block diagram of an embodiment of the present invention.
Stage 1 that can move in the X-Y2 directions on the earthquake-proof table 108
07 is installed. Light 10 emitted from the light source 101
0 becomes a parallel light flux by the condenser lens 102 and passes through the reticle 103 which is enlarged by n times the actual size of the semiconductor integrated circuit pattern. The reticle image is reduced to 1 / n, that is, the actual size by the reduction projection lens 104, and image-wise exposed on the wafer 105.

【0012】ところで縮小投影レンズ104を用いて一
度に露光可能な面積は通常5〜15mm角であり、それ
に対し用いられるウェハーは直径100〜200mm程
度で、ウェハー全面に一度に露光することは不可能であ
る。そこで1ショット分の領域を露光した後、ステージ
107を移動し、他の領域を露光し、再びステージの移
動,露光を繰り返すことによってウェハー全面が露光さ
れる。
By the way, the area which can be exposed at one time using the reduction projection lens 104 is usually 5 to 15 mm square, and the wafer used for it has a diameter of about 100 to 200 mm, and it is impossible to expose the entire surface of the wafer at one time. Is. Therefore, after exposing the area for one shot, the stage 107 is moved, the other areas are exposed, and the movement and exposure of the stage are repeated again to expose the entire surface of the wafer.

【0013】露光遮蔽カバー109は、図2の良品素子
がとれる限界ライン205より外側のウェハー外周端2
04側に紫外光が当たらない様な形でつくられており、
ステージ107に露光時は固定されている。このため露
光部202および露光部203を含む位置に6面付けの
レチクル103によって露光を行った場合、露光部20
3の位置には半導体集積回路のパターニングを行うこと
ができ、かつ露光部203の位置の良品素子がとれる限
界ライン205より外側は露光されずにすむ。
The exposure shield cover 109 is a wafer outer peripheral edge 2 outside the limit line 205 where the non-defective element of FIG. 2 can be taken.
It is made so that the 04 side is not exposed to ultraviolet light,
The stage 107 is fixed during exposure. Therefore, when the reticle 103 with six impositions is used for exposure at a position including the exposure unit 202 and the exposure unit 203, the exposure unit 20
The semiconductor integrated circuit can be patterned at the position 3 and the outside of the limit line 205 where the non-defective element at the position of the exposure portion 203 can be taken is not exposed.

【0014】よって露光ショット領域206(6面付
け)の領域全てに露光を行っても、良品素子がとれる限
界ライン205より外側は露光されていないため光感光
性有機膜が残り、次工程でのエッチング処理を正常に行
うことが可能となる。
Therefore, even if the entire area of the exposure shot area 206 (6 impositions) is exposed, since the area outside the limit line 205 where the non-defective element can be taken is not exposed, the photo-sensitive organic film remains and the next step The etching process can be normally performed.

【0015】[0015]

【発明の効果】以上説明したように本発明は、半導体集
積回路の良品素子がとれる限界ラインより外側に、光感
光性有機膜が露光されないように露光遮蔽がカバーをと
りつけることにより、多面付け露光を行う場合には良品
素子がとれる領域全てに露光を行うことが可能となり、
かつ次工程のエッチング処理工程を安定して処理できる
効果がある。さらに、良品素子となる半導体集積回路の
個数が増すため、ウェハー1枚における半導体集積回路
の収率を上げる効果を有する。
As described above, according to the present invention, the exposure shield is attached to the outside of the limit line where a good element of the semiconductor integrated circuit can be taken so that the photosensitive organic film is not exposed. When performing, it becomes possible to perform exposure on all areas where good elements can be obtained,
Moreover, there is an effect that the next etching process can be stably performed. Furthermore, since the number of semiconductor integrated circuits that become non-defective elements increases, it has the effect of increasing the yield of semiconductor integrated circuits on one wafer.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の構成図である。FIG. 1 is a configuration diagram of an embodiment of the present invention.

【図2】多面付け露光のショットの打ち方を説明するウ
ェハーの平面図である。
FIG. 2 is a plan view of a wafer for explaining how to hit a shot in multiple-sided exposure.

【図3】従来装置の構成図である。FIG. 3 is a configuration diagram of a conventional device.

【符号の説明】 100 紫外光 101 光源 102 コンデンサレンズ 103 レチクル 104 縮小投影レンズ 105 ウェハー 106 ウェハー台 107 ステージ 108 防震台 109 露光遮蔽カバー 201 露光部 202 露光部 203 露光部 204 ウェハー外周端 205 良品素子がとれる限界ライン 206 露光ショット領域[Explanation of reference signs] 100 ultraviolet light 101 light source 102 condenser lens 103 reticle 104 reduction projection lens 105 wafer 106 wafer stage 107 stage 108 seismic isolation table 109 exposure shield cover 201 exposure section 202 exposure section 203 exposure section 204 wafer outer edge 205 Limitable line 206 Exposure shot area

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 紫外光によりレチクル上に形成されてい
るパターンを光感光性有機膜の塗布されたウェハー上に
投影露光を行う半導体製造装置において、ウェハーの最
外周部に露光されない部分を作るための露光遮蔽カバー
を設けたことを特徴とする半導体の製造装置。
1. In a semiconductor manufacturing apparatus for performing projection exposure of a pattern formed on a reticle by ultraviolet light onto a wafer coated with a photosensitive organic film, in order to form an unexposed portion on the outermost peripheral portion of the wafer. The semiconductor manufacturing apparatus, which is provided with the exposure shielding cover.
JP16518092A 1992-06-24 1992-06-24 Manufacture equipment of semiconductor Pending JPH065508A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16518092A JPH065508A (en) 1992-06-24 1992-06-24 Manufacture equipment of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16518092A JPH065508A (en) 1992-06-24 1992-06-24 Manufacture equipment of semiconductor

Publications (1)

Publication Number Publication Date
JPH065508A true JPH065508A (en) 1994-01-14

Family

ID=15807370

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16518092A Pending JPH065508A (en) 1992-06-24 1992-06-24 Manufacture equipment of semiconductor

Country Status (1)

Country Link
JP (1) JPH065508A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10214810A (en) * 1996-12-23 1998-08-11 Lsi Logic Corp Method of improving uniformity and flatness on edge-die and removing tungsten-stringers caused by cmp of wafer
KR100307566B1 (en) * 1998-08-05 2001-09-24 가네꼬 히사시 Charged beam drawing apparatus and method thereof
JP2005505147A (en) * 2001-10-09 2005-02-17 ウルトラテック インク Method and apparatus for mechanically masking a workpiece
JP2008258634A (en) * 2007-04-05 2008-10-23 Asml Netherlands Bv Lithography device and method for masking substrate

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10214810A (en) * 1996-12-23 1998-08-11 Lsi Logic Corp Method of improving uniformity and flatness on edge-die and removing tungsten-stringers caused by cmp of wafer
JP4620189B2 (en) * 1996-12-23 2011-01-26 エルエスアイ コーポレーション A novel method for improving uniformity and flatness on edge dies and removing tungsten stringers resulting from CMP of a wafer
KR100307566B1 (en) * 1998-08-05 2001-09-24 가네꼬 히사시 Charged beam drawing apparatus and method thereof
JP2005505147A (en) * 2001-10-09 2005-02-17 ウルトラテック インク Method and apparatus for mechanically masking a workpiece
JP2008258634A (en) * 2007-04-05 2008-10-23 Asml Netherlands Bv Lithography device and method for masking substrate

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Effective date: 19990928