JPH06181164A - Aligner and aligning method - Google Patents

Abstract

PURPOSE:To realize highest resolving power for each property of functional pattern by selecting different regions from a plurality of blocks and exposing each region a plurality of times onto a substrate using an optimal exposing system or illuminating system. CONSTITUTION:Logic IC region 13 and joint region 12 on a mask 3 are partially screened by means of a masking blade 4 thus projection exposing only a part of memory IC region 11 and the joint region 12 for a predetermined time onto a region 14 on a substrate. The memory IC region 11 and the joint region 12 on a mask 7 are then screened partially by means of the masking blade 4 thus projection exposing only a part of the logic IC region 13 and the joint region 12 for a predetermined time onto a region 15 on the substrate. The masking blade 4 is set such that the joint regions 12 are exposed while being overlapped partially. This method allows fine patterning of circuit in each block thus realizing advanced function.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exposure method using a reduction projection exposure apparatus used for forming fine patterns of various solid state elements.

[0002]

2. Description of the Related Art In order to improve the degree of integration and operation speed of solid-state elements such as LSIs, circuit patterns are becoming finer.
At present, a reduction projection exposure method which is excellent in mass productivity and resolution performance is widely used for forming these patterns. The resolution limit of this method is proportional to the exposure wavelength, and the numerical aperture (N
Since it is inversely proportional to A), the resolution has been improved by increasing the NA of the lens and shortening the wavelength of the exposure light. However, due to the limitations of lens design and manufacturing technology and the restrictions on materials suitable for short wavelength light, it has become increasingly difficult to improve resolution by increasing the NA and shortening the wavelength. Further, along with this, the depth of focus sharply decreases.

To solve this problem, the following various methods have been proposed.

First, a phase shift method has been proposed as a method for dramatically improving the resolution of the conventional projection exposure method.
In this method, since the phases of the adjacent aperture patterns are inverted, it is difficult to arrange the phase shifter for phase inversion when the patterns are complicated. Therefore, although it is suitable for a simple pattern such as a memory, it is not suitable for a complicated pattern such as a microprocessor. The phase shift method is discussed in, for example, Japanese Patent No. 1441789.

On the other hand, an annular illumination method has long been known as a method for improving the resolution of an optical system in a microscope or the like. Regarding the application of the annular illumination method to optical lithography, for example, JP-A-59-49514 or JP-A-61-61.
-91662.

[0006]

In recent years, with the development of LSIs, one LSI has not only a single function such as a memory, a microprocessor, and a logic, but also a function as a system combining these. Has come to be required.

A problem in manufacturing such a system LSI is that the optimum manufacturing process is different for each function. In particular, in the optical lithography process, it is desired to apply some optical method for improving the resolution and the depth of focus as described above. At this time, since the optimum method depends on the nature of the pattern arrangement and the required depth of focus, when the nature of the pattern arrangement and the step structure are different for each of the plurality of functional blocks, there is a problem of what exposure method should be used. Occurs.

Consider, for example, the case of transferring a pattern of a special-purpose memory having a memory area having a simple repeating pattern and a three-dimensional device structure, and a logic area including a complicated input / output circuit. For the memory area, high resolution and large depth of focus can be obtained by using the iterative phase shift method with high coherence illumination. On the other hand, it is difficult in terms of pattern layout to adopt this method for a logic LSI having a complicated wiring pattern. In this case, it is preferable to use an annular illumination method or the like, which has a relatively high degree of pattern freedom, although it is not expected that the resolution will be improved as much as the repetitive phase shift method.
However, when the annular illumination method is used, the resolution of the iterative phase shift method deteriorates. Therefore, in case of exposing such a mask pattern, if the phase shift method is applied to the memory area, the logic area becomes a normal mask exposure by normal illumination, while the annular illumination method is applied to the logic area. Then, the phase shift method cannot be applied to the memory area. That is, in any case, it is impossible to miniaturize both patterns at the same time to sufficiently reduce the chip area.

It is an object of the present invention to provide an exposure method capable of realizing the highest resolution according to the property of each functional pattern when projecting and exposing a plurality of different functional patterns on the same substrate. Further, as a result, an exposure method for realizing a more advanced system LSI is provided by miniaturizing the circuit pattern in each functional block such as a memory, a microprocessor, and a logic configuring the system LSI as much as possible. The purpose is to

On the other hand, the exposure area of the projection lens has increased along with the increase in the chip area of the LSI. However, because of the trade-off relationship between the numerical aperture and the exposure area in the design of the projection lens, it is difficult to achieve both resolution improvement and exposure area expansion. Therefore, gigabit class memory LS
When manufacturing I, it is expected that the exposure area of the projection lens will be insufficient. In order to solve this problem, it has been attempted to form one chip by combining multiple exposures. That is, one half of the chip is exposed with the first mask and then the other half is exposed with the second mask.
In this case, since the reticle needs to be replaced and the mask needs to be aligned, the time required for the exposure becomes twice as long as usual. Further, since the reticles are aligned independently, the alignment accuracy between the two masks is stipulated by the alignment accuracy of the three layers.

Another object of the present invention is to minimize an increase in wafer exposure processing time when an LSI having a specific circuit configuration is manufactured, even when the chip area exceeds the exposure area of an exposure apparatus. Another object of the present invention is to provide an exposure method that can achieve high alignment accuracy. Another object of the present invention is to provide an exposure method for realizing a gigabit class memory LSI.

Another object of the present invention is to expose a wafer in the case of avoiding the above contradiction by overlapping and exposing a plurality of masks in a repetitive phase shift mask because the pattern layout has a contradiction. An object of the present invention is to provide an exposure method capable of minimizing the increase in processing time and achieving high alignment accuracy.

[0013]

The above object is to form a circuit pattern for one LSI by projecting and exposing a pattern consisting of a plurality of blocks on one mask onto a substrate through a lens. This is achieved by selecting different regions from the plurality of blocks and exposing each of the regions on the substrate a plurality of times by using an optimal exposure system or illumination system.

More specifically, the above-mentioned object is, when exposing an LSI including a memory area and a logic area, as an optimal exposure method or illumination method for each area, for example, a repetitive phase shift mask for the memory area or This is achieved by applying the quadrupole illumination method and applying the annular illumination method or normal illumination to the logic region.

Here, in order to select different areas from the plurality of blocks, a masking blade may be used to shield the areas other than the selected blocks from light. Further, a second mask may be placed at a position conjugate with the mask to block light in areas other than necessary areas. In addition, the stage on which the mask and the substrate are mounted may be moved or fixed depending on the purpose between the exposures of the blocks.

[0016]

By selecting only a specific area on the mask by using the masking blade, pattern areas having different graphic features are separately exposed in terms of time and space. Does not affect other areas. Further, if the second mask is installed at a position conjugate with the mask, it is possible to select a region having an arbitrarily complicated shape which cannot be achieved by the masking blade. Furthermore, if the second mask is composed of a liquid crystal panel, the time required for selecting a region can be significantly reduced.

Further, if the substrate is not moved through the exposure for these different areas, the pattern positional deviation between the areas can be made substantially zero.

On the other hand, even when the substrate is moved, the positional accuracy of the above-mentioned area projected on the substrate is mainly determined by the positional accuracy of the wafer stage. It is possible to greatly improve the alignment accuracy. Further, the processing time can be shortened because the reticle exchange and the matching process are unnecessary.

[0019]

【Example】

 Example 1 One example of the present invention will be described with reference to the drawings.

FIG. 8 shows a schematic diagram of the exposure apparatus used in this embodiment. The light emitted from the secondary light source surface 1 of the illumination optical system is
It is condensed by the condenser lens 2 in the illumination optical system to illuminate the mask 3. The mask 3 forms an image near the surface of the wafer substrate 6 coated with the resist by the projection lens 5. The masking blade 4 defines an illuminated area on the mask by blocking a part of the illumination light. Here, in FIG. 8, only one masking blade 4 is shown immediately above the mask for the sake of simplicity. However, in practice, it is placed on a plane conjugate with the mask in the illumination optical system, and four shield plates are combined. By doing so, it is possible to define an arbitrary rectangular illumination area. Further, by using five or more or a shading plate having an arbitrary shape, it is possible to define an illumination area having a more complicated shape. The exposure light is KrF excimer ray.
The projection lens used had an NA (numerical aperture) of 0.45.

An outline of the mask used in this example is shown in FIG. The mask shown in FIG. 2 includes a memory IC area 11, an input / output logic IC area 12, and a connection area 1 between the areas.
It consists of three. Here, the memory IC area is mainly composed of a periodic wiring pattern, and the minimum dimension is 0.18.
μm (converted value on wafer). A repetitive phase shift mask is applied to this region. On the other hand, the logic IC area and the connection area are designed using the 0.25 μm rule and the 0.3 μm rule, respectively, and the phase shift method is not applied.

Next, the above-mentioned mask was exposed on the wafer using the above-mentioned exposure apparatus according to the method schematically shown in FIG. The resist used was a chemically amplified negative type.

First, the masking blade 4 shields a part of the logic IC area 13 and the connection area 12 on the mask 3 from light, and leaves only a part of the memory IC area 11 and the connection area 12 in the area 14 on the substrate. Projection exposure was performed for a predetermined exposure time (FIG. 1A). At this time, an aperture as shown in FIG. 3A was placed on the secondary light source surface in the illumination optical system for illuminating the mask, and the spatial coherence factor σ of the illumination system was set to 0.4. Note that the scale in FIG. 3 is standardized coordinates in which the radius of the region conjugate with the pupil aperture of the projection lens on the secondary light source surface is 1. Although the masking blade 4 is shown right above the mask in FIG. 1 for simplicity, it is actually placed on the plane conjugate with the mask in the illumination optical system as in FIG.

Next, a part of the memory IC area 11 and the connection area 12 on the mask is shielded from light by the masking blade 4, and only a part of the logic IC area 13 and the connection area 12 is formed on the area 15 on the substrate. Projection exposure was performed for a predetermined exposure time (FIG. 1 (b)). At this time, the diaphragm of the secondary light source is set to
An annular illumination method was applied by changing to an annular diaphragm as shown in (b). Further, when the masking blade 4 is set, the portions of the connection region 12 that are respectively exposed in the two exposures are made to overlap each other.

After the exposure, predetermined heat treatment and development were performed to form a resist pattern. As a result, 25 mm
0.5 on the entire surface of a chip having a square shape with corners
It was possible to form a 0.18 μm pattern for the memory region and a 0.25 μm pattern for the logic region on the substrate having a ground step difference of μm. In the connection area, the line width of the double-exposed portion in the double exposure was as thick as 0.40 μm, but the final LSI
There was no problem in terms of electrical characteristics.

The exposure wavelength of the exposure apparatus, NA, the type of resist, the design rule of the mask, the shape of the illumination diaphragm, etc. are not limited to those shown in this embodiment. If necessary, the edge enhancement type (auxiliary pattern type) phase shift method may be applied to all the mask regions including the logic IC region and the connection region.

When either the memory area or the logic area is a fine isolated exposure pattern such as a through hole, the multiple image forming exposure method (so-called FLEX method) is applied to the area including the pattern. May be. In particular, when a region including an isolated pattern spreads over a step, the entire region may be collectively exposed and then the focal position may be changed only for the above region to selectively expose the region. That is, the plurality of exposure areas may not only overlap each other, but one exposure area may completely include another exposure area. further,
Needless to say, when there is a large step between a plurality of regions and the optimum focus position for each region is different, it is desirable to perform exposure for each region under the optimum focus condition for each region.

When a plurality of LSI chips are exposed on the substrate, the memory area is first exposed to all of the plurality of LSI chips in accordance with the usual step-and-repeat exposure procedure, and then the plurality of LSI chips are similarly exposed. The logic area may be exposed to all of the LSI chips. In this case, a positional deviation of about a stage position accuracy error occurs between the memory area and the logic area, but there is practically no problem. In this case, since it is not necessary to change the setting of the masking blade for each exposure field, the throughput is significantly improved. Therefore, it is preferable to use this method in an actual production line.

Regarding the circuit block configuration on the mask,
It goes without saying that various combinations other than those shown in this embodiment can be considered. The present invention can be applied to these various circuit block configurations without departing from the spirit of the present embodiment. For example, in the case of exposing a microprocessor including a memory area, a logical operation area, a control area, an input / output area, a connection area, etc., an optimum method for each of the above areas or a combination of some Exposure can be performed.

Further, from the different functional blocks on the same mask, only the blocks necessary for the purpose of the LSI may be selected and exposed. For example, in this embodiment, two input / output blocks A and B for different input / output interfaces are prepared on the same mask, and only one of them is selected as an input / output area on the wafer as needed. Can be transcribed. As a result, two types of LSIs can be formed on one wafer without changing the mask.

Embodiment 2 Another embodiment of the present invention will be described with reference to the drawings.

The mask of the LSI used in this embodiment is shown in FIG. The mask of FIG. 4 includes a memory mat area 21, an x-direction connection area 22, a y-direction connection area 23, an x-direction end (left) area 24, an x-direction end (right) area 25, and a y-direction end (top) area 26. It consists of a y-direction end (lower) region 27. Each area is arranged on the mask via a light shielding area for a predetermined distance. The x (y) direction connection area is a peripheral circuit that connects two memory mat areas in the x (y) direction. The x (y) direction end region is a peripheral circuit arranged at the end of the memory mat and also has an input / output function. Here, the direct peripheral circuits in the memory mat region, each connection region, and the termination region are mainly periodic wiring patterns (minimum dimension is 0.18 μm), and a repetitive phase shift mask is applied. Each region has a transition region of constant width around it. The transition region is a region that may be double-exposed when two predetermined regions are exposed so as to overlap each other, and the width thereof is set to approximately the same as the setting accuracy of the masking blade.

The above mask was exposed on a substrate coated with a resist (negative chemical amplification type) using a KrF excimer laser stepper having an NA (numerical aperture) of 0.45 as follows. The exposure process on the substrate is schematically shown in FIG.

First, a portion other than the memory mat area 21 on the mask was shielded from light by a masking blade, and only the memory mat area 21 was projected and exposed onto a predetermined area A on the substrate for a predetermined exposure time. Next, the substrate stage is x,
Then, the memory mat region 21 was exposed to the predetermined regions B, C, D, E, F, G, and H on the substrate in order by moving in the y and y directions (FIG. 5A).

Next, a portion other than the x-direction connection region 22 on the mask was shielded by a masking blade, and only the x-direction connection region 22 was projected and exposed on a predetermined region AB on the substrate for a predetermined exposure time. At this time, the transition area in the memory mat area transferred to the areas A and B and the transition area in the x-direction connection area transferred to the area AB were made to overlap each other.
Further, the substrate stage is moved in the x and y directions, and x
The direction connection area 22 is defined as the areas BC, CD, EF, F on the substrate.
G and GH were sequentially exposed (FIG. 5B).

Similarly, the y-direction connection area 23 is exposed on the areas AE, BF, CG and DH on the substrate (see FIG. 5).
(C)), the x-direction end area (left) is set to areas XA and XE,
Further, the x-direction end region (right) is exposed to the regions DX and HX (FIG. 5D), and the y-direction end region (upper) is changed to the regions YA, YB, YC, and YD, and the y-direction end region ( The lower part is exposed to areas EY, FY, GY, and HY, respectively (FIG. 5).
(E)).

The exposure positions of all the above-mentioned areas are set so that the transition areas of all the areas adjacent to each other overlap each other.
Predetermined.

After the exposure, a predetermined post-exposure heat treatment and development were performed to form a resist pattern. As a result, 25m
On the entire surface of a chip having a rectangular shape of mx 50 mm, 0.18 is formed on a substrate having a step difference of 0.5 μm.
It was possible to form a μm pattern. The line width of the overlapped part of each area is 0.22 μm.
Although it was thicker, there was no problem in the electrical characteristics of the LSI. According to this embodiment, it is possible to manufacture an LSI having a chip area far exceeding the exposure field of a normal exposure apparatus. For example, a memory LSI equivalent to a 4 Gbit DRAM can be manufactured by using a lens having an exposure area similar to that of a conventional one and a 6-inch reticle. In addition,
When a plurality of LSI chips are exposed on the substrate, the memory mat area is exposed to all of the LSI chips, and then the connection area and the termination area are exposed to all of the LSI chips. May be performed respectively.
Further, the input / output function may be provided in each connection area instead of the termination area.

Example 3 The repetitive phase shift method was applied to a memory LSI having a complicated input / output circuit. However, the arrangement of the phase shifter inevitably caused a contradiction, and an unnecessary pattern (unexposed pattern) was formed at the edge of the phase shifter. (Corresponding to a section) has occurred. Therefore, in order to erase only the unnecessary edge pattern portion by exposing it separately, a mask as shown in FIG. 6 was produced. The mask shown in FIG. 6 has a main pattern region 31 by the phase shift method while keeping the shifter arrangement inconsistent, and an auxiliary pattern region 32 including an auxiliary pattern for exposing only a portion corresponding to an unnecessary edge portion.
It consists of The above two areas are arranged via a light shielding area for a predetermined distance.

The above mask was exposed on a substrate using a KrF excimer laser stepper having an NA (numerical aperture) of 0.45 as follows. The resist used is a chemically amplified negative resist. The outline of the exposure method is schematically shown in FIG.

First, the area other than the main pattern area 31 on the mask is shielded by the masking blade 4, and only the main pattern 31 is projected and exposed onto the area 33 on the substrate for a predetermined exposure time (FIG. 7A). . At this time, a stop as shown in FIG. 3a was placed on the secondary light source surface in the illumination optical system for illuminating the mask, and the spatial coherence factor σ of the illumination system was set to 0.4. Next, the masking blade 4 shields the area other than the auxiliary pattern area 32 on the mask from light and moves the substrate stage to move the auxiliary pattern area 32.
The area 33 was made to coincide with the position where the image of 3 was obtained. Then, only the auxiliary pattern 32 was projected and exposed on the substrate area 33 so as to overlap with the exposure of the main pattern (FIG. 7B). At this time, the stop of the illumination system was changed to set the spatial coherence factor σ to 0.6, but this change is not necessarily essential.

After the exposure, a predetermined post-exposure heat treatment and development were performed to form a resist pattern. As a result, 25m
On the entire surface of the chip having a rectangular shape of mx12 mm, 0.20
It was possible to form a μm pattern.

When it is necessary to narrow the exposure spot for erasing unnecessary edges as small as possible, the edge enhancement type phase shift method or the pupil filtering method may be applied to the auxiliary pattern area. Further, the method shown in the present embodiment is not limited to the unnecessary edge erasing of the repetitive phase shift method, but also the unnecessary edge erasure in the shift method in which the shifter edge utilization is phased, etc. It can be applied in any case.

Example 4 When the mask of Example 3 was sequentially exposed on the wafer by the step-and-repeat method, the masking blade was used to shield each region from light in the following manner.

Main pattern area 3 on the mask on the wafer
Step-and-repeat exposure was performed using the distance corresponding to the distance between the opposing patterns of 1 and the auxiliary pattern area 32 as the stage movement pitch. As a result, the main pattern area 31 and the auxiliary pattern area 32 were exposed in an overlapping manner by two successive exposures, and the same effect as in Example 3 was obtained. According to the present embodiment, the number of exposures may be smaller than that in the third embodiment, and thus the throughput is improved. However,
At the outermost edge of the wafer, there was a portion where the main pattern area 31 and the auxiliary pattern area 32 were not overlapped and exposed. In this embodiment, the edge enhancement type phase shift method is applied to the auxiliary pattern area in order to narrow the exposure spot for erasing the unnecessary edges as small as possible.

Embodiment 5 FIG. 9 shows an embodiment of the projection exposure apparatus according to the present invention. The illumination optical system 41 has a function of setting the second mask 42 at a position substantially conjugate with the mask surface and an alignment function 43 of aligning the second mask with the first mask.

When the exposure apparatus according to this embodiment is used, the pattern printed on the wafer is a superposition of the first mask and the second mask. Therefore, for example, when it is desired to selectively expose only a region on the first mask, a second mask having an opening only at a portion corresponding to the region may be used. The exposure area can be changed by changing the second mask. By using this apparatus, not only can an exposure region having a complicated shape, which is difficult for a masking blade, to be set, but also various situations where two masks need to be overlapped can be dealt with.

The resolution and alignment accuracy of the optical image formed on the wafer surface with respect to the pattern on the second mask may be lower than the resolution and alignment accuracy with respect to the pattern on the first mask. In addition, the magnification relationship between the second mask and the first mask is not particularly limited.

Embodiment 6 FIG. 10 shows another embodiment of the projection exposure apparatus according to the present invention. In this embodiment, the second mask in the fifth embodiment is replaced with the liquid crystal panel 44. Pattern input device 4
By inputting a desired pattern from No. 5, a pattern for blocking exposure light is formed on the liquid crystal panel.
The same effect as can be obtained. In the present embodiment, the pattern on the second mask can be changed much more rapidly than in the fifth embodiment, and thus high throughput can be expected.

[0050]

As described above, according to the present invention, when projecting and exposing a mask pattern of one LSI including a plurality of functional blocks onto a substrate through a lens, different areas are selected from the plurality of functional block areas. Then, one LSI is manufactured by exposing the substrate a plurality of times by using the optimum exposure method according to the nature of the pattern in the selected area, and thus the highest resolution is obtained for each functional block. Can be realized. As a result, in a system LSI including functional blocks such as a memory, a microprocessor, and a logic, it is possible to realize a more advanced function by making the circuit pattern in each block as fine as possible. In addition, L having a large chip area that exceeds the exposure area of the exposure apparatus with a minimum increase in wafer exposure processing time and sufficient pattern accuracy.
It is possible to fabricate SI and avoid pattern layout in a repetitive phase shift mask.

[0051]

[Brief description of drawings]

FIG. 1 is a schematic view showing an outline of an exposure method according to an embodiment of the present invention.

FIG. 2 is a schematic view showing a configuration of a mask used in one embodiment of the present invention.

FIG. 3 is a schematic view showing an illumination diaphragm used in one embodiment of the present invention.

FIG. 4 is a schematic diagram showing a configuration of a mask used in another embodiment of the present invention.

FIG. 5 is a schematic diagram showing an exposure process of another embodiment of the present invention.

FIG. 6 is a schematic view showing a configuration of a mask used in another embodiment of the present invention.

FIG. 7 is a schematic view showing an outline of an exposure method of another embodiment of the present invention.

FIG. 8 is a schematic diagram showing a configuration of an exposure apparatus used in one embodiment of the present invention.

FIG. 9 is a schematic view showing the outline of an exposure apparatus according to another embodiment of the present invention.

FIG. 10 is a schematic view showing the outline of an exposure apparatus according to another embodiment of the present invention.

[Explanation of symbols]

1 ... Secondary light source surface, 2 ... Condenser lens, 3 ... Mask, 4 ... Masking blade, 5 ... Projection lens, 6 ... Wafer substrate, 11 ... Memory IC area, 12 ... Connection area,
13 ... Logic IC area, 14 ... Area A, 15 ... Area B, 21 ... Memory mat area, 22 ... X direction connection area, 23 ... Y direction connection area, 24 ... X direction end area (left), 25 ... X direction End region region (right), 26 ... y direction end region (top), 27 ... y direction end region region (bottom),
31 ... Main pattern area, 32 ... Auxiliary pattern area, 41
... illumination optical system, 42 ... second mask, 43 ... alignment function, 44 ... liquid crystal panel, 45 ... pattern input device.

Claims (8)

[Claims] 1. When forming a circuit pattern for one layer of one LSI by projecting and exposing a pattern on the mask onto a substrate through a lens, the mask includes a plurality of blocks, and the plurality of blocks. An exposure method, wherein different regions are selected from the above, and each of the regions is exposed a plurality of times on the substrate by selectively using an optimal exposure system or illumination system. 2. The exposure method according to claim 1, wherein the method of selecting different areas from the plurality of blocks is a method of shielding the areas other than the selected blocks with a masking blade. 3. The method of selecting different regions from the plurality of blocks is performed by setting a second mask at a position conjugate with the mask.
The exposure method described. 4. The exposure method according to claim 1, wherein the relative positional relationship between the mask and the substrate is fixed with respect to a direction perpendicular to the optical axis through the plurality of exposures. 5. The exposure method according to claim 1, wherein the relative positional relationship between the mask and the substrate is changed with respect to a direction perpendicular or parallel to the optical axis through the plurality of exposures. 6. The plurality of blocks include a memory region and a logic region, a repetitive phase shift mask or a quadrupole illumination method is applied to the memory region, and an annular illumination is applied to the logic region. Method or the normal illumination method is applied, The exposure method of Claim 1 characterized by the above-mentioned. 7. When projecting and exposing a pattern on a mask onto a substrate sequentially through a lens using a step-and-repeat method, the mask includes a plurality of blocks, and the plurality of blocks are located at the same chip position on a wafer. An exposure method characterized in that a step-and-repeat movement pitch is set so as to be overlaid and exposed. 8. An exposure apparatus for projecting and exposing a pattern on a first mask onto a substrate through a lens, the function of installing a second mask at a position conjugate with the first mask, and An exposure apparatus having a function of aligning a second mask with a first mask.