JPS593924A - Positioning of wafer and substrate having pattern to be transferred - Google Patents

Abstract

PURPOSE:To improve the yield of chips, by a method wherein blank regions where no pattern is formed are provided at positions on a substrate and a wafer which correspond to each other, and alignment is effected in accordance with the blank regions. CONSTITUTION:Separately from monitor chips 13, 14, 15 with special patterns drawn thereon which are provided in the center, blank chips (blank regions) 17, 18 are substantially symmetrically provided in the peripheral portions of a mask 11 and a wafer 12, thereby to make it easy to observe a figure representing the contour of each of chips 16 existing around the blank chips when the mask 11 is overlaid on the wafer 12. First, the monitor chips 13, 14, 15 are aligned, and then, the figures of the chips in the vicinities of the blank chips 17, 18 are overlaid one upon another. If the blank chips 17, 18 are provided near portions 17', 18' which are removed as unnecessary portions when the wafer 12 is cut into chips 16, losses are reduced, and the manufacture becomes economical.

Description

Detailed Description of the Invention fal Technical Field of the Invention The present invention is an effective method for forming circuits using both an alignment system that exposes one shot at a time and a batch exposure system using a stepper that draws high-density integrated circuits on a wafer. Regarding alignment methods.

(b) Background of the Technology - With the development of microfabrication technology, MO3Lsr dynamic RAM is an example of a semiconductor device that is ahead in integration technology. The 64, which is currently in the commercialization stage, is equipped with approximately 150,000 dynamic RAM elements.

Furthermore, in the field of VLSI, there is an increasing demand for microfabrication technology with a gate width of 1.2 to 1.5 .mu.m (D gate width).Therefore, there is a demand for improvements in device circuits, miniaturization in one dimension, and larger chips.

In particular, microfabrication technology cannot be adequately supported by conventional photolithography (light exposure) technology, so high-precision 1:1 equal-size projection aligners, exposure equipment using deep ultraviolet light sources, miniature projection aligners, etc. are being used. It will be done. In either method, chip alignment is an important issue in order to transfer a fine pattern precisely drawn on a mask or reticle onto a wafer.

+11. ) Problems with Conventional Technology Reduction projection exposure equipment usually performs step-and-repeat processing of the pattern on the reticle at a reduction ratio of 10:1.
If a pattern with a chip size of, for example, 5 x 5 m/m is projected and exposed one shot at a time on a wafer of 1°Oφ using the wafer and repeat method, approximately 300 exposures (France) are required.

Alignment is performed for each chip, and even if the time required for this and the exposure time are estimated to be the minimum, 0.4 sec is required, and the time required for one wafer reaches 300 sec. A simple calculation of the sloop of 7 sheets is 12 sheets/hour.

Since the quality of alignment is related to accuracy and time, this method is optimal for alignments that require high precision.
For patterning, which does not require much precision, a mixed exposure method using a 1:1 contact aligner or a projection aligner that forms an image at the same magnification is used.

For example, 5 types of reticles are used to project a 5-layer precision pattern onto a wafer to form a precision image chip, and then a contact aligner or projection aligner is used to draw a desired pattern on this chip. Repeated transfer to Chinopuhi using the mask of 1c
Forms a high-density fine pattern that requires multiple layers.

In such a high-density integrated circuit, if 1c does not work or if a sufficient characteristic 1↓ is not produced, it is very difficult to investigate the cause of the failure.

For this reason, it is common practice to provide several monitor chips on the mask and wafer to ensure inter-process checking.

A specific example is shown in FIG. In the figure, 1 is a mask, 2
3.4.5 represents a wafer, 3.4.5 represents a monitor, and 56 represents a chip. At the beginning of exposure, the pattern of one or two layers is not so complicated and alignment is easy by visual inspection, but as the third and fourth layers are transferred in sequence, the fine pattern becomes convergent.

The alignment becomes circular.

Therefore, the monitor chip 3 is placed between the chips 6 as shown in the figure.
4.5 is inserted into the mask 1 and the wafer 2-hi, and the pattern of the monitor 1,000 knobs 3.4.5 is overlapped to facilitate alignment.

A special pattern image is drawn on this monitor chip 3, 4, 5 to facilitate one position alignment, but as the number of layers increases, fine patterns are sequentially transferred to the chip 6, and the center part is made by aligning the monitor chip 6. Although alignment is possible, it becomes difficult to overlay the chips 6, especially in the peripheral area, which causes pattern positional deviation and reduces the yield of the chips 6.

(d) Purpose of the Invention In view of the above-mentioned drawbacks, the present invention proposes an alignment method in which a blank chip is provided at the periphery of a mask and a wafer when transferring a built-up circuit pattern onto a wafer (J4 L, chip alignment method). The purpose is to improve yield.

tel Structure of the Invention According to the present invention, the above-mentioned object is achieved by providing empty areas where no pattern is formed at corresponding positions of a substrate having a pattern to be transferred and a wafer, and performing alignment based on the empty areas.

(fl　Embodiments of the invention Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a top view showing a blank chip for alignment provided on the periphery of a wafer and manifold according to an embodiment of the present invention.

FIG. 3 is an enlarged view of the vicinity of the blank thousand knob shown in FIG. 2. The monitor 13.14.15 with a special pattern drawn in the center is 'Al+ (fixed with mask 11).
Blank chips (blank areas) 17 and 18 as shown in the figure are provided on the periphery of the wafer 12 at substantially symmetrical positions.

Blank chips 17 and 18 are formed by skipping shots to form a blank area when the image on the reticle is scanned one by one, and is formed by the normal process of 1 JTI by giving position designation to the aligner control system. Ru.

By providing the blank chips 17 and 18, when superimposing the mask 11 on the wafer 12, the contour figures of the chips 16 interposed around the wafer 12 can be easily seen, thereby improving the alignment accuracy. First of all, monitor chip 13 in the center
．． 14.15 to align blank chip 17
．． The positioning is performed by overlapping the figures of 1,000 knobs around 18, making the positioning easier than in the past.

As mentioned above, in order to create high-density devices, usually about 10 reticles or masks are stacked on a wafer. This overlay accuracy is a strict requirement, and when using this precision beam lithography apparatus, by improving the alignment accuracy, more precise alignment of fine patterns on the chip 16 becomes possible.

Blank chips 1.7.18 are each chip 1 of wafer 12
Part 1 that is removed as unnecessary part when cut every 6
If they are provided near 7' and 18', the loss will be reduced and it will be economical.

(a) Effects of the Invention As explained in detail above, by providing the alignment blank part of the present invention, the alignment accuracy of overlapping the mask on the wafer is improved and simplified compared to the conventional method, and moreover, it is easier than the conventional manufacturing method. A blank part is formed in the process,
It has an excellent economical effect of improving the yield of chips.

[Brief explanation of the drawing]

FIG. 1 is a top view showing a conventional monitor chip for aligning a mask on a wafer and its position. FIG. 2 is a top view showing an alignment blank chip (blank area) provided around the wafer and mask according to an embodiment of the present invention. FIG. 3 is an enlarged view of the blank chip shown in FIG. 2. In the figure, 11 is a mask, and 12 is a wafer. 13.14.15 is monitor chip, 16 is chip, 1
7.18 indicates a blank chip. Figure 1 and half 7

Claims (1)

[Claims] A method for aligning a substrate having a pattern to be transferred and a wafer, characterized in that an empty area where no pattern is formed is provided at corresponding positions on the substrate and the wafer having the pattern to be transferred, and alignment is performed based on the empty area.