CN117577631A - Three-dimensional integrated circuit device and method of manufacturing the same - Google Patents

Abstract

The present disclosure provides a method of generating a dummy pad pattern. A method of manufacturing a three-dimensional integrated circuit device according to an embodiment of the present disclosure includes: receiving a design layout including a device region disposed in a scribe line region, identifying a center portion of the scribe line region surrounding the device region and an edge portion surrounding the center portion, dividing the edge portion into a plurality of rectangular partitions; the method includes superimposing a dummy pattern on each of a plurality of rectangular partitions to obtain an edge dummy pattern, superimposing the dummy pattern on a center portion to obtain a center dummy pattern, engraving a portion of the dummy pattern corresponding to a device region from the center dummy pattern to obtain a net center dummy pattern, generating a scribe line dummy pattern based on the edge dummy pattern and the net center dummy pattern, and manufacturing a first photomask including the scribe line dummy pattern. Embodiments of the present invention also provide a three-dimensional integrated circuit device.

Description

Three-dimensional integrated circuit device and method of manufacturing the same

Technical Field

Embodiments of the invention relate to three-dimensional integrated circuit devices and methods of manufacturing the same.

Background

As three-dimensional (3D) Integrated Circuit (IC) packages have become more popular in the semiconductor industry, efficient ways of performing wafer-to-wafer (WoW) bonding have been explored. The WoW bonding technique includes implementing a bonding layer on different IC dies. Each bonding layer includes a metal feature embedded in a dielectric layer. For the bonding layer used for WoW bonding, the surfaces of the dielectric layers and the metal features of the different bonding layers should be aligned. When the metal parts of the two bonding layers are misaligned, the bond may be compromised.

Disclosure of Invention

Some embodiments of the present invention provide a three-dimensional integrated circuit (3 DIC) device comprising: a first device comprising a first layer comprising a first layout and a first scribe area; and a second device comprising a second layer comprising a second layout and a second scribe area, wherein the first layer is bonded to the second layer, wherein the first layout is a mirror image of the second layout, wherein the first scribe area comprises a first plurality of dummy features arranged symmetrically with respect to a center of the first scribe area.

Further embodiments of the present invention provide a method of fabricating a three-dimensional integrated circuit device, the method comprising: receiving a design layout including a device region disposed in the scribe line region; identifying a center portion of the scribe line region surrounding the device region and an edge portion surrounding the center portion; dividing the edge portion into a plurality of rectangular partitions; superimposing a dummy pattern on each of the plurality of rectangular partitions to obtain an edge dummy pattern; superimposing a dummy pattern on the center portion to obtain a center dummy pattern; engraving a portion of the dummy pattern corresponding to the device region from the center dummy pattern to obtain a net center dummy pattern; generating a scribe line dummy pattern based on the edge dummy pattern and the net center dummy pattern; and fabricating a first photomask including the scribe line dummy pattern.

Still further embodiments of the present invention provide a method of fabricating a three-dimensional integrated circuit device, the method comprising: receiving a design layout, the design layout including a device region disposed in the scribe line region; dividing the scribing region into a center portion and an edge portion around the center portion; dividing the edge portion into a first partition, a second partition, a third partition and a fourth partition; receiving a dummy pattern; identifying a first centroid of the dummy pattern, a second centroid of the first partition, a third centroid of the second partition, a fourth centroid of the third partition, a fifth centroid of the fourth partition, and a sixth centroid of the center portion; superimposing the pseudo pattern on the first partition such that the second centroid overlaps the first centroid to obtain a first pattern; superimposing the pseudo pattern on the second partition such that the third centroid overlaps the first centroid to obtain a second pattern; superimposing the pseudo pattern on the third partition such that the fourth centroid overlaps the first centroid to obtain a third pattern; superimposing the pseudo pattern on the fourth partition such that the fifth centroid overlaps the first centroid to obtain a fourth pattern; superimposing the dummy pattern on the central portion such that the sixth centroid overlaps the first centroid to obtain a fifth pattern; removing a first portion of the dummy pattern corresponding to the device region from the fifth pattern to obtain a sixth pattern; and generating a dummy pad pattern design based on the first pattern, the second pattern, the third pattern, the fourth pattern, and the sixth pattern; and manufacturing a first photomask including the dummy pad pattern design.

Drawings

The disclosure is best understood from the following detailed description when read in connection with the accompanying drawing figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a partial cross-sectional view of a top die and a bottom die bonded together by a bonding layer according to one or more aspects of the present disclosure.

Fig. 2-8 illustrate operations of designing wafer level dummy pad patterns for scribe areas according to one or more aspects of the present disclosure.

Fig. 9 is a flowchart illustrating an exemplary embodiment of a method of designing a wafer level dummy pad pattern for scribe areas in accordance with one or more aspects of the present disclosure.

Fig. 10-28 illustrate operations of performing the method of fig. 9 for various design layouts in accordance with one or more aspects of the present disclosure.

Detailed Description

The following disclosure provides many different embodiments, or examples, of the different components used to implement the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Moreover, spatially relative terms such as "under …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In addition, when numerical values or numerical ranges are described using "about," "approximately," etc., the term is intended to cover numerical values within a reasonable range as understood by one of ordinary skill in the art in view of variations inherently present during manufacture. For example, a value or range of values encompasses a reasonable range including the recited value, such as within +/-10% of the recited value, based on known manufacturing tolerances associated with manufacturing components having characteristics associated with the value. For example, a material layer having a thickness of "about 5nm" may range in size from 4.25nm to 5.75nm, with a manufacturing tolerance of +/-15% associated with depositing the material layer known to one of ordinary skill in the art. Still further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the embodiments and/or configurations discussed.

Multi-dimensional integrated chips are typically formed by stacking a plurality of semiconductor substrates (e.g., semiconductor wafers) on top of one another. For example, during a multi-dimensional integrated chip manufacturing process, the top wafer may be flipped and bonded to the bottom wafer to enable wafer-to-wafer communication. Bonding of the top and bottom wafers may be achieved via a wafer glue layer. In some cases, the wafer glue layer includes a first bonding layer disposed on the top wafer and a second bonding layer disposed on the bottom wafer. Each of the first bonding layer and the second bonding layer includes a metal feature disposed in a dielectric layer. To achieve a strong bond, the metal features in the first and second bonding layers are vertically aligned, and the exposed dielectric layers in the first and second bonding layers are also vertically aligned. The first bonding layer and the second bonding layer cover the scribe line region in addition to the device region. The metal features in the first and second bonding layers above the scribe line region do not provide electrical functionality and may be referred to as dummy features. However, the dummy features in the scribe line region provide wafer bonding functionality. When the dummy features in the first and second bonding layers are not vertically aligned, the wafer-to-wafer bond may be weakened or compromised.

The present disclosure provides a method of generating a dummy pad pattern in a photomask design. These methods include performing multiple alignments or overlaps of the dummy patterns with the edge portions and the center portion of the device layout design. For example, when a first die is to be bonded to a second die, both the first die and the second die may be fabricated on the same wafer. When using step-wise photolithographic exposure to form dummy pad patterns for the first die and the second die, adjacent exposure areas may share portions of the scribe area because the dummy pad patterns on the scribe area are symmetrical using the methods of the present disclosure.

Fig. 1 shows a partial cross-sectional view of a package structure 10. The package structure 10 includes a top die 200 that is flipped over and bonded to a bottom die 100 by a layer of wafer glue 300. The bottom die 100 includes a first substrate 102, a plurality of first transistors 106 fabricated on the first substrate 102, and a first interconnect structure 108 over the first substrate 102. The top die 200 includes a second substrate 202, a plurality of second transistors 206 fabricated on the second substrate 202, and a second interconnect structure 208 over the second substrate 202. In an embodiment, the first substrate 102 and the second substrate 202 each comprise silicon (Si). Alternatively, the first substrate 102 and the second substrate 202 may include a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs),/or indium antimonide; alloy semiconductors such as silicon germanium (SiGe), gaAsP, alInAs, alGaAs, gaInAs, gaInP, and/or GaInAsP; or a combination thereof. Alternatively, the first substrate 102 and the second substrate 202 may be semiconductor-on-insulator substrates, such as silicon-on-insulator (SOI) substrates, silicon-germanium-on-insulator (SGOI) substrates, or germanium-on-insulator (GeOI) substrates. Semiconductor-on-insulator substrates may be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods. The first substrate 102 and the second substrate 202 may each include various doped regions depending on design requirements.

Still referring to fig. 1, each of the first transistor 106 and the second transistor 206 may be a planar transistor or a multi-gate transistor, such as a fin field effect transistor (FinFET) or a full-gate-all-around (GAA) transistor. A planar transistor includes a gate structure that can induce a planar channel region along one surface of its active region, hence the name. The FinFET includes a fin active region protruding from a substrate and a gate structure disposed over a top surface and sidewalls of the fin active region. The GAA transistor includes at least one channel member extending between two source/drain features, and a gate structure completely surrounding the at least one channel member. GAA transistors may also be referred to as Surrounding Gate Transistors (SGT) or multi-bridge channel (MBC) transistors because their gate structures wrap around the channel elements. Depending on the shape and orientation, the channel members in GAA transistors may be referred to as nanoplates, semiconductor lines, nanowires, nanostructures, nanopillars, nanobeams (nano-beams), or nanobridges (nano-bridges). In some cases, GAA transistors may be referred to by the shape of the channel member. For example, GAA transistors having one or more nanoflake channel members may also be referred to as nanoflake transistors or nanoflake FETs.

Referring to fig. 1, each of the first interconnect structure 108 and the second interconnect structure 208 may include three (3) to sixteen (16) metal layers to functionally connect the first transistor 106 or the second transistor 206. For ease of illustration, each of the first interconnect structure 108 and the second interconnect structure 208 is illustrated as including 4 metal layers, shown in fig. 1, which are representatively illustrated as dice. It should be appreciated that each of the first interconnect structure 108 and the second interconnect structure 208 may include fewer or more metal layers. In one embodiment, the first interconnect structure 108 includes six (6) metal layers and the second interconnect structure 208 includes seven (7) metal layers. Each metal layer includes an Etch Stop Layer (ESL) and an inter-metal dielectric (IMD) layer disposed on the ESL. With respect to each of the first interconnect structure 108 and the second interconnect structure 208, it can be said that the ESL is interleaved with IMD layers or the IMD layers are interleaved with ESL. The ESL may comprise silicon carbide, silicon nitride or silicon oxynitride. The IMD layer may include silicon oxide, tetraethyl orthosilicate (TEOS) oxide, undoped Silicate Glass (USG), or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused Silicate Glass (FSG), phosphosilicate glass (PSG), boron doped silicate glass (BSG), low-k dielectric materials, other suitable dielectric materials, or combinations thereof. Exemplary low-k dielectric materials include carbon doped silicon oxide, xerogel, aerogel, amorphous carbon fluoride, benzocyclobutene (BCB), or polyimide.

Each metal layer of the first interconnect structure 108 and the second interconnect structure 208 includes a plurality of vertically extending vias and a plurality of horizontally extending metal lines. The contact vias and metal lines in the first interconnect structure 108 and the second interconnect structure 208 may include copper (Cu), tantalum (Ta), nickel (Ni), cobalt (Co), aluminum (Al), or combinations thereof. In one embodiment, the contact via, metal line, and top metal may comprise copper (Cu). Although not explicitly shown, the contact vias, metal lines, and top metal features may also include a barrier layer interfacing with the oxygen-containing IMD. The barrier layer may include titanium nitride (TiN), tantalum nitride (TaN), manganese nitride (MnN), or other transition metal nitrides.

The bottom die 100 includes a backside adjacent to the first substrate 102 and a front side adjacent to the first interconnect structure 108. The top die 200 includes a backside adjacent to the second substrate 202 and a front side adjacent to the second interconnect structure 208. On its front side, the bottom die 100 includes a first pad contact layer 110 and a first pad layer 120 over the first pad contact layer 110. The top die 200 includes a second pad contact layer 210 and a second pad layer 220 over the second pad contact layer 210. The first pad layer 120 includes a first metal pad 124 embedded in a first dielectric layer 122. The second pad layer 220 includes a second metal pad 224 embedded in a second dielectric layer 222. As shown in fig. 1, the first pad contact layer 110 functions to electrically couple the first interconnect structure 108 to the first metal pad 124 in the first pad layer 120. The second pad contact layer 210 functions to electrically couple the second interconnect structure 208 to the second metal pad 224 in the second pad layer 220. When the top die 200 is bonded to the bottom die 100, the first metal pads 124 and the second metal pads 224 are vertically aligned and the exposed surfaces of the first dielectric layer 122 and the second dielectric layer 222 are also aligned to maximize metal-to-metal and dielectric-to-dielectric contact. The first dielectric layer 122 and the second dielectric layer 222 may have a composition similar to the IMD layers described above. The first and second metal pads 124 and 224 may include copper (Cu), tantalum (Ta), nickel (Ni), cobalt (Co), aluminum (Al), combinations thereof, or alloys thereof. In one embodiment, the first metal pad 124 and the second metal pad 224 may include copper (Cu). The first pad contact layer 110, the first pad layer 120, the second pad contact layer 210, and the second pad layer 220 may be collectively referred to as a wafer glue layer 300.

In an exemplary process of bonding the top die 200 to the bottom die 100, the first and second pad layers 120 and 220 are planarized by, for example, a CMP process. Then, the surfaces of the first and second pad layers 120 and 220 are cleaned to remove organic and metal contaminants. For example, a sulfuric acid hydrogen peroxide mixture (SPM), a mixture of ammonium hydroxide and hydrogen peroxide (SC 1), or both, may be used to remove organic contaminants on the surfaces of the first metal pad 124, the first dielectric layer 122, the second metal pad 224, and the second dielectric layer 222. A mixture of hydrochloric acid and hydrogen peroxide (SC 2) may be used to remove metal contaminants. In addition to cleaning, the first metal pad 124, the first dielectric layer 122, the second metal pad 224, and the second dielectric layer 222 may be treated by argon plasma or nitrogen plasma to activate their surfaces. After the first metal pad 124 is aligned with the second metal pad 224, an anneal is performed to promote van der waals bonding of the first dielectric layer 122 and the second dielectric layer 222 and Surface Activated Bonding (SAB) of the first metal pad 124 and the second metal pad 224. In some cases, annealing includes a temperature between about 200 ℃ and about 300 ℃. It should be noted that first dielectric layer 122 and second dielectric layer 222 polish faster than first metal pad 124 and second metal pad 224. In some cases, a gap between about 5nm and about 50nm may remain between the surfaces of the first dielectric layer 122 and the second dielectric layer 222 after bonding the bottom die 100 to the top die 200.

A die such as bottom die 100 and top die 200 shown in fig. 1 may include a device region and a scribe region. Scribe areas are locations where the wafer is diced during the singulation process to obtain dies. Because of the nature of the scribe area, devices or components that provide electrical functionality after singulation are not fabricated in the scribe area by design. That is, the scribe area may include features that provide registration, identification, process control, acceptance testing, feature density control, or other functionality prior to singulation processes. For example, the scribe area may be the locus of an Overlay (OVL) pattern, a Critical Dimension Bar (CDBAR) pattern, a Process Control Monitor (PCM) pattern, an Identification (IDNT) pattern, a Wafer Acceptance Test (WAT) pattern, or a dummy frame cell. When referring to metal features in the wafer glue layer, such as the first metal pad 124 in the first pad layer 120 and the second metal pad 224 in the second pad layer 220, the metal features are formed not only over the device region, but also over the scribe line region. The metal part is placed in the scribe area for at least two reasons. First, the metal features in the scribe line regions may increase the pattern density in the scribe line regions that are otherwise isolated. Without these metal features, the scribe area may have a smaller pattern density and may be damaged during a planarization process such as a Chemical Mechanical Polishing (CMP) process. Second, the metal features in the scribe line region may provide additional bonding surfaces, including metal surfaces and dielectric surfaces. Because the metal components of the first and second pad layers 120 and 220 in the scribe line region do not provide any electrical function and may be electrically floating, they may also be referred to as dummy pads, dummy components, or dummy pad components. In some cases, each dummy pad has a width or diameter between about 0.2 μm and about 2.5 μm.

Fig. 2-8 illustrate an exemplary method of generating a dummy pad pattern for a scribe area of a design layout 400. Referring first to FIG. 2, a design layout 400 is shown. The design layout includes at least one device region 402 surrounded by scribe line region 404. It can be seen that scribe line region 404 in fig. 2 is sawed between adjacent device regions 402. In some embodiments shown in fig. 2, the design layout 400 also includes PCM patterns 406 and OVL patterns 408 that fall within the scribe line region 404. In other embodiments not explicitly shown in fig. 2, PCM pattern 406 may be replaced by an OVL pattern, a CDBAR pattern, an IDNT pattern, or a WAT pattern, or PCM pattern 406 may include an OVL pattern, a CDBAR pattern, an IDNT pattern, or a WAT pattern. Also, the OVL pattern 408 may be replaced by a PCM pattern, a CDBAR pattern, an IDNT pattern, or a WAT pattern, or the OVL pattern 408 may include a PCM pattern, a CDBAR pattern, an IDNT pattern, or a WAT pattern.

Still referring to fig. 2, the dummy pattern 450 including the dummy pad shape is aligned with the entire design layout 400, such as the geometric center 450C of the dummy pattern 450 vertically overlaps the geometric center 400C of the design layout 400. As shown in fig. 3, a dummy pattern 450 is superimposed (super-positioned) on the design layout 400, including over the device region 402, scribe line region 404, PCM pattern 406, and OVL pattern 408. Referring to fig. 4, after the dummy pattern 450 is aligned with the design layout 400, portions of the dummy pattern 450 directly over the device region 402, the PCM pattern 406, and the OVL pattern 408 are removed or engraved. This operation is required because the dummy pattern 450 will be fabricated on the photomask and the photomask will be used in a photolithographic process to form the dummy pads in the scribe line region 404. A functional metal feature will be formed over device region 402. In addition, because dummy pads over the PCM pattern 406 and OVL pattern 408 may interfere with the detection of the PCM pattern 406 and OVL pattern 408, the dummy pattern 450 over the PCM pattern 406 and OVL pattern 408 should be removed. After selectively removing the dummy pattern 450 from over the device region 402, the PCM pattern 406, and the OVL pattern 408, a dummy pad pattern 480 is generated as shown in fig. 4.

When patterning the wafer, a first photomask including the dummy pad pattern 480 and a second photomask including a mirror image 480M of the dummy pad pattern 480 may be manufactured. The images of the first photomask and the second photomask may be transferred stepwise onto the wafer. The use of the first photomask and the second photomask ensures alignment of the bonding layer during a wafer-on-wafer (WoW) bonding process. Referring to fig. 5, an arrow symbol is applied to show that the dummy pad pattern 480 and the mirror image 480M are mirror images of each other with respect to a dotted line. Exposing the semiconductor wafer 500 includes alternately stepping the dummy pad pattern 480 (on the first photomask) and its mirror image (on the second photomask) across the semiconductor wafer 500 shown in fig. 6 along the X-direction and along the Y-direction. For illustration purposes, each dummy pad pattern 480 in fig. 6 is marked with a right arrow (→) and each mirror image 480M in fig. 6 is marked with a left arrow (≡). As shown in fig. 6, the image of the dummy pad pattern 480 is interleaved with the image of the mirror 480M along the X-direction and the Y-direction. Note that the semiconductor wafer 500 extends along an X-Y plane. To maximize yield, adjacent images of the dummy pad pattern 480 and the mirror image 480M may share the double exposure portion 490 in the scribe line region. Because each design layout 400 is rectangular in shape, the double exposure portion 490 is an edge portion of the scribe line region and may be rectangular in shape. Because the alignment of the dummy pattern 450 with the design layout 400 is performed with respect to the geometric centers of the dummy pattern 450 and the design layout 400, the double exposure portion 490 may not be perfectly aligned.

Fig. 7 shows the case where the double exposure portions 490 are not perfectly aligned. In fig. 7, the dummy pad pattern 480 includes an array of dummy pad shapes disposed closer to the right edge of the dummy pad pattern 480. As a mirror image of the dummy pad pattern 480, the mirror image 480M includes an array of dummy pad shapes disposed closer to the left edge of the mirror image 480M. When the scribe line region of the dummy pad pattern 480 overlaps the scribe line region of the mirror image 480M at the double exposure portion 490, the dummy pad shape is not perfectly aligned and an abnormal exposure image 495 may be generated. It has been observed that such an abnormally exposed image 495 may interfere with the vertical alignment of the metal parts, thereby weakening the wafer bond. In some embodiments shown in the figures, each dummy pad shape is circular. In some other embodiments, the dummy pad shape may be rectangular or include a combination of circular and rectangular shapes.

Fig. 8 shows the case where the double exposure portions 490 are exactly perfectly aligned. In fig. 8, the dummy pad pattern 480 includes an array of dummy pad shapes aligned with the geometric center of the scribe line region adjacent to the right edge. As a mirror image of the dummy pad pattern 480, the mirror image 480M includes an array of dummy pad shapes aligned with the geometric center of the scribe line region adjacent to the left edge. When the scribe line region of the dummy pad pattern 480 overlaps the scribe line region of the mirror image 480M at the double exposure portion 490, the dummy pad shape is perfectly aligned. It has been observed that this perfect alignment promotes vertical alignment of the metal components, thereby enhancing wafer bonding. It should be noted that although the situation shown in fig. 8 may occur if once the dummy patterns 450 are aligned with the design layout 400 with respect to their geometric centers, it is not guaranteed that this will always occur. Thus, process instability may result.

Fig. 9 is a flow chart illustrating a method 600 of fabricating a photomask. The method 600 is merely an example and is not intended to limit the present disclosure to what is explicitly shown in the method 600. Additional steps may be provided before, during, and after the method 600, and some of the steps described may be replaced, eliminated, or moved for additional embodiments of the method. For simplicity, not all steps are described in detail herein. The method 600 is described below in connection with fig. 10-28, with fig. 10-28 including schematic top views of various design layouts, various dummy patterns, various photomask designs, various photomasks, and step exposures (stepwise exposure) of the various photomasks. For the avoidance of doubt, X, Y and Z directions used in fig. 10 to 28 are identical and perpendicular to each other. Throughout this disclosure, like reference numerals refer to like parts unless explicitly described otherwise.

Referring to fig. 9-11, method 600 includes a block 602, at block 602, a design layout is received. The design layer received at block 602 may be an O-frame design layout 400 or a U-frame design layout 401. The design layout 400 in fig. 10 includes a device region 402 and a scribe line region 404. The scribe line region 404 includes an edge portion 404E and a center portion 404C. In some embodiments shown in fig. 10, the design layout 400 further includes PCM patterns 406 and OVL patterns 408 that fall within the scribe line region 404 (or edge portion 404E). In other embodiments, PCM pattern 406 may be replaced by or may include an OVL pattern, a CDBAR pattern, an IDNT pattern, or a WAT pattern. Also, the OVL pattern 408 may be replaced by, or may include, a PCM pattern, a CDBAR pattern, an IDNT pattern, or a WAT pattern. The O-frame design layout 400 is named because the edge portion 404E of the scribe line region 404 extends completely around the O-frame design layout 400. In some embodiments, as shown in FIG. 10, the O-frame design layout 400 is rectangular in shape in the X-Y plane. The U-frame design layout 401 in fig. 11 includes a device region 402 and a scribe line region 405. The scribe line region 405 in fig. 11 includes an edge portion 405E and a center portion 405C, wherein the edge portion 405E engages the center portion 405C on three sides. In some embodiments shown in fig. 11, the design layout 401 further includes PCM patterns 406 and OVL patterns 408 that fall within the scribe line region 405 (or edge portion 405E). The PCM pattern 406 may be replaced by or may include an OVL pattern, a CDBAR pattern, an IDNT pattern, or a WAT pattern. Also, the OVL pattern 408 may be replaced by, or may include, a PCM pattern, a CDBAR pattern, an IDNT pattern, or a WAT pattern. The U-shaped frame design layout 401 is named because its edge portions 405E form a U-shape. In some embodiments shown in FIG. 11, the U-shaped frame design layout 401 is rectangular in shape in the X-Y plane. For the O-frame design layout 400, the device region 402 is enclosed in the center portion 404C of fig. 10; and for the U-frame design layout 401, the device region 402 is enclosed in the center portion 405C in fig. 11. To facilitate the step exposure operation, the opposite edges of edge portion 404E or edge portion 405E have the same width to ensure perfect vertical alignment.

Referring to fig. 9 and 12-13, the method 600 includes a block 604 where an edge portion of a scribe line region of a design layout is divided into rectangular partitions at block 604. As shown in fig. 12, an edge portion 404E of the O-frame design layout 400 may be divided into a first partition 4042, a second partition 4044, a third partition 4046, and a fourth partition 4048. Each of the first, second, third and fourth partitions 4042, 4044, 4046, 4048 is rectangular in shape. It should be noted that the first and second partitions 4042 and 4044 extend longitudinally along the Y-direction, and the third and fourth partitions 4046 and 4048 extend longitudinally along the X-direction. As shown in fig. 13, an edge portion 405E of the U-shaped frame design layout 401 may be divided into a first partition 4052, a second partition 4054, and a third partition 4056. Each of the first, second and third partitions 4052, 4054, 4056 is rectangular in shape. It should be noted that the first and second partitions 4052, 4054 extend longitudinally along the Y-direction and the third partition 4056 extends longitudinally along the X-direction. It should be appreciated that the edge portion 404E of the O-frame design layout 400 and the edge portion 405E of the U-frame design layout 401 may be divided differently to enable the method 600. For example, with respect to the O-frame design layout 400, the third and fourth partitions 4046, 4048 may extend along the X-direction all the way to the boundary of the O-frame design layout 400, and the first and second partitions 4042, 4044 extend along the Y-direction only between the third and fourth partitions 4046, 4048. As another example, with respect to the U-shaped frame design layout 401, the third partition 4056 may extend along the X-direction all the way to the boundary of the U-shaped frame design layout 401, and the first partition 4052 and the second partition 4054 extend along the Y-direction only from the third partition 4056.

Referring to fig. 9 and 12-13, the method 600 includes a block 606, at which 606 the dummy pattern 450, the center portion region, and the geometric center of each rectangular partition are identified. As shown in fig. 12, at block 606, a geometric center or centroid (shown as a dashed cross) is identified for the dummy pattern 450 and the center portion 404C, first partition 4042, second partition 4044, third partition 4046, and fourth partition 4048 of the O-frame design layout 400. As shown in fig. 13, at block 606, a geometric center or centroid (shown as a dashed cross) is identified for the dummy pattern 450 and the center portion 405C, first partition 4052, second partition 4054, and third partition 4056 of the U-shaped frame design layout 401. For the avoidance of doubt, because the patterns, regions and zones in fig. 12 or 13 are rectangular in shape, their geometric centers are equidistant from the boundaries along the X-direction or Y-direction.

Referring to fig. 9 and 14-22, the method 600 includes a block 608, at which 608 the dummy pattern 450 is aligned with each rectangular section of the center and edge portions, respectively, of the scribe line region. As shown in fig. 14-18, with respect to the O-frame design layout 400, the dummy patterns 450 are superimposed on the first partition 4042 such that their geometric centers completely overlap; the dummy patterns 450 are superimposed on the second partitions 4044 such that their geometric centers are completely overlapped; the dummy patterns 450 are superimposed on the third partitions 4046 such that their geometric centers are completely overlapped; the dummy patterns 450 are superimposed on the fourth region 4048 such that their geometric centers are completely overlapped; and the dummy patterns 450 are superimposed on the center portion 404C such that their geometric centers are completely overlapped. The purpose of each alignment operation is to obtain a portion of the dummy pattern 450 that overlaps the boundary of each of the center portion 404C, the first partition 4042, the second partition 4044, the third partition 4046, and the fourth partition 4048. It should be noted that the alignment operations for the O-frame design layout 400 may be performed in any order.

As shown in fig. 19 to 22, regarding the U-shaped frame design layout 401, the dummy patterns 450 are superimposed on the first partition 4052 such that their geometric centers completely overlap; the dummy patterns 450 are superimposed on the second partitions 4054 such that their geometric centers completely overlap; the dummy patterns 450 are superimposed on the third partitions 4056 such that their geometric centers are completely overlapped; and the dummy patterns 450 are superimposed on the central portion 405C such that their geometric centers completely overlap. The purpose of each alignment operation is to obtain a portion of the dummy pattern 450 that overlaps the boundary of each of the center portion 405C, the first partition 4052, the second partition 4054, and the third partition 4056. It should be noted that the alignment operations for the U-frame design layout 401 may be performed in any order. As described above and shown in fig. 14-22, all alignment operations at block 608 are performed to align the geometric centers.

Referring to fig. 9 and 23-24, the method 600 includes a block 610, at which a scribe pad pattern is derived from the alignment performed at block 608. Reference is first made to fig. 23. In an exemplary operation, the images of the dummy patterns 450 aligned with the first, second, third, fourth and center sections 4042, 4044, 4046, 4048, 404C of the O-frame design layout 400 are first combined to form a combined pattern, and then the images of the dummy patterns 450 over the device region 402, PCM pattern 406 and OVL pattern 408 are selectively removed or engraved from the combined pattern to form a first scribe pad pattern 480 (first net dummy pad pattern 480 or first dummy pad pattern 480). Reference is then made to fig. 24. In an exemplary operation, the images of the dummy patterns 450 aligned with the first, second, third, and center sections 4052, 4054, 4056, 405C of the U-shaped frame design layout 401 are first combined to form a combined pattern, and then the images of the dummy patterns 450 over the device region 402, PCM pattern 406, and OVL pattern 408 are removed or engraved from the combined pattern to form a second scribe pad pattern 482 (second net dummy pad pattern 482 or second dummy pad pattern 482).

Referring to fig. 9 and 25, method 600 includes block 612, at block 612, a photomask including a scribe pad pattern is fabricated. Although not explicitly shown in the drawings, the photomask may be a transmissive photomask including a transparent fused silica plate having an absorbing member formed of chromium (Cr) or iron oxide. Fabrication of the photomask may include depositing the various layers and patterning the various layers using electron beam (e-beam) lithography. In some embodiments, because a photomask is used for step exposure, it may also be referred to as a reticle. Regarding the O-frame design layout 400, the photomask fabricated at block 612 may include a first photomask 702 and a second photomask 704, the first photomask 702 including a first scribe pad pattern 480 and the second photomask 704 including a mirror image 480M of the first scribe pad pattern 480 (as shown in fig. 26). Regarding the U-frame design layout 401, the photomask fabricated at block 612 may include a third photomask 706 and a fourth photomask 708, the third photomask 706 including the second scribe pad pattern 482 and the fourth photomask 708 including a mirror image 482M of the second scribe pad pattern 482 (as shown in fig. 27). As described below, the step exposure may be performed using the first photomask 702, the second photomask 704, the third photomask 706, and the fourth photomask 708 in different combinations. As shown in fig. 25, each of the first photomask 702, the second photomask 704, the third photomask 706, and the fourth photomask 708 further includes a functional pad pattern 720 located in the engraved device region 402. The functional pad pattern 720 is generated separately from the first scribing pad pattern 480 or the second scribing pad pattern 482. In some embodiments, functional pad pattern 720 may be inserted into device region 402 after first scribe pad pattern 480 or second scribe pad pattern 482 is generated.

Referring to fig. 9 and 26-28, method 600 includes block 614, at block 614, using a photomask and a mirror image of the photomask to step-expose a photoresist layer on a substrate. In some embodiments, the substrate may be a semiconductor substrate similar to the first substrate 102 or the second substrate 202 shown in fig. 1. When the photoresist layer is exposed to a radiation source, such as an Ultraviolet (UV) light source or a Deep UV (DUV) light source, a combination of the first photomask 702, the second photomask 704, the third photomask 706, and the fourth photomask 708 is used. As shown in fig. 26, 27 and 28, the photoresist layer may be subjected to step exposure to transfer the pattern of the first scribe pad pattern 480, the mirror image 480M of the first scribe pad pattern 480, the second scribe pad pattern 482, or the mirror image 482M of the second scribe pad pattern 482 to the photoresist. It should be noted that the substrate may be a semiconductor wafer similar to the semiconductor wafer 500 shown in fig. 6, and that a photoresist layer is disposed over the top surface of the semiconductor wafer. The step exposure may be transferred or repeated in two perpendicular directions (such as the X-direction and the Y-direction shown in fig. 6) until the image of the first scribe pad pattern 480, mirror 480M, second scribe pad pattern 482, or mirror 482M is transferred to a rectangular partition on the semiconductor wafer.

Fig. 26 shows an example in which step exposure repeatedly transfers the first scribe pad pattern 480 and the image of the mirror image 480M of the first scribe pad pattern 480 onto the photoresist layer. The step exposure includes using a first photomask 702 and a second photomask 704 shown in fig. 25. As shown in fig. 26, the first scribe pad pattern 480 and the adjacent image of the mirror image 480M of the first scribe pad pattern 480 may share the double exposure portion 490. Because of the multiple alignments at block 608, the dummy pad shapes in the double exposure portion 490 are aligned vertically. An abnormal shape like the abnormal exposure image 495 in fig. 7 will not be generated. The functional pad patterns 720 of the first photomask 702 and the second photomask 704 produce functional pad images 820.

Fig. 27 shows an example in which step exposure repeatedly transfers the second scribe pad pattern 482 and an image of the mirror image 482M of the second scribe pad pattern 482 onto the photoresist layer. The step exposure includes using a third photomask 706 and a fourth photomask 708 shown in FIG. 25. As shown in fig. 27, the second scribe pad pattern 482 and the adjacent image of the mirror image 482M of the second scribe pad pattern 482 may share the double exposure portion 490. Because of the multiple alignments at block 608, the dummy pad shapes in the double exposure portion 490 are aligned vertically. An abnormal shape like the abnormal exposure image 495 in fig. 7 will not be generated. The functional pad patterns 720 of the third photomask 706 and the fourth photomask 708 produce functional pad images 820.

Fig. 28 shows an example in which step exposure repeatedly transfers images of mirror image 482M of first scribe pad pattern 480 and second scribe pad pattern 482 onto the photoresist layer. The step exposure includes using the first photomask 702 and the fourth photomask 708 shown in fig. 25. As shown in fig. 28, adjacent images of mirror image 482M of first scribe pad pattern 480 and second scribe pad pattern 482 may share double exposure portion 490. Because of the multiple alignments at block 608, the dummy pad shapes in the double exposure portion 490 are aligned vertically. An abnormal shape like the abnormal exposure image 495 in fig. 7 will not be generated. The functional pad patterns 720 of the first photomask 702 and the fourth photomask 708 produce functional pad images 820.

Fig. 26 to 28 show a double exposure portion 490 extending longitudinally along the Y direction. It should be appreciated that a similar double exposure portion 490 may extend longitudinally in the X-direction between the first scribe pad pattern 480 and the mirror image 480M of the underlying first scribe pad pattern 480 or longitudinally in the X-direction between the first scribe pad pattern 480 and the mirror image 482M of the underlying second scribe pad pattern 482.

Referring to fig. 9, method 600 includes block 616, at block 616, further processing is performed. Such further processing may include, for example, etching the dielectric layer under the patterned photoresist layer using the patterned photoresist layer as an etch mask. For example, a photoresist layer may be deposited on the hard mask layer, which is deposited on dielectric layers similar to the first dielectric layer 122 and the second dielectric layer 222 shown in fig. 1. In some embodiments, the dielectric layer may include silicon oxide or silicon oxynitride. The step exposure at block 614 transfers the image of the first scribe pad pattern 480, the mirror 480M of the first scribe pad pattern 480, the second scribe pad pattern 482, or the mirror 482M of the second scribe pad pattern 482 onto the photoresist layer. The patterned photoresist layer may be subjected to a post-exposure bake. Thereafter, the baked photoresist layer may be developed in a developer. After baking the photoresist layer in a post-development bake process, it is applied as an etch mask to pattern the underlying hard mask layer. The patterned hard mask layer is then applied as an etch mask to pattern the dielectric layer. In some embodiments, a metal layer may then be deposited over the dielectric layer. After the planarization process, a bonding layer similar to the first pad layer 120 or the second pad layer 220 shown in fig. 1 may be formed.

When the method 600 described above in connection with fig. 10-28 is applied to form the package structure 10 shown in fig. 1, the package structure 10 will include several unique features. In one aspect, the plurality of first transistors 106 in the bottom die 100 and the plurality of second transistors 206 in the top die 200 may have different technology nodes. That is, they may have significantly different gate pitches and gate lengths. For example, in a 28nm technology node, a representative gate length may be between about 27nm and about 32nm, and a representative gate pitch may be between about 110nm and about 130 nm. In a 40nm technology node, a representative gate length may be between about 35nm and about 45nm, and a representative gate pitch may be between about 155nm and about 170 nm. In a 65nm technology node, a representative gate length may be between about 65nm and about 75nm, and a representative gate pitch may be between about 250nm and about 270 nm. In one embodiment, the bottom die 100 is an Image Signal Processing (ISP) die, wherein the plurality of first transistors 106 have 28nm technology nodes. The top die 200 is a CMOS Image Sensor (CIS) die in which the plurality of second transistors 206 have 65nm technology nodes. In another aspect, the dies of different technology nodes may have different scribe arrangements. For example, a 28nm technology node die may have an O-frame layout as shown in fig. 10, while a 40nm or 65nm technology node die may have a U-frame layout as shown in fig. 11. That is, in the foregoing embodiment where the bottom die 100 is an ISP die and the top die 200 is a CIS die, the bottom die 100 has an O-frame layout and the top die 200 has a U-frame layout. This again demonstrates how important it is to center the dummy pattern 450 with respect to the different rectangular sections of the scribe line region to ensure perfect alignment of the double exposure regions.

In one exemplary aspect, the present disclosure is directed to a three-dimensional integrated circuit (3 DIC) device. A three-dimensional integrated circuit (3 DIC) device includes a first device including a first tier including a first layout and a first scribe area and a second device including a second tier including a second layout and a second scribe area. The first layer is bonded to the second layer. The first layout is a mirror image of the second layout. The first scribe line region includes a first plurality of dummy features symmetrically arranged with respect to a center of the first scribe line region.

In some embodiments, the second scribe area includes a second plurality of dummy features symmetrically arranged with respect to a center of the second scribe area. In some embodiments, the first scribe area includes a first overlay pattern and the second scribe area includes a second overlay pattern.

In another exemplary aspect, the present disclosure is directed to a method. The method includes receiving a design layout including a device region disposed in a scribe line region, identifying a center portion of the scribe line region surrounding the device region and an edge portion surrounding the center portion, dividing the edge portion into a plurality of rectangular partitions, superimposing a dummy pattern on each of the plurality of rectangular partitions to obtain an edge dummy pattern, superimposing the dummy pattern on the center portion to obtain a center dummy pattern, engraving a portion of the dummy pattern corresponding to the device region from the center dummy pattern to obtain a net center dummy pattern, generating a scribe line dummy pattern based on the edge dummy pattern and the net center dummy pattern, and manufacturing a first photomask including the scribe line dummy pattern.

In some embodiments, the method further comprises fabricating a second photomask comprising a mirror image of the scribe line dummy pattern. In some embodiments, the method may further include receiving a wafer including a photoresist layer, and step-wise transferring the first image of the first photomask and the second image of the second photomask onto the photoresist layer. In some embodiments, the step transfer forms an array comprising a plurality of first images and a plurality of second images. In some embodiments, step transfer is performed such that the first image overlaps the second image at the double exposure region. In some embodiments, the first image includes a first dummy feature and the second image includes a second dummy feature, and the first dummy feature and the second dummy feature completely overlap in the double exposure region. In some cases, the double exposure area includes a rectangular shape. In some embodiments, the edge portion surrounds the center portion on three sides, and the plurality of rectangular partitions includes three rectangular partitions. In some embodiments, the edge portion surrounds the center portion on four sides, and the plurality of rectangular partitions includes four rectangular partitions.

In yet another exemplary aspect, the present disclosure is directed to a method. The method includes receiving a design layout including a device region disposed in a scribe line region, dividing the scribe line region into a center portion and an edge portion around the center portion, dividing the edge portion into a first partition, a second partition, a third partition, and a fourth partition, receiving a dummy pattern, identifying a first centroid of the dummy pattern, a second centroid of the first partition, a third centroid of the second partition, a fourth centroid of the third partition, a fifth centroid of the fourth partition, and a sixth centroid of the center portion, superimposing a dummy pattern on the first partition such that the second centroid overlaps the first centroid to obtain a first pattern, superimposing the dummy pattern on the second partition such that the third centroid overlaps the first centroid to obtain a second pattern, superimposing the dummy pattern on the third partition such that the fourth centroid overlaps the first centroid to obtain a third pattern, superimposing the dummy pattern on the fourth partition such that the fifth centroid overlaps the first centroid to obtain a fourth pattern, superimposing the fourth centroid, superimposing the fifth pattern on the fourth centroid to obtain a fifth pattern, superimposing the fifth pattern on the fifth centroid to obtain a fifth pattern, superimposing the fifth pattern, and the fifth pattern is superimposed on the fifth pattern, generating a fifth pattern, and a mask pattern is superimposed on the fifth pattern.

In some embodiments, each of the first partition, the second partition, the third partition, the fourth partition, and the central portion is rectangular in shape. In some embodiments, the method further comprises inserting the functional pad pattern into the dummy pad pattern design prior to fabrication. In some embodiments, the method further includes fabricating a second photomask including a mirror image of the dummy pad pattern design. In some embodiments, the method further comprises receiving a wafer comprising a photoresist layer, and step-wise transferring the image of the first photomask and the image of the second photomask onto the photoresist layer. In some embodiments, the image of the first photomask and the image of the second photomask at least partially overlap in the double-exposure portion. In some embodiments, the central portion further includes an Overlay (OVL) pattern, a Critical Dimension Bar (CDBAR) pattern, a Process Control Monitor (PCM) pattern, an Identification (IDNT) pattern, or a Wafer Acceptance Test (WAT) pattern. In some embodiments, the removing includes removing a second portion of the dummy pattern corresponding to the OVL pattern, CDBAR pattern, PCM pattern, IDNT pattern, or WAT pattern from the sixth pattern.

The foregoing outlines features of a drop-off embodiment so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1. A three-dimensional integrated circuit device, comprising:

a first device comprising a first layer comprising a first layout and a first scribe area; and

a second device comprising a second layer, the second layer comprising a second layout and a second scribe area,

wherein the first layer is bonded to the second layer,

wherein the first layout is a mirror image of the second layout,

wherein the first scribe line region includes a first plurality of dummy features symmetrically arranged with respect to a center of the first scribe line region.

2. The three-dimensional integrated circuit device of claim 1, wherein the second scribe area comprises a second plurality of dummy features arranged symmetrically with respect to a center of the second scribe area.

3. The three-dimensional integrated circuit device of claim 1,

wherein the first scribe area includes a first overlay pattern,

wherein the second scribe area includes a second overlay pattern.

4. A method of fabricating a three-dimensional integrated circuit device, comprising:

receiving a design layout, the design layout including a device region disposed in a scribe line region;

identifying a central portion of the scribe line region surrounding the device region and an edge portion surrounding the central portion;

Dividing the edge portion into a plurality of rectangular partitions;

superimposing a dummy pattern on each of the plurality of rectangular partitions to obtain an edge dummy pattern;

superimposing the dummy pattern on the central portion to obtain a central dummy pattern;

engraving a portion of the dummy pattern corresponding to the device region from the center dummy pattern to obtain a net center dummy pattern;

generating a scribe line dummy pattern based on the edge dummy pattern and the net center dummy pattern; and

a first photomask including the scribe line dummy pattern is manufactured.

5. The method of claim 4, further comprising:

a second photomask including a mirror image of the scribe line dummy pattern is fabricated.

6. The method of claim 5, further comprising:

receiving a wafer comprising a photoresist layer; and

the first image of the first photomask and the second image of the second photomask are transferred onto the photoresist layer step by step.

7. The method of claim 6, wherein the step-wise transferring forms an array comprising a plurality of the first images and a plurality of the second images.

8. The method of claim 6, wherein the step transfer is performed such that the first image overlaps the second image at a double exposure area.

9. The method according to claim 8, wherein the method comprises,

wherein the first image comprises a first dummy feature and the second image comprises a second dummy feature,

wherein the first dummy feature and the second dummy feature completely overlap in the double exposure region.

10. A method of fabricating a three-dimensional integrated circuit device, comprising:

receiving a design layout, the design layout including a device region disposed in a scribe line region;

dividing the scribing region into a center portion and an edge portion around the center portion;

dividing the edge portion into a first partition, a second partition, a third partition and a fourth partition;

receiving a dummy pattern;

identifying a first centroid of the dummy pattern, a second centroid of the first partition, a third centroid of the second partition, a fourth centroid of the third partition, a fifth centroid of the fourth partition, and a sixth centroid of the central portion;

superimposing the pseudo pattern on the first partition such that the second centroid overlaps the first centroid to obtain a first pattern;

superimposing the pseudo pattern on the second partition such that the third centroid overlaps the first centroid to obtain a second pattern;

Superimposing the pseudo pattern on the third partition such that the fourth centroid overlaps the first centroid to obtain a third pattern;

superimposing the pseudo pattern on the fourth partition such that the fifth centroid overlaps the first centroid to obtain a fourth pattern;

superimposing the dummy pattern on the central portion such that the sixth centroid overlaps the first centroid to obtain a fifth pattern;

removing a first portion of the dummy pattern corresponding to the device region from the fifth pattern to obtain a sixth pattern; and

generating a dummy pad pattern design based on the first pattern, the second pattern, the third pattern, the fourth pattern, and the sixth pattern; and

a first photomask including the dummy pad pattern design is manufactured.