JP5471427B2 - Single-phase differential conversion circuit - Google Patents

Description

  The present invention relates to a single-phase differential conversion circuit that converts a single-phase input signal into a differential output signal.

  The single-phase differential conversion circuit is a circuit that generates a differential output signal composed of a normal-phase output signal and a reverse-phase output signal from the single-phase input signal. In general, a single-phase differential conversion circuit generates a positive-phase output signal by passing a single-phase input signal through an even number of inverter rows, and a positive-phase output signal by passing the same single-phase input signal through an odd number of inverter rows. Generates a negative phase output signal having a negative phase and a differential relationship. For this reason, the number of stages of the inverter train differs between the positive phase side and the negative phase side in the single-phase differential conversion circuit, and the phase cannot be matched between the positive phase output signal and the negative phase output signal. The same is true even if the even and odd stages are reversed.

  Here, the fact that the phases match means that the positive phase output signal and the negative phase output signal have a phase difference of exactly 180 °. The deviation from the 180 ° phase difference corresponds to the phase deviation.

  In order to eliminate such a phase shift, it has been proposed to insert a delay circuit in a smaller number of inverter stages or to increase a delay time of an inverter having a smaller number of inverter stages. For example, Patent Literatures 1 and 2 are used.

JP 2001-345683 A JP-A-7-74787

  However, in order to match the phases by inserting a delay circuit, it is necessary to accurately set the delay amount of the delay circuit, and it is difficult to absorb manufacturing variations of transistor devices. Similarly, it is not easy to adjust the delay time of the inverter longer.

  Therefore, an object of the present invention is to provide a single-phase differential conversion circuit in which the phases of a normal phase output signal and a negative phase output signal are matched.

The first aspect of the present invention is:
An input terminal to which a single-phase input signal is input;
A positive phase output terminal for outputting a positive phase output signal;
A negative phase output terminal from which a negative phase output signal in a differential relationship with the positive phase output signal is output;
A first inverter row provided between the input terminal and the positive phase output terminal and including at least first and second inverters connected in series;
A second inverter provided between the input terminal and the negative-phase output terminal and including at least third, fourth, and fifth inverters connected in series and having one stage higher than the first inverter row And
The first inverter row further includes a dummy inverter having a transistor having a drain connected to the output terminal of the first inverter and a gate connected to a voltage that is not conductive.

In the first configuration, preferably, a ratio of gate widths of the first, second, dummy, third, fourth, and fifth inverters is m / 2: m ² : m / 2: 1: m: m. ² and m is the multiplication factor of the inverter.

According to a second aspect of the present invention, an input terminal to which a single-phase input signal is input;
A positive phase output terminal for outputting a positive phase output signal;
A negative phase output terminal for outputting a negative phase output signal opposite to the positive phase output signal;
A first inverter row provided between the input terminal and the positive phase output terminal and including at least first and second inverters connected in series;
A second inverter provided between the input terminal and the negative-phase output terminal and including at least third, fourth, and fifth inverters connected in series and having one stage higher than the first inverter row And
The first inverter train further includes:
A first dummy inverter having a transistor having a transistor with a drain connected to the output terminal of the first inverter and a gate connected to a non-conductive voltage; and a gate connected to the output terminal of the first inverter; And a second dummy inverter having a transistor.

In the second configuration, preferably, the ratio of the gate widths of the first, second, dummy, third, fourth, and fifth inverters is m / 2: m ² : m / 2: 1: m: m ^2. Where m is the multiplication factor of the inverter.

  According to the first configuration or the second configuration of the present invention, the phase difference between the output signal of the first inverter row and the output signal of the second inverter row can be set to 180 ° more accurately and easily than in the past. .

It is a figure which shows the single phase input signal of a single phase differential conversion circuit, and a positive phase and a negative phase output signal. It is a figure which shows an example of a single phase differential conversion circuit. It is a circuit diagram of the single phase differential conversion circuit in the first embodiment. It is a figure explaining the output delay characteristic of an inverter. It is a figure explaining the gate capacity | capacitance and drain capacity | capacitance of a MOS transistor. It is a figure explaining the relationship between the gate width of a transistor, and the number of fingers. It is a figure which shows the simulation result of the single phase differential conversion circuit of 1st Embodiment. It is a circuit diagram of the comparative example of FIG. It is a circuit diagram of the specific example of the single phase differential conversion circuit of a 1st embodiment. It is a circuit diagram of the specific example of the single phase differential conversion circuit of a 1st embodiment. It is a circuit diagram of the single phase differential conversion circuit in the 2nd this embodiment. It is a circuit diagram of the specific example of the single phase differential conversion circuit of 2nd Embodiment. It is a circuit diagram of the specific example of the single phase differential conversion circuit of 2nd Embodiment.

  The present embodiment will be described below with reference to the drawings.

  FIG. 1 is a diagram showing a single-phase input signal and normal-phase and reverse-phase output signals of the single-phase differential conversion circuit. As shown in the figure, the single-phase input signal IN is a clock signal that alternately repeats an H level and an L level, for example. The single-phase differential conversion circuit 10 receives this single-phase input signal IN, and outputs a positive-phase output signal OUTp and a negative-phase output signal OUTx that are in opposite phases and in a differential relationship. Ideally, the output signals OUTp and OUTx are in phase with a phase difference of 180 °.

  FIG. 2 is a diagram illustrating an example of a single-phase differential conversion circuit. The single-phase differential conversion circuit 10 has two inverters INV1 and INV2 on the positive phase side and three inverters INV3, INV4 and INV5 on the negative phase side. That is, an even number of inverters are provided on the positive phase side, and an odd number of inverters are provided on the negative phase side. As a result, the output signals OUTp and OUTx are reversed phase signals.

  However, since the number of inverter stages is different between the positive phase side and the negative phase side, in the above example, the phase of the positive phase output signal OUTp is 180 ° + α ahead of the phase of the negative phase output signal OUTx. This α is out of phase.

FIG. 3 is a circuit diagram of the single-phase differential conversion circuit according to the first embodiment. This single-phase differential conversion circuit 10 includes an input terminal 11 to which a single-phase input signal IN is input, a positive-phase output terminal 12 to which a positive-phase output signal OUTp is output, and a reverse-phase signal that is in a differential relationship with the positive-phase output signal. And a negative phase output terminal 13 from which the phase output signal OUTx is output. Furthermore, the single-phase differential conversion circuit 10 is provided between the input terminal 11 and the negative-phase output terminal 13 and has a gate width GW of a, ma, m ² a (gate width ratio is 1: m: m ² ). A second inverter row including third, fourth, and fifth inverters INV3, INV4, and INV5 each having a transistor is included. These inverters are connected in series. The single-phase differential conversion circuit 10 is provided between the input terminal 11 and the positive-phase output terminal 12 and has a gate width of ma / 2 and m ² a (a gate width ratio of m / 2: m ² ). And a first inverter row including first and second inverters INV1 and INV2, respectively, a drain dn1 connected to the output terminal n1 of the first inverter INV1, a source connected to a gate, and a gate width of ma / 2. And a dummy inverter DINV1 having a number of transistors. The first and second inverters are also connected in series.

  Here, a represents a gate width of one unit, and m represents a multiplication number (positive number). If the multiplication factor m is m = 1, the gate widths GW1 to GW5 of the transistors of the first to fifth inverters are a / 2, a, a, a, a, and the gate widths of the transistors of the dummy inverter GWd is a / 2. When the unit gate width a is a = 2, the gate widths GW1 to GW5 are 1, 2, 2, 2, and 2, and the gate width GWd is 1.

  The first inverter INV1 includes a P-channel MOS transistor P1 and an N-channel MOS transistor N1 each having a gate width GW1 = ma / 2. The source of the P-channel MOS transistor P1 is connected to the high power supply Vdd, the source of the N-channel MOS transistor is connected to the low voltage (ground GND), and the gate and drain are connected to each other. In the CMOS inverter composed of the transistors P1 and N1, the gate terminal g1 is an input terminal and the drain terminal d1 is an output terminal.

  Similarly to the first inverter INV1, the second to fifth inverters INV2 to INV5 are also CMOS inverters. However, the gate width GW of each transistor has a relationship as shown in the figure. The output terminal n1 of the first inverter INV1 is connected to the input terminal g2 of the second inverter INV2. The output terminals and input terminals of the third, fourth and fifth inverters INV3 to INV5 are also connected in the same manner.

  Further, the dummy inverter DINV1 has a P-channel MOS transistor DP1 and an N-channel MOS transistor DN1 each having a gate width GWd = ma / 2, and the drains dn1 of both transistors are connected. The output terminal n1 of the first inverter INV1 is connected to the drains dn1 of the transistors DP1 and DN1 of the dummy inverter DINV1, the transistor DP1 of the dummy inverter DINV1 is connected to the source of DP1, and the gate of DN1 is connected to the source of DN1. It is connected. That is, the drain capacitance of the dummy inverter DINV1 is connected to the output terminal n1 of the first inverter INV1, but the gate capacitance of the dummy inverter DINV1 is not connected to the output terminal n1 of the first inverter INV1. The gates of the transistors DP1 and DN1 of the dummy inverter DINV1 are preferably connected to their respective sources, but the gates only need to be connected to a fixed voltage that does not cause the transistors to conduct. As a result, the drain capacity of the own inverter INV1, the drain capacity of the dummy inverter DINV1, and the gate capacity of the second inverter INV2 are connected to the output terminal n1 of the first inverter INV1. The drain terminal of its own INV3 and the gate capacity of the fourth inverter INV4 are connected to the output terminal n3 of the third inverter INV3. A similar capacitor is connected to the output terminal n4 of the fourth inverter INV.

Also, the final-phase inverter INV2 on the positive phase side and the final-stage inverter INV5 on the negative phase side have the same gate width GW2 = GW5 = m ² a. An equivalent load capacity is connected to the positive phase output terminal 12 and the negative phase output terminal 13. Therefore, if the gate widths of the transistors of both inverters INV2 and INV5 are made equal, the delay times of both inverters INV2 and INV5 can be made equivalent.

  FIG. 4 is a diagram for explaining the output delay characteristics of the inverter. The circuit of FIG. 4 includes a front-stage inverter Inv1 and a rear-stage inverter Inv2, the inverter Inv1 includes a PMOS transistor PM1 and an NMOS transistor NM1, and the inverter Inv2 includes a PMOS transistor PM2 and an NMOS transistor NM2.

  The drains of the transistors PM1 and NM1 of the inverter Inv1 are connected, and the output node n1 that is the connected drain is connected to the input gate of the inverter Inv2. Therefore, the drain capacitance Cd of the transistors PM1 and NM1 of the inverter Inv1 and the gate capacitance Cg of the transistors PM2 and NM2 of the inverter Inv2 are connected to the output node n1, and these capacitances affect the delay time. Further, when the transistor PM1 becomes conductive and the drive current Idr flows, the output resistance of the transistor PM1 affects the delay time. When the transistor NM1 becomes conductive, the output resistance of the transistor NM1 affects the delay time.

  FIG. 5 is a diagram for explaining the gate capacitance Cg and the drain capacitance Cd of the MOS transistor. FIG. 5A shows an N-channel MOS transistor NM1, and parasitic gate capacitance Cg and drain capacitance Cd formed thereon. FIG. 5B shows a cross-sectional structure of the MOS transistor NM1. For example, the gate insulating film 21 and the gate electrode 22 are provided on the surface of the P-type substrate 20, and the N-type drain region 23 and the source region 24 are provided on both sides of the gate electrode 22. The substrate 20 is connected to the ground GND, and the source region 24 is also connected to the ground GND. The drain region 23 is connected to the drain of a P-channel MOS transistor (not shown) constituting the CMOS inverter.

Returning to FIG. 4, it is assumed that the gate widths of the two transistors PM1 and NM1 of the inverter Inv1 are GW1 = a1, and the gate widths of the two transistors PM2 and NM2 of the inverter Inv2 are GW2 = a2. The gate capacity and drain capacity of the transistor are proportional to the gate width of the transistor, and the output resistance is inversely proportional to the gate width of the transistor. Therefore, the CR time constant when the output terminal n1 of the inverter Inv1 rises from the ground potential GND to the power supply voltage Vdd is
CR = (Rdt / a1) × (Cdt × a1 + Cgt × a2) (1)
In the above formula, Cgt, Cdt, and Rdt are values of gate capacitance, drain capacitance, and output resistance when the gate width is unit length.

  As can be understood from the above equation (1), when the gate width of the transistor of the CMOS inverter is increased, the output resistance is decreased, but the gate capacitance and the drain capacitance are increased.

Next, the delay time of the single-phase differential conversion circuit of FIG. 3 will be described. In the circuit of FIG. 3, the final-stage inverters INV2 and INV5 on the positive phase side and the negative phase side have the same gate width m ² a. As a result, when similar output capacitors are connected to the output terminals 12 and 13, the delay times of the output signals of both the inverters INV2 and INV5 are approximately the same. Therefore, the delay characteristics on the positive phase side and the negative phase side excluding the delay characteristics of the inverter at the final stage, that is, the CR time constant will be described below.

First, the negative phase CR time constant CRx is the sum of the CR time constant of the output signal of the inverter INV3 and the CR time constant of the output signal of the inverter INV4. Since the gate widths GW of the inverters INV3 to INV5 on the negative phase side are a, ma, m ² a, CRx is
CRx
= (Rdt / a) × (Cdt × a + Cgt × ma) + (Rdt / ma) × (Cdt × ma + Cgt × m ² a)
= (RdtCdt + mRdtCgt) + (RdtCdt + mRdtCgt)
= 2RdtCdt + 2mRdtCgt (2)
That is, the CR time constants of the inverters INV3 and INV4 are equal, and the CR time constant obtained by adding both is as shown in the above equation (2).

On the other hand, the CR time constant CRp on the positive phase side is the CR time constant of the output signal of the inverter INV1. Since the drain capacity of the inverter INV1, the drain capacity of the dummy inverter DINV1, and the gate capacity of the inverter INV2 are connected to the output terminal n1 of the inverter INV1, the CR time constant CRp on the positive phase side is as follows: .
CRp = (2Rdt / ma) × {(Cdt × ma / 2) + (Cdt × ma / 2) + Cgt × m ² a}
= 2RdtCdt + 2mRdtCgt (3)
By making the gate width GW1 of the first inverter INV1 and the dummy inverter DINV1 1 / (2m) times the gate width GW2 of the second inverter INV2, the CR time constant on the positive phase side becomes equal to that on the negative phase side. be able to.

  Thus, the above equations (2) and (3) have equal CR time constants. As a result, in the single phase differential conversion circuit of the first embodiment of FIG. 3, the phase difference between the positive phase output signal OUTp on the positive phase side and the negative phase output signal OUTx on the negative phase side is exactly 180 °. It has a reverse phase relationship with no phase shift from the phase difference.

As can be understood from the above equation (1), when the gate width of the transistor of the CMOS inverter is increased, the output resistance is decreased, but the gate capacitance and the drain capacitance are increased. Therefore, in the single-phase differential conversion circuit of FIG. 3, the gate widths of the fourth to sixth inverters on the reverse phase side are changed from GW3 = a at the first stage to GW4 = ma at the next stage, and GW5 = m ^{2 at the} next stage. a and a geometric sequence increasing with a multiplication factor m. By setting in this way, the CR time constants of the inverters INV4 and INV5 can be made equal to each other.

  On the other hand, the gate of the second inverter INV2 and the drain of the dummy inverter DINV1 are connected to the output terminal n1 of the first inverter INV1 on the positive phase side. It becomes a constant. This CR time constant is equal to Equation (2) on the opposite phase side.

  Further, the CR time constants CRp and CRx in the above formulas (2) and (3) include the multiplication factor m, but the relationship of positive phase CR time constant = reverse phase CR time constant is the capacity Cgt, Cdt, output resistance Rdt. This holds regardless of the value of the unit gate width a. This means that even if the transistor characteristics vary due to process variations, there is no effect on the phase shift between the normal phase and the reverse phase. Therefore, the normal-phase output signal and the negative-phase output signal match with a phase difference of 180 degrees without depending on process variations.

  FIG. 6 is a diagram for explaining the relationship between the gate width of a transistor and the number of fingers. FIG. 6 shows a plan view of three types of transistors. FIG. 6A shows an example in which a drain D and a source S are provided on both sides of the gate electrode G, and the gate width is GW = 1. The gate width is the width of the region facing the source and drain of the gate electrode.

  FIG. 6B shows an example in which the gate width is GW = 2, the source S is disposed on both sides of the drain D, and one gate electrode G is provided between the drain D and the source S on both sides. ing. This transistor has the same structure as that of FIG. 6A in which two gate electrodes G are provided.

  FIG. 6C shows an example in which the gate width is GW = 2, and there is one gate electrode G, but it has a length twice that of the gate electrode G of the transistor in FIG.

  In general, when the transistor having the structure shown in FIG. 6B is used as one unit and N transistors having this structure are provided in parallel and the gate G, drain D, and source S are connected in parallel, the gate width GW is increased. be able to. Therefore, a transistor in which N 1-unit transistors are provided in parallel is referred to as a transistor having N fingers.

  The above-described gate width GW can be replaced with the number N of fingers described above to define the transistor structures of the first to fifth inverters. In that case, the gate capacitance Cg and the drain capacitance Cd are proportional to the number of fingers N, and the output resistance Rd is inversely proportional to the number of fingers N.

  FIG. 7 is a diagram illustrating a simulation result of the single-phase differential conversion circuit according to the first embodiment. 7A is an example of the embodiment of FIG. 3, and FIGS. 7B and 7C are comparative examples. The waveforms of the positive phase output signal OUTp and the negative phase output signal OUTx are shown, respectively. A solid line is a normal phase output signal and a broken line is a reverse phase output signal. Both waveforms are clock signals that rise and fall between an L level (0 V) and an H level (1.2 V).

  In the embodiment shown in FIG. 7A, the time difference between the positive phase signal and the negative phase signal at an intermediate voltage of 0.6 V at the L and H levels is 2.4 ps. On the other hand, in the comparative examples of FIGS. 7B and 7C, the time difference is as long as 5.5 ps and 10.2 ps.

  7A is an example in which m = 1 and a = 4 in FIG. 3, and the gate widths (or the number of fingers) of the inverters INV1, DINV1, INV2, INV3, INV4, and INV5 are the same. It is an example of 2,2,4,4,4,4.

  FIG. 8 is a circuit diagram of the comparative example of FIG. This comparative example includes five inverters INV1 to INV5. The comparative example of FIG. 7B is an example in which the gate widths GW of the transistors of the five inverters are all 4, and the comparative example of FIG. 7C is that the gate width GW of only the inverter INV1 is 2, This is an example in which the gate width GW of the transistors of the inverters INV2 to INV5 is 4. That is, the comparative example of FIG. 7C is an example in which the delay time is increased by reducing the gate width of the first inverter INV1.

  9 and 10 are circuit diagrams of specific examples of the single-phase differential conversion circuit according to the first embodiment. Each of them has a first inverter INV1, a dummy inverter DINV1, and second to fifth inverters INV2 to INV5, and the gate width GW of the transistors of these inverters is shown in the drawing.

  In the specific example of FIG. 9A, m = 1 and a = 2, and GW1, GWd, GW2, GW3, GW4, and GW5 are 1, 1, 2, 2, 2, and 2. In the specific example of FIG. 9B, m = 2 and a = 1, and GW1, GWd, GW2, GW3, GW4, and GW5 are 1, 1, 4, 1, 2, and 4, respectively. Further, in the specific example of FIG. 10, m = 1/2 and a = 4, and GW1, GWd, GW2, GW3, GW4, and GW5 are 1,1,1,4,2,1.

  In addition to the above, GW1, GWd, GW2, GW3, GW4, GW5 are examples of 2, 2, 16, 1, 4, 16 (m = 4, a = 1), 3, 3, 18, 2, 6 , 18 examples (m = 3, a = 2) are also possible. However, when the integer ratio is increased, the number of unit transistors in FIG.

  In addition to the two inverters on the positive phase side and one dummy inverter, and the three inverters on the negative phase side, the single-phase differential conversion circuit 10 in FIG. May be added to the output. However, the CR time constants of the M inverters added are required to be equal. Further, the number of inverter stages is one more in the second inverter row on the negative phase side than in the first inverter row on the positive phase side. Further, in the single-phase differential conversion circuit 10 of FIG. 3, when a high-frequency single-phase signal is converted into a differential signal, the multiplication factor m is preferably m> 1. This is because by setting m> 1, the gate width of the subsequent inverter becomes larger and the high-frequency signal can be driven appropriately. However, even when m <1, it is possible to drive high-frequency signals by providing inverter circuits with large drive capability and equal delay time for the positive-phase output and reverse-phase output of the single-phase differential conversion circuit. It is.

FIG. 11 is a circuit diagram of a single-phase differential conversion circuit according to the second embodiment. This single-phase differential conversion circuit 10 includes first and second inverters INV11 and INV12 between an input terminal 11 and a positive-phase output terminal 12, as in the first embodiment of FIG. Between the input terminal 11 and the negative phase output terminal 13, third, fourth, and fifth inverters INV3, INV4, and INV5 are provided. The output terminal n11 of the first inverter INV11 is connected to the drain terminal dn11 of the first dummy inverter DINV11 whose gate and source are connected and the gate terminal dg12 of the second dummy inverter DINV12. The drain terminal of the second inverter DINV12 is not connected to any of the terminals of the first to fifth inverters INV11 to INV15 and the terminal of the first dummy inverter DINV1. However, the drain terminal of the second inverter DINV12 may be connected to another output terminal (not shown). Then, the relationship between the gate width GW of the respective inverter, as ^{shown, GW11 = ma, GWd11 = ma} , GWd12 = m 2 a, GW12 = m 2 a, GW13 = a, GW14 = ma, GW15 = m 2 a. That is, the gate widths of the inverters INV12, INV13, INV14, INV15 of the single-phase differential conversion circuit of FIG. 11 are the same as those of the first embodiment of FIG. However, in the case of the single-phase differential conversion circuit of FIG. 11, the gate width GW11 of the first inverter INV1 is larger than the example of FIG. 4 corresponding to ma, and correspondingly, the drain capacitances of the two dummy inverters DINV11 and DINV12 A gate capacitor is connected to the output terminal n11 of the first inverter INV1.

In the single-phase differential conversion circuit of FIG. 11, the CR time constant CRp on the positive phase side and the CR time constant CRx on the negative phase side are as follows. CRx is the same as the above formula (2).
CRp
= (Rdt / ma) × {(Cdt × ma) + (Cdt × ma) + (Cgt × m ² a) + (Cgt × m ² a)}
= 2RdtCdt + 2mRdtCgt (4)
CRx
= (Rdt / a) × (Cdt × a + Cgt × ma) + (Rdt / ma) × (Cdt × ma + Cgt × m ² a)
= (RdtCdt + mRdtCgt) + (RdtCdt + mRdtCgt)
= 2RdtCdt + 2mRdtCgt (2)
As described above, CRp = CRx, and the delay time on the positive phase side is equal to the delay time on the negative phase side. Moreover, the relationship of normal phase CR time constant = reverse phase CR time constant is established irrespective of the values of Cgt, Cdt, Rdt, and a. As a result, there is no variation in delay time due to process variations, and the normal phase output signal and the negative phase output signal coincide with each other with a phase difference of 180 ° regardless of the process variation.

  12 and 13 are circuit diagrams of specific examples of the single-phase differential conversion circuit according to the second embodiment. Each of them has first to fifth inverters INV11 to INV15, a first dummy inverter DINV11, and a second dummy inverter DINV12, and the gate width GW of the transistors of these inverters is shown in the figure. ing.

  In the specific example of FIG. 12A, m = 1 and a = 2, and GW11, GWd11, GWd12, GW12, GW13, GW14, and GW15 are 2, 2, 2, 2, 2, 2, 2. It is. That is, in this specific example, the transistor sizes of all inverters can be set equal.

  In the specific example of FIG. 12B, m = 2 and a = 1, and GW11, GWd11, GWd12, GW12, GW13, GW14, and GW15 are 2, 2, 4, 4, 1, 2, 4, respectively. It is. In this example, since the transistor size of the final stage is large, it is suitable for high-frequency signals.

  Further, in the specific example of FIG. 13, m = 1/2 and a = 4, and GW11, GWd11, GWd12, GW12, GW13, GW14, and GW15 are 2, 2, 1, 1, 4, 2, 1.

  In any of the above combinations, the delay times on the positive phase side and the negative phase side are equal, and the phase difference between the positive phase output signal and the negative phase output signal is exactly 180 °.

  Also in the case of the second embodiment, in addition to the inverter shown in FIG. 11, the same inverter may be added to the input or output on the positive phase side and the negative phase side. However, the CR time constants of the added inverters are required to be equal. Further, the number of inverter stages is one more in the second inverter row on the negative phase side than in the first inverter row on the positive phase side.

11: input terminal 12: normal phase output terminal 13: reverse phase output terminal IN: single phase input signal OUTp: normal phase output signal OUTx: reverse phase output signals INV1 to INV5: first to fifth inverters DINV1: dummy inverter INV11 INV15: first to fifth inverters DINV11 to DINV12 in the second embodiment: first to second dummy inverters in the second embodiment

Claims (3)

An input terminal to which a single-phase input signal is input;
A positive phase output terminal for outputting a positive phase output signal;
A negative phase output terminal from which a negative phase output signal in a differential relationship with the positive phase output signal is output;
A first inverter row provided between the input terminal and the positive phase output terminal and including at least first and second inverters connected in series;
A second inverter provided between the input terminal and the negative-phase output terminal and including at least third, fourth, and fifth inverters connected in series and having one more stage than the first inverter row; And
It said first inverter string, further wherein the drain to the output terminal of the first inverter are connected, have a dummy inverter having a transistor with a gate connected to a voltage that does not conduct,
A ratio of gate widths of the first, second, dummy, third, fourth, and fifth inverters is m / 2: m ² : m / 2: 1: m: m ² , where m is an inverter. Single-phase differential conversion circuit that is a multiplication factor of . An input terminal to which a single-phase input signal is input;
A positive phase output terminal for outputting a positive phase output signal;
A negative phase output terminal for outputting a negative phase output signal opposite to the positive phase output signal;
A first inverter row provided between the input terminal and the positive phase output terminal and including at least first and second inverters connected in series;
A second inverter provided between the input terminal and the negative-phase output terminal and including at least third, fourth, and fifth inverters connected in series and having one more stage than the first inverter row; And
The first inverter train further includes:
A first dummy inverter having a transistor having a transistor with a drain connected to the output terminal of the first inverter and a gate connected to a non-conductive voltage; and a gate connected to the output terminal of the first inverter; have a second dummy inverter having a transistor,
A ratio of gate widths of the first, second, first dummy, second dummy, third, fourth, and fifth inverters is m: m ² : m: m ² : 1: m: m ^2. Wherein m is a single-phase differential conversion circuit which is a multiplication factor of the inverter . In claim 1 or 2 ,
The single-phase differential conversion circuit, wherein output terminals of the second and third inverters are respectively connected to the positive-phase output terminal and the negative-phase output terminal having the same load capacity.

Images