JP3629146B2 - RC delay circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit, and more particularly to an RC delay circuit formed in an integrated circuit having a MOS structure, and is used for a memory such as a DRAM or SRAM, a logic gate, or a CPU.
[0002]
[Prior art]
13 and 16 show Conventional Example 1 and Conventional Example 2 of an RC delay circuit using a CMOS inverter formed in an integrated circuit having a MOS structure.
[0003]
<Conventional example 1>
In the RC delay circuit shown in FIG. 13, a plurality (two in this example) of delay circuits 131 are connected in series, and this delay circuit 131 is RC between two stages of CMOS inverters IV1 and IV2. The circuit 130 is inserted. in this case, the above As shown in FIG. 25, the CMOS inverters IV1 and IV2 are formed by connecting the drains of the PMOS transistor TP and the NMOS transistor TN and connecting the gates thereof.
[0004]
In the RC circuit 130, a resistor element R and an NMOS capacitor C are connected in series, one end side of the resistor element is connected to the output node of the preceding CMOS inverter IV1, and the other end side of the resistor element is the next stage CMOS. It is connected to the input node of the inverter IV2. That is, one end side of the resistor element is connected to the drain of the NMOS transistor (not shown) of the preceding CMOS inverter IV1, and the other end side of the resistor element is a PMOS transistor (not shown) of the next stage CMOS inverter IV2. Connected to the gate.
[0005]
<Conventional example 2>
The RC delay circuit shown in FIG. 16 has a plurality (two in this example) of delay circuits 161 connected in series, and this delay circuit 161 is connected between the two stages of CMOS inverters IV1 and IV2. The circuit 160 is inserted. In this case, in the RC circuit 160, the resistor element R and the PMOS capacitor C are connected in series, one end side of the resistor element is connected to the output node of the preceding CMOS inverter IV1, and the other end side of the resistor element is the next stage CMOS. It is connected to the input node of the inverter IV2. That is, one end side of the resistance element is connected to the drain of a PMOS transistor (not shown) of the preceding CMOS inverter IV1, and the other end side of the resistance element is an NMOS transistor (not shown) of the next stage CMOS inverter IV2. Connected to the gate.
[0006]
However, the RC delay circuit of Conventional Example 1 shown in FIG. 13 and the RC delay circuit of Conventional Example 2 shown in FIG. 16 are different in the absolute value of the threshold value of the PMOS transistor of the CMOS inverter and the threshold value of the NMOS transistor due to variations in the manufacturing process. There is a problem that the delay time also varies when the absolute values of are varied in opposite directions, which will be described in detail below.
[0007]
Regarding the RC delay circuit shown in FIG. 13 and FIG. 16, (a) the threshold value VTP of the PMOS transistor is a design value (for example, −0.6 V) and the threshold value VTN of the NMOS transistor is a design value (for example, 0.5 V); (B) When the absolute value | VTP | of the PMOS transistor increases by 0.2V and the absolute value | VTN | of the NMOS transistor decreases by, for example, 0.2V due to process variations (VTP is −0.8V, (When VTN is 0.3 V) and (c) the absolute value | VTP | of the PMOS transistor is decreased by 0.2 V due to process variations, and the threshold of the NMOS transistor is increased by, for example, 0.2 V (VTP is − Input / output when the input signal voltage is changed from “L” level to “H” level. The simulation result of the voltage waveform of the waveform and major nodes of voltage 14, 15, 17, shown in FIG. 18.
[0008]
14 (a), 14 (b), and 14 (c) show the case in which the threshold value of the MOS transistor of the RC delay circuit of Conventional Example 1 shown in FIG. In this case, the simulation waveforms of the input voltage Vin2 and the output voltage Vout2 are shown for the case of variation as in (c) described above.
[0009]
FIGS. 15A, 15B and 15C show the case where the threshold value of the MOS transistor of the RC delay circuit of the conventional example 1 shown in FIG. In the case of such variations, the simulation waveforms of the voltages Vin2, V15, V16, V18, and V19 at the main nodes are shown for the case of variations as in (c) described above. Here, t5 represents a signal transmission time from the input voltage Vin2 to the intermediate node voltage V16, and t6 represents a signal transmission time from the intermediate node voltage V16 to the intermediate node voltage V19.
[0010]
That is, in the RC delay circuit of Conventional Example 1 shown in FIG. 13, as can be seen from FIGS. 14A, 14B, and 14C, the absolute value of the threshold value of the PMOS transistor and the absolute value of the threshold value of the NMOS transistor are When the values fluctuate in opposite directions, the input / output waveform (input / output characteristics) fluctuates greatly. The reason for this will be described below.
[0011]
1) When the absolute value of the threshold value of the PMOS transistor increases by 0.2V and the absolute value of the threshold value of the NMOS transistor decreases by 0.2V.
[0012]
The circuit threshold value of the inverter IV2 of the delay circuit 131 in the preceding stage in FIG. 13 decreases, and the delay of the signal transmission time t5 increases as shown in FIG. In addition, the circuit threshold value of the inverter IV2 in the delay circuit 131 in the subsequent stage in FIG. 13 also decreases, and the delay of the signal transmission time t6 increases as shown in FIG. 15B. Therefore, the sum of the signal transmission times t5 and t6 is larger than when the threshold value is a design value.
[0013]
2) When the absolute value of the threshold value of the PMOS transistor decreases by 0.2V and the absolute value of the threshold value of the NMOS transistor increases by 0.2V.
[0014]
The circuit threshold value of the inverter IV2 of the delay circuit 131 in the preceding stage in FIG. 13 is increased, and the delay of the signal transmission time t5 is reduced as shown in FIG. Further, the circuit threshold value of the inverter IV2 in the delay circuit 131 in the latter stage in FIG. 13 also increases, and the delay of the signal transmission time t6 is reduced as shown in FIG. Therefore, the sum of the signal transmission times t5 and t6 is smaller than when the threshold value is a design value.
[0015]
On the other hand, FIGS. 17A, 17B, and 17C show the case where the threshold value of the MOS transistor of the RC delay circuit of Conventional Example 2 shown in FIG. ), The simulation waveforms of the input voltage Vin3 and the output voltage Vout3 are shown for the case of variation as in (c) described above.
[0016]
18 (a), 18 (b), and 18 (c) show the above-described case (b) when the threshold value of the MOS transistor of the RC delay circuit of the conventional example 2 shown in FIG. In this case, the simulation waveforms of the voltages V21, V23, V24, V26, and V27 of the main nodes are shown for the case of the variation as in (c) described above. Here, t7 represents a signal transmission time from the input voltage Vin3 to the intermediate node voltage V24, and t8 represents a signal transmission time from the intermediate node voltage V24 to the intermediate node voltage V27.
[0017]
That is, in the RC delay circuit of Conventional Example 2 shown in FIG. 16, as can be seen from FIGS. 17A, 17B and 17C, the absolute value of the threshold value of the PMOS transistor and the absolute value of the threshold value of the NMOS transistor When the values fluctuate in opposite directions, the input / output waveform (input / output characteristics) fluctuates greatly. The reason for this will be described below.
[0018]
1) When the absolute value of the threshold value of the PMOS transistor increases by 0.2V and the absolute value of the threshold value of the NMOS transistor decreases by 0.2V.
[0019]
The circuit threshold value of the inverter IV2 of the preceding delay circuit 161 in FIG. 16 decreases, and the delay of the signal transmission time t7 decreases as shown in FIG. 18B. Further, the circuit threshold value of the inverter IV2 in the delay circuit 161 in the subsequent stage in FIG. 16 is also lowered, and the delay of the signal transmission time t8 is also reduced as shown in FIG. 18B. Therefore, the sum of the signal transmission times t7 and t8 is smaller than when the threshold value is a design value.
[0020]
2) When the absolute value of the threshold value of the PMOS transistor decreases by 0.2V and the absolute value of the threshold value of the NMOS transistor increases by 0.2V.
[0021]
The circuit threshold value of the inverter IV2 in the delay circuit 161 in the preceding stage in FIG. 16 increases, and the delay of the signal transmission time t7 increases as shown in FIG. 18 (c). Further, the circuit threshold value of the inverter IV2 in the delay circuit 161 in the latter stage in FIG. 16 also increases, and the delay of the signal transmission time t8 increases as shown in FIG. 18C. Therefore, the sum of the signal transmission times t7 and t8 is larger than when the threshold value is a design value.
[0022]
19 and 22 show Conventional Example 3 and Conventional Example 4 of an RC delay circuit using a modified CMOS inverter formed in an integrated circuit having a MOS structure.
[0023]
<Conventional example 3>
The RC delay circuit shown in FIG. 19 has a plurality (two in this example) of delay circuits 191 connected in series, and this delay circuit 191 is a resistance element between the drains of the PMOS transistor TP and the NMOS transistor TN. A modified CMOS inverter IV1a in which R is inserted and the gates are connected, an NMOS capacitor C connected between the drain of the PMOS transistor TP and the ground node, and an input node is connected to the drain of the PMOS transistor TP. And a next-stage CMOS inverter IV2. In this case, an RC circuit is formed by the resistance element R of the modified CMOS inverter IV1a and the NMOS capacitor C.
[0024]
That is, one end side of the resistance element R of the RC circuit is connected to the drain of the NMOS transistor TN of the former-stage modified CMOS inverter IV1a, and the other end side of the resistance element R is a PMOS transistor (not shown) of the next-stage CMOS inverter IV2. )) Is connected to the gate.
[0025]
<Conventional Example 4>
The RC delay circuit shown in FIG. 22 has a plurality (two in this example) of delay circuits 221 connected in series, and this delay circuit 221 is a resistance element between the drains of the PMOS transistor TP and the NMOS transistor TN. An input node is connected to the modified CMOS inverter IV1a in which R is inserted and the gates are connected, a PMOS capacitor C connected between the drain TN and the VCC node of the NMOS transistor, and a drain of the NMOS transistor TN. And a next-stage CMOS inverter IV2. In this case, an RC circuit is formed by the resistance element R of the modified CMOS inverter IV1a and the PMOS capacitor C.
[0026]
That is, one end side of the resistance element R of the RC circuit is connected to the drain of the PMOS transistor TP of the modified CMOS inverter IV1a at the previous stage, and the other end side of the resistance element R is an NMOS transistor (not shown) of the CMOS inverter IV2 at the next stage. )) Is connected to the gate.
[0027]
However, also in the RC delay circuit of Conventional Example 3 shown in FIG. 19 and the RC delay circuit of Conventional Example 4 shown in FIG. 22, the absolute value of the threshold value of the PMOS transistor of the CMOS inverter and the NMOS transistor due to variations in the manufacturing process. When the absolute value of the threshold value varies in the opposite direction, there is a problem that the delay time also varies, which will be described in detail below.
[0028]
20 (a), 20 (b), and 20 (c) show the case where the threshold value of the MOS transistor of the RC delay circuit of the conventional example 3 shown in FIG. In this case, the simulation waveforms of the input voltage Vin2 and the output voltage Vout2 are shown for the case of variation as in (c) described above.
[0029]
FIGS. 21A, 21B and 21C show the case where the threshold value of the MOS transistor of the RC delay circuit of the conventional example 3 shown in FIG. 19 is the above-described design value (a). In the case of such variation, the simulation waveforms of the voltages Vin2, V10, V11, V12, and V13 of the main nodes are shown for the case of variation as in (c) described above. Here, t5 represents a signal transmission time from the input voltage Vin2 to the intermediate node voltage V11, and t6 represents a signal transmission time from the intermediate node voltage V11 to the intermediate node voltage V13.
[0030]
That is, in the RC delay circuit of Conventional Example 3 shown in FIG. 19, as can be seen from FIGS. 20A, 20B, and 20C, the absolute value of the threshold value of the PMOS transistor and the absolute value of the threshold value of the NMOS transistor are When the values fluctuate in opposite directions, the input / output waveform (input / output characteristics) fluctuates greatly. The reason for this will be described below.
[0031]
1) When the absolute value of the threshold value of the PMOS transistor increases by 0.2V and the absolute value of the threshold value of the NMOS transistor decreases by 0.2V.
[0032]
The circuit threshold value of the inverter IV2 of the delay circuit 191 in the preceding stage in FIG. 19 decreases, and the delay of the signal transmission time t5 increases as shown in FIG. Further, the circuit threshold value of the inverter IV2 in the latter delay circuit 191 in FIG. 19 also decreases, and the delay of the signal transmission time t6 also increases as shown in FIG. Therefore, the sum of the signal transmission times t5 and t6 is larger than when the threshold value is a design value.
[0033]
2) When the absolute value of the threshold value of the PMOS transistor decreases by 0.2V and the absolute value of the threshold value of the NMOS transistor increases by 0.2V.
[0034]
The circuit threshold value of the inverter IV2 of the preceding delay circuit 191 in FIG. 19 increases, and the delay of the signal transmission time t5 becomes smaller as shown in FIG. 21 (c). Further, the circuit threshold value of the inverter IV2 of the latter delay circuit 191 in FIG. 19 is also increased, and the delay of the signal transmission time t6 is reduced as shown in FIG. 21 (c). Therefore, the sum of the signal transmission times t5 and t6 is smaller than when the threshold value is a design value.
[0035]
On the other hand, FIGS. 23A, 23B and 23C show the case where the threshold value of the MOS transistor of the RC delay circuit of the conventional example 4 shown in FIG. ), The simulation waveforms of the input voltage Vin3 and the output voltage Vout3 are shown for the case of variation as in (c) described above.
[0036]
FIGS. 24A, 24B, and 24C show the case where the threshold value of the MOS transistor of the RC delay circuit of the conventional example 4 shown in FIG. 22 is the above-described design value (a). In the case of such variation, the simulation waveforms of the voltages V15, V16, V17, V18, and V19 of the main nodes are shown for the case of variation as in (c) described above. Here, t7 represents a signal transmission time from the input voltage Vin3 to the intermediate node voltage V17, and t8 represents a signal transmission time from the intermediate node voltage V17 to the intermediate node voltage V19.
[0037]
That is, in the RC delay circuit of Conventional Example 4 shown in FIG. 22, as can be seen from FIGS. 23 (a), (b), and (c), the absolute value of the threshold value of the PMOS transistor and the absolute value of the threshold value of the NMOS transistor When the values fluctuate in opposite directions, the input / output waveform (input / output characteristics) fluctuates greatly. The reason for this will be described below.
[0038]
1) When the absolute value of the threshold value of the PMOS transistor increases by 0.2V and the absolute value of the threshold value of the NMOS transistor decreases by 0.2V.
[0039]
The circuit threshold value of the inverter IV2 of the preceding delay circuit 221 in FIG. 22 decreases, and the delay of the signal transmission time t7 decreases as shown in FIG. Further, the circuit threshold value of the inverter IV2 of the latter delay circuit 221 in FIG. 22 also decreases, and the delay of the signal transmission time t8 also decreases as shown in FIG. Therefore, the sum of the signal transmission times t7 and t8 is smaller than when the threshold value is a design value.
[0040]
2) When the absolute value of the threshold value of the PMOS transistor decreases by 0.2V and the absolute value of the threshold value of the NMOS transistor increases by 0.2V.
[0041]
The circuit threshold value of the inverter IV2 of the preceding delay circuit 221 in FIG. 22 increases, and the delay of the signal transmission time t7 increases as shown in FIG. Further, the circuit threshold value of the inverter IV2 in the delay circuit 221 in the latter stage in FIG. 22 also increases, and the delay of the signal transmission time t8 also increases as shown in FIG. Therefore, the sum of the signal transmission times t7 and t8 is larger than when the threshold value is a design value.
[0042]
[Problems to be solved by the invention]
As described above, in the conventional RC delay circuit, when the absolute value of the threshold value of the PMOS transistor and the absolute value of the threshold value of the NMOS transistor included in the circuit vary in opposite directions, the delay time also varies. was there.
[0043]
The present invention has been made to solve the above problems, and even when the absolute value of the threshold value of the PMOS transistor and the absolute value of the threshold value of the NMOS transistor included in the circuit vary in opposite directions, the delay time varies. An object of the present invention is to provide an RC delay circuit with less delay.
[0044]
[Means for Solving the Problems]
The RC delay circuit according to the first aspect of the present invention is provided with at least one set of unit delay circuits in which a first delay circuit and a second delay circuit are connected in series, and the first delay circuit includes: An input circuit, a first RC circuit in which a first resistor element and a first capacitor are connected in series to an output node of the first input circuit, and the first resistor element and the first capacitor A first CMOS inverter circuit having an input node connected to the series connection node, and the second delay circuit includes a second resistor at a second input circuit and an output node of the second input circuit. A second RC circuit in which an element and a second capacitor are connected in series; and a second CMOS inverter circuit in which an input node is connected to a series connection node of the second resistor element and the second capacitor. Become Characterized in that the transition direction of the input potential of the transition direction between the second CMOS inverter circuit of an input potential of the first CMOS inverter circuit with the transition of the logic level of the signal is reverse.
[0045]
The RC delay circuit of the second invention is provided with at least one unit delay circuit in which a first delay circuit and a second delay circuit are connected in series, and the first delay circuit includes: A first input circuit in which a first resistance element is inserted between the drains of the PMOS transistor and the first NMOS transistor, and the gates of the first PMOS transistor and the first NMOS transistor are connected to each other; A first capacitor connected between the drain of the first PMOS transistor and the discharge potential node and forming a first RC circuit together with the first resistance element; and an input node at the drain of the first PMOS transistor Are connected to each other, and the second delay circuit includes a second PMOS transistor and a second NMOS transistor. A second input element in which a second resistance element is inserted between the drains of the transistors and the gates of the second PMOS transistor and the second NMOS transistor are connected to each other; and a drain of the second NMOS transistor; A second capacitor connected between the charge potential node and forming a second RC circuit together with the second resistance element; and a second CMOS having an input node connected to the drain of the second NMOS transistor And an inverter circuit.
[0046]
According to a third aspect of the present invention, there is provided an RC delay circuit including at least one unit delay circuit in which a first delay circuit and a second delay circuit are connected in series, wherein the first delay circuit includes: A first resistance element and a second resistance element are inserted in series between the drains of the PMOS transistor and the first NMOS transistor, and the gates of the first PMOS transistor and the first NMOS transistor are connected to each other. A first input circuit; a first capacitor connected between a series connection node of the first resistance element and the second resistance element; and a discharge potential node; the first resistance element; An input node is connected to the second capacitor connected between the series connection node of the resistance element and the charging potential node, and the series connection node of the first resistance element and the second resistance element. The second delay circuit includes a third resistance element and a fourth resistance element inserted in series between the drains of the second PMOS transistor and the second NMOS transistor. A second input circuit in which the gates of the second PMOS transistor and the second NMOS transistor are connected to each other, and a series connection node of the third resistance element and the fourth resistance element and a discharge potential node. A third capacitor connected to the first capacitor; a fourth capacitor connected between a series connection node of the third resistor element and the fourth resistor element; and a charging potential node; the third resistor element; And a second CMOS inverter circuit having an input node connected to a series connection node of the fourth resistance element.
[0047]
An RC delay circuit according to a fourth aspect of the present invention is the first delay circuit and the second delay circuit each including an RC circuit in which a resistance element and a capacitor are connected in series in the integrated circuit. The first delay circuit is connected in series, and the first delay circuit includes a first RC circuit in which a first resistor element and a first capacitor are connected in series, and a series of the first resistor element and the first capacitor. A first RC inverter having an input node connected to a connection node, and the second delay circuit includes a second RC circuit in which a second resistance element and a second capacitor are connected in series; A second CMOS inverter having an input node connected to a series connection node of the second resistance element and the second capacitor; As the logic level of the input signal transitions, A serial connection node of the first resistance element of the first RC circuit and the first capacitor Potential and A serial connection node of the second resistance element of the second RC circuit and the second capacitor The potential of transitions in the opposite direction Is configured as It is characterized by that.
[0048]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0049]
<First embodiment>
FIG. 1 shows an RC delay circuit according to a first embodiment of the present invention.
[0050]
The RC delay circuit shown in FIG. 1 includes at least a delay circuit in which two types of delay circuits 11 and 12 are connected in series via an odd-numbered stage (one stage in this example) CMOS inverter circuit 13 in an integrated circuit. One set (one set in this example) is provided.
[0051]
The first delay circuit 11 in the delay circuit is formed by inserting a first RC circuit 110 between the two stages of CMOS inverters IV1 and IV2. In this case, the CMOS inverters IV1 and IV2 are connected in series between the source and drain of the PMOS transistor TP and between the drain and source of the NMOS transistor TN between the VCC node and the ground node, respectively, for example, as shown in FIG. The PMOS transistor TP and the NMOS transistor TN have a normal configuration in which the gates are connected to each other.
[0052]
In the first RC circuit 110, the resistor element R and the NMOS capacitor Cn are connected in series, one end side of the resistor element R is connected to the output node of the preceding CMOS inverter IV1, and the other end side of the resistor element R is connected to the first RC circuit 110. It is connected to the input node of the next stage CMOS inverter IV2.
[0053]
That is, one end side of the resistor element R is connected to the drain of the NMOS transistor TN of the preceding CMOS inverter IV1, and the other end side of the resistor element R is connected to the gate of the PMOS transistor TP of the next stage CMOS inverter IV2. Yes.
[0054]
The second delay circuit 12 in the delay circuit includes a second RC circuit 120 inserted between the two stages of CMOS inverters IV1 and IV2. In this case, in the second RC circuit 120, the resistor element R and the PMOS capacitor Cp are connected in series, and one end side of the resistor element R is connected to the output node of the CMOS inverter IV1 in the previous stage. The end side is connected to the input node of the next stage CMOS inverter IV2.
[0055]
That is, one end side of the resistor element R is connected to the drain of the PMOS transistor TP of the preceding CMOS inverter IV1, and the other end side of the resistor element R is connected to the gate of the NMOS transistor TN of the next stage CMOS inverter IV2. Yes.
[0056]
Here, regarding the RC delay circuit according to the first embodiment shown in FIG. 1, (a) the threshold value VTP of the PMOS transistor is a design value (for example, −0.6 V) and the threshold value VTN of the NMOS transistor is a design value (for example, 0. 5V) and (b) the case where the absolute value | VTP | of the PMOS transistor increases by 0.2V and the absolute value | VTN | of the NMOS transistor decreases by, for example, 0.2V due to process variations (VTP) (When V is -0.8V and VTN is 0.3V), and (c) due to process variations, the absolute value | VTP | of the PMOS transistor is decreased by 0.2V, and the threshold of the NMOS transistor is increased by 0.2V, for example. In this case (when VTP is −0.4V and VTN is 0.7V), the input signal voltage is changed from “L” level to “H” level. The simulation results of the waveform of the output voltage of the multiplexer and voltage waveforms of the major nodes shown in FIGS.
[0057]
2 (a), 2 (b), and 2 (c) show the case (b) when the threshold value of the MOS transistor of the RC delay circuit of the first embodiment shown in FIG. The simulation waveforms of the input voltage Vin0 and the output voltage Vout0 are shown for the case of variation as shown in FIG.
[0058]
FIGS. 3A, 3B, and 3C show the case where the threshold value of the MOS transistor of the RC delay circuit of the first embodiment shown in FIG. 1 is the above-described design value (b). The simulation waveforms of the voltages Vin0, V1, V2, V3, V5, and V6 of the main nodes are shown for the case where the variation is as shown in FIG.
[0059]
Here, t1 represents a signal transmission time from the input voltage Vin0 to the intermediate node voltage V2, and t2 represents a signal transmission time from the intermediate node voltage V3 to the intermediate node voltage V6.
[0060]
When the simulation result of the RC delay circuit of the first embodiment is compared with the simulation result of the RC delay circuit of the conventional example 1, the absolute value of the threshold value of the PMOS transistor and the threshold value of the NMOS transistor are compared in the RC delay circuit of the conventional example 1. The input / output characteristics fluctuate greatly when the absolute values of the NMOS transistors vary in opposite directions. However, in the RC delay circuit of the first embodiment, the absolute value of the threshold value of the PMOS transistor and the absolute value of the threshold value of the NMOS transistor are different. Even when they vary in the opposite directions, the input / output characteristics hardly change as shown in FIGS. 2 (a), 2 (b), and 2 (c).
[0061]
The reason is described.
[0062]
1) When the absolute value of the threshold value of the PMOS transistor increases by 0.2V and the absolute value of the threshold value of the NMOS transistor decreases by 0.2V.
[0063]
The circuit threshold value of the inverter IV2 of the first delay circuit 11 in FIG. 1 decreases, and the delay of the signal transmission time t1 increases as shown in FIG. 3B. On the other hand, the circuit threshold value of the inverter IV2 of the second delay circuit 12 in FIG. 1 also decreases, and the delay of the signal transmission time t2 becomes small as shown in FIG. 3B. In this case, the sum of the signal transmission times t1 and t2 is substantially equal to the case where the threshold value is a design value.
[0064]
2) When the absolute value of the threshold value of the PMOS transistor decreases by 0.2V and the absolute value of the threshold value of the NMOS transistor increases by 0.2V.
[0065]
The circuit threshold value of the inverter IV2 of the first delay circuit 11 in FIG. 1 is increased, and the signal transmission time delay is reduced as shown in FIG. On the other hand, the circuit threshold value of the inverter IV2 of the second delay circuit 12 in FIG. 1 also increases, and the delay of the signal transmission time t2 increases as shown in FIG. In this case, the sum of the signal transmission times t1 and t2 is substantially equal to the case where the threshold value is a design value.
[0066]
In other words, the RC delay circuit of the first embodiment includes the first delay circuit 11 and the second delay circuit respectively including RC circuits 110 and 120 each having a resistance element R and a capacitor Cn or Cp connected in series in the integrated circuit. Delay circuit 12 is provided in series.
[0067]
Along with the transition of the logic level of the input signal to the RC delay circuit, the potential of the connection node between the resistance element R and the capacitor Cn of the RC circuit 110 of the first delay circuit 11 (in this example, the first delay circuit). 11 and the potential VS of the connection node between the resistance element R and the capacitor Cp of the RC circuit 120 of the second delay circuit 12 (in this example, the CMOS inverter circuit of the second delay circuit 12). The input potential (IV2) is shifted in the reverse direction.
[0068]
In this case, the two delay circuits are connected so that the transition direction of the logic level of the input signal of the second delay circuit 12 is opposite to the transition direction of the logic level of the input signal of the first delay circuit 11. An odd number of inverter circuits 13 are inserted therebetween.
[0069]
With such a configuration, even when the absolute value of the threshold value of the PMOS transistor and the absolute value of the threshold value of the NMOS transistor included in the circuit vary in opposite directions, the change in the delay time of the two delay circuits 11 and 12 is As a result, the variation in delay time can be suppressed as a whole.
[0070]
The circuit on the input side in the first delay circuit 11 is not limited to the CMOS inverter IV1, but is an input circuit having an NMOS transistor connected between the resistance element R of the first RC circuit 110 and the discharge potential node. Any CMOS logic circuit (for example, a NAND circuit or a NOR circuit) that logically processes a plurality of input signals may be used.
[0071]
Similarly, the input-side circuit in the second delay circuit 12 is not limited to the CMOS inverter IV1, and an input circuit having a PMOS transistor connected between the resistance element R of the second RC circuit 120 and the charging potential node. Any CMOS logic circuit that logically processes a plurality of input signals may be used.
[0072]
Further, the capacitor in the first RC circuit 110 is not limited to the NMOS capacitor Cn that is used by short-circuiting the drain and source of the NMOS transistor as described above, but may be a capacitor having another configuration. An NMOS capacitor is desirable from the viewpoint of process simplification.
[0073]
Similarly, the capacitor in the second RC circuit 120 is not limited to the PMOS capacitor Cp that is used by short-circuiting the drain and source of the PMOS transistor as described above, but may be a capacitor having another configuration. A PMOS capacitor is desirable from the viewpoint of simplification of the process. It should be noted that the NMOS, PMOS, and capacitive element in the above may have a so-called MIS structure in which the gate insulating film is formed of an insulating film other than an oxide film, and the same applies to the following.
[0074]
Further, in the RC delay circuit of the first embodiment, the first delay circuit 11 including the first RC circuit 110 is provided in the previous stage, and the second delay circuit 12 including the second RC circuit 120 is provided in the subsequent stage. However, a configuration in which the front-rear relationship of the first delay circuit 11 and the second delay circuit 12 is switched may be used.
[0075]
Further, in order to cancel the variation in delay time of the first delay circuit 11 and the variation in delay time of the second delay circuit 12, the resistance value of the resistance element R and the capacitance of the capacitor Cn in the first delay circuit 11 are eliminated. The product of the value and the sum of the input gate capacitance values of the CMOS inverter IV2 is the product of the resistance value of the resistance element R and the capacitance value of the capacitor Cp and the sum of the input gate capacitance values of the CMOS inverter IV2 in the second delay circuit 12 It is desirable that the two are approximately equal to each other.
[0076]
However, the resistance value of the resistance element R of the first delay circuit 11 and the resistance value of the resistance element R of the second delay circuit 12 are set to be substantially equal, and the capacitance value of the capacitor Cn of the first delay circuit 11 is set. And the capacitance value of the capacitor Cp of the second delay circuit 12 are set to be approximately equal so that the size of the PMOS transistor of the first delay circuit 11 and the size of the PMOS transistor of the second delay circuit 12 are approximately equal. It is particularly desirable from the viewpoint of simplification of design to set the size of the NMOS transistor of the first delay circuit 11 and the size of the NMOS transistor of the second delay circuit 12 to be approximately equal.
[0077]
<Second embodiment>
FIG. 4 shows an RC delay circuit according to the second embodiment.
[0078]
Compared with the RC delay circuit of the first embodiment shown in FIG. 1, the RC delay circuit shown in FIG. 4 is (1) a connection node between the resistance element R and the NMOS capacitor Cn in the first delay circuit 41 and a VCC node. (2) An NMOS capacitor Cn is additionally connected between the connection node between the resistance element R and the PMOS capacitor Cp in the second delay circuit 42 and the ground node. The other points are the same.
[0079]
FIGS. 5A, 5B, and 5C show the case where the threshold value of the MOS transistor of the RC delay circuit of the second embodiment shown in FIG. 4 is the above-described design value (a). The simulation waveforms of the input voltage Vin1 and the output voltage Vout1 are shown for the case of variation as shown in FIG.
[0080]
6 (a), 6 (b) and 6 (c) show the case (b) when the threshold value of the MOS transistor of the RC delay circuit of the second embodiment shown in FIG. In this case, the simulation waveforms of the voltages Vin1, V8, V9, V10, V12, and V13 at the main nodes are shown for the case of the variation as described in (c). Here, t3 represents a signal transmission time from the input voltage Vin1 to the intermediate node voltage V9, and t4 represents a signal transmission time from the intermediate node voltage V10 to the intermediate node voltage V13.
[0081]
When the simulation result of the RC delay circuit of the second embodiment is compared with the simulation result of the RC delay circuit of the conventional example 2, the absolute value of the threshold value of the PMOS transistor and the threshold value of the NMOS transistor are compared in the RC delay circuit of the conventional example 2. The input / output waveform (input / output characteristics) fluctuates greatly when the absolute value of the transistor varies in the opposite direction. However, in the RC delay circuit of the second embodiment, the absolute value of the threshold of the PMOS transistor and the threshold of the NMOS transistor Even when the absolute values of the values fluctuate in opposite directions, the input / output waveforms (input / output characteristics) hardly change as shown in FIGS. 5 (a), (b) and (c).
[0082]
The reason is described.
[0083]
1) When the absolute value of the threshold value of the PMOS transistor increases by 0.2V and the absolute value of the threshold value of the NMOS transistor decreases by 0.2V.
[0084]
The circuit threshold value of the inverter IV2 of the first delay circuit 41 in FIG. 4 decreases, and the delay of the signal transmission time t3 increases as shown in FIG. 6B. On the other hand, the circuit threshold value of the inverter IV2 of the second delay circuit 42 in FIG. 4 also decreases, and the delay of the signal transmission time t4 becomes small as shown in FIG. 6B. In this case, the sum of the signal transmission times t3 and t4 is substantially equal to the case where the threshold value is a design value.
[0085]
2) When the absolute value of the threshold value of the PMOS transistor decreases by 0.2V and the absolute value of the threshold value of the NMOS transistor increases by 0.2V.
[0086]
The circuit threshold value of the inverter IV2 of the first delay circuit 41 in FIG. 4 is increased, and the delay of the signal transmission time t3 is reduced as shown in FIG. 6 (c). On the other hand, the circuit threshold value of the inverter IV2 of the second delay circuit 42 in FIG. 4 also increases, and the delay of the signal transmission time t4 increases as shown in FIG. 6C. In this case, the sum of the signal transmission times t3 and t4 is substantially equal to the case where the threshold value is a design value.
[0087]
Therefore, in the RC delay circuit of the second embodiment, as in the RC delay circuit of the first embodiment, the absolute value of the threshold value of the PMOS transistor and the absolute value of the threshold value of the NMOS transistor included in the circuit are opposite to each other. Even in the case of fluctuations, changes in the delay times of the two delay circuits cancel each other, and variations in delay time can be suppressed as a whole.
[0088]
In addition, the RC delay circuit of the second embodiment is different from the RC delay circuit of the first embodiment in that the input signal voltage is changed from “L” level to “H” level and the input signal voltage is “ When the level is changed from the “H” level to the “L” level, substantially the same delay is obtained, and the delay time as a whole is substantially equal even if the threshold voltage of the MOS transistor varies as described above.
[0089]
In the RC delay circuit of the second embodiment, various modifications can be made and appropriate constants can be set in the same manner as the RC delay circuit of the first embodiment described above.
[0090]
<Third embodiment>
FIG. 7 shows an RC delay circuit according to the third embodiment.
[0091]
The RC delay circuit of FIG. 7 differs from the RC delay circuit of the first embodiment shown in FIG.
[0092]
That is, the RC delay circuit shown in FIG. 7 is a delay circuit in which two types of delay circuits 71 and 72 are connected in series via an odd-numbered stage (in this example, one stage) CMOS inverter circuit 73 in an integrated circuit. Are provided at least one set (one set in this example).
[0093]
The first delay circuit 71 in the delay circuit includes a modified CMOS inverter IV1a in which a resistance element R is inserted between the drains of the PMOS transistor TP and the NMOS transistor TN, and the gates of the PMOS transistor and the NMOS transistor are connected to each other. It comprises an NMOS capacitor Cn connected between the drain of the PMOS transistor TP and the ground node, and a CMOS inverter IV2 in the next stage having an input node connected to the drain of the PMOS transistor TP.
[0094]
In this case, a third RC circuit is formed by the resistance element R of the modified CMOS inverter IV1a and the NMOS capacitor Cn. That is, one end side of the resistance element R of the third RC circuit is connected to the drain of the NMOS transistor TN of the former-stage modified CMOS inverter IV1a, and the other end side of the resistance element R is the PMOS transistor of the next-stage CMOS inverter IV2. (TP in FIG. 25) is connected to the gate.
[0095]
The second delay circuit 72 in the delay circuit includes a modified CMOS inverter IV1b in which a resistance element R is inserted between the drains of the PMOS transistor TP and the NMOS transistor TN, and the gates of the PMOS transistor and the NMOS transistor are connected to each other. And a PMOS capacitor Cp connected between the drain of the NMOS transistor TN and the VCC node, and a CMOS inverter IV2 in the next stage having an input node connected to the drain of the NMOS transistor TN.
[0096]
In this case, a fourth RC circuit is formed by the resistance element R of the modified CMOS inverter IV1b and the PMOS capacitor Cn. In other words, one end side of the resistor element R of the fourth RC circuit is connected to the drain of the PMOS transistor TP of the former-stage modified CMOS inverter IV1b, and the other end side of the resistor element R is an NMOS transistor of the next-stage CMOS inverter IV2. (TN in FIG. 25) is connected to the gate.
[0097]
FIGS. 8A, 8B and 8C show the case where the threshold value of the MOS transistor of the RC delay circuit of the third embodiment shown in FIG. 7 is the above-mentioned design value (a). The simulation waveforms of the input voltage Vin0 and the output voltage Vout0 are shown for the case of variation as shown in FIG.
[0098]
FIGS. 9A, 9B and 9C show the case where the threshold value of the MOS transistor of the RC delay circuit of the third embodiment shown in FIG. 7 is the above-described design value (a). The simulation waveforms of the voltages Vin 0, V 0, V 1, V 2, V 3, V 4 at the main nodes are shown for the case where the variation is as shown in FIG. Here, t1 represents a signal transmission time from the input voltage Vin0 to the intermediate node voltage V1, and t2 represents a signal transmission time from the intermediate node voltage V2 to the intermediate node voltage V4.
[0099]
When the simulation result of the RC delay circuit of the third embodiment is compared with the simulation result of the RC delay circuit of the conventional example 3, in the RC delay circuit of the conventional example 3, the absolute value of the threshold value of the PMOS transistor and the threshold value of the NMOS transistor are compared. The input / output waveform (input / output characteristics) fluctuates greatly when the absolute value of the transistor varies in the opposite direction. However, in the RC delay circuit of the second embodiment, the absolute value of the threshold of the PMOS transistor and the threshold of the NMOS transistor Even when the absolute values of the values fluctuate in opposite directions, the input / output waveforms (input / output characteristics) hardly change as shown in FIGS. 8 (a), 8 (b), and 8 (c).
[0100]
The reason is described.
[0101]
1) When the absolute value of the threshold value of the PMOS transistor increases by 0.2V and the absolute value of the threshold value of the NMOS transistor decreases by 0.2V.
[0102]
The circuit threshold value of the inverter IV2 of the first delay circuit 71 in FIG. 7 decreases, and the delay of the signal transmission time t1 increases as shown in FIG. 9B. On the other hand, the circuit threshold value of the inverter IV2 of the second delay circuit 72 in FIG. 7 also decreases, and the delay of the signal transmission time t2 becomes small as shown in FIG. 9B. In this case, the sum of the signal transmission times t1 and t2 is substantially equal to the case where the threshold value is a design value.
[0103]
2) When the absolute value of the threshold value of the PMOS transistor decreases by 0.2V and the absolute value of the threshold value of the NMOS transistor increases by 0.2V.
[0104]
The circuit threshold value of the inverter IV2 of the first delay circuit 71 in FIG. 7 is increased, and the delay of the signal transmission time t1 is reduced as shown in FIG. 9 (c). On the other hand, the circuit threshold value of the inverter IV2 of the second delay circuit 72 in FIG. 7 also increases, and the delay of the signal transmission time t2 increases as shown in FIG. 9C. In this case, the sum of the signal transmission times t1 and t2 is substantially equal to the case where the threshold value is a design value.
[0105]
Therefore, in the RC delay circuit of the third embodiment, as in the RC delay circuit of the first embodiment, the absolute value of the threshold value of the PMOS transistor and the absolute value of the threshold value of the NMOS transistor included in the circuit are opposite to each other. Even in the case of fluctuations, changes in the delay times of the two delay circuits cancel each other, and variations in delay time can be suppressed as a whole.
[0106]
In the RC delay circuit of the third embodiment, various modifications can be made and appropriate constants can be set in the same manner as the RC delay circuit of the first embodiment described above.
[0107]
<Fourth embodiment>
FIG. 10 shows an RC delay circuit according to the fourth embodiment.
[0108]
The RC delay circuit of FIG. 10 is different from the RC delay circuit of the third embodiment shown in FIG.
[0109]
That is, the RC delay circuit shown in FIG. 10 includes at least two (in this example, two) delay circuits 100 connected in series via an odd-numbered (in this example, one) CMOS inverter circuit 73 in the integrated circuit. At least one set of unit delay circuits connected (one set in this example) is provided.
[0110]
The delay circuit 100 includes a modified CMOS inverter IV1c in which two resistance elements R1 and R2 are inserted between the drains of the PMOS transistor TP and the NMOS transistor TN and the gates are connected to each other, and the two resistance elements R1 and R1. An NMOS capacitor Cn connected between the series connection node of R2 and the ground node; a PMOS capacitor Cp connected between the series connection node of the two resistance elements R1 and R2 and the VCC node; It comprises a CMOS inverter IV2 at the next stage in which an input node is connected to a series connection node of the resistor elements R1 and R2.
[0111]
In this case, in the delay circuit 100 in the previous stage, a third RC circuit is formed by one resistive element R2 of the modified CMOS inverter IV1c and the NMOS capacitor Cn. That is, one end side of the resistor element R2 of the third RC circuit is connected to the drain of the NMOS transistor TN of the former-stage modified CMOS inverter IV1c, and the other end side of the resistor element R1 is the PMOS transistor of the next-stage CMOS inverter IV2. (TP in FIG. 25) is connected to the gate.
[0112]
Further, in the delay circuit 100 at the subsequent stage, a fourth RC circuit is formed by one resistance element R1 of the modified CMOS inverter IV1c and the PMOS capacitor Cp. That is, one end side of the resistor element R1 of the fourth RC circuit is connected to the drain of the PMOS transistor TP of the previous stage modified CMOS inverter IV1c, and the other end side of the resistor element R1 is an NMOS transistor of the next stage CMOS inverter IV2. (TN in FIG. 25) is connected to the gate.
[0113]
11 (a), 11 (b), and 11 (c) show the case where the threshold value of the MOS transistor of the RC delay circuit of the fourth embodiment shown in FIG. 10 is the aforementioned design value (a). The simulation waveforms of the input voltage Vin1 and the output voltage Vout1 are shown for the case of variation as shown in FIG.
[0114]
12 (a), 12 (b), and 12 (c) show the above (b) when the threshold value of the MOS transistor of the RC delay circuit of the fourth embodiment shown in FIG. 10 is the above-described design value (a). The simulation waveforms of the voltages Vin 1, V 5, V 6, V 7, V 8, V 9 at the main nodes are shown for the case where the variation is as shown in FIG. Here, t3 represents a signal transmission time from the input voltage Vin1 to the intermediate node voltage V6, and t4 represents a signal transmission time from the intermediate node voltage V7 to the intermediate node voltage V9.
[0115]
Comparing the simulation result of the RC delay circuit according to the fourth embodiment with the simulation result of the RC delay circuit of the conventional example 4, the RC delay circuit of the conventional example 4 shows the absolute value of the threshold value of the PMOS transistor and the NMOS transistor. When the absolute value of the threshold value varies in the opposite direction, the input / output waveform (input / output characteristics) fluctuates greatly. However, in the RC delay circuit of the fourth embodiment, the absolute value of the threshold value of the PMOS transistor and the NMOS transistor Even when the absolute value of the threshold value varies in the opposite direction, the input / output waveform (input / output characteristics) hardly changes as shown in FIGS. 11 (a), 11 (b), and 11 (c).
[0116]
Further, the RC delay circuit according to the fourth embodiment has a case where the input signal voltage is changed from the “L” level to the “H” level and the input signal voltage is different from that of the RC delay circuit of the third embodiment. A substantially equal delay is obtained when the level changes from the “H” level to the “L” level, and the delay time as a whole is substantially equal even if there is a variation in the threshold voltage of the MOS transistor as described above.
[0117]
The reason is described.
[0118]
1) When the absolute value of the threshold value of the PMOS transistor increases by 0.2V and the absolute value of the threshold value of the NMOS transistor decreases by 0.2V.
[0119]
The circuit threshold value of the inverter IV2 of the delay circuit 100 in the preceding stage in FIG. 10 decreases, and the delay of the signal transmission time t3 increases as shown in FIG. In contrast, the circuit threshold value of the inverter IV2 of the delay circuit 100 in the subsequent stage in FIG. In this case, the sum of the signal transmission times t3 and t4 is substantially equal to the case where the threshold value is a design value.
[0120]
2) When the absolute value of the threshold value of the PMOS transistor decreases by 0.2V and the absolute value of the threshold value of the NMOS transistor increases by 0.2V.
[0121]
The circuit threshold value of the inverter IV2 of the delay circuit 100 in the preceding stage in FIG. 10 increases, and the delay of the signal transmission time t3 becomes small as shown in FIG. 12 (c). On the other hand, the circuit threshold value of the inverter IV2 of the delay circuit 100 in the subsequent stage in FIG. In this case, the sum of the signal transmission times t3 and t4 is substantially equal to the case where the threshold value is a design value.
[0122]
Therefore, in the RC delay circuit of the fourth embodiment, as in the RC delay circuit of the first embodiment, the absolute value of the threshold value of the PMOS transistor and the absolute value of the threshold value of the NMOS transistor included in the circuit are opposite to each other. Even in the case of fluctuations, changes in the delay time of the two delay circuits cancel each other, and variations in delay time can be suppressed as a whole.
[0123]
In addition, the RC delay circuit of the fourth embodiment is different from the RC delay circuit of the first embodiment in that the input signal voltage is changed from “L” level to “H” level and the input signal voltage is “ A substantially equal delay is selected when the level changes from the “H” level to the “L” level, and the delay time as a whole is substantially equal even if there is a variation in the threshold voltage of the MOS transistor as described above.
[0124]
In the RC delay circuit of the fourth embodiment, various modifications can be made and appropriate constants can be set in the same manner as the RC delay circuit of the first embodiment described above. In this case, in each delay circuit 100, the resistance value of the resistance element R1 and the resistance value of the resistance element R2 are substantially equal, the capacitance value of the capacitor Cn and the capacitance value of the capacitor Cp are substantially equal, and the delay circuit 100 of the previous stage. It is possible to simplify the design by setting the resistance value of the resistance element R1, the resistance value of the resistance element R2, the capacitance value of the capacitor Cn, and the capacitance value of the capacitor Cp to be substantially equal between the delay circuit 100 and the delay circuit 100 in the subsequent stage. From the viewpoint of
[0125]
【The invention's effect】
As described above, according to the RC delay circuit of the present invention, even when the absolute value of the threshold value of the PMOS transistor included in the circuit and the absolute value of the threshold value of the NMOS transistor vary in opposite directions, variation in delay time is suppressed. can do.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an RC delay circuit according to a first embodiment of the present invention.
FIG. 2 is a diagram showing input / output voltage waveforms by simulation in the RC delay circuit of FIG. 1 when the threshold value of the PMOS transistor and the threshold value of the NMOS transistor are the design values and when the threshold value varies in opposite directions.
3 is a diagram showing waveforms of voltages of main nodes by simulation in the RC delay circuit of FIG. 1 when a threshold value of a PMOS transistor and a threshold value of an NMOS transistor are design values and two cases where the threshold values vary in opposite directions.
FIG. 4 is a circuit diagram showing an RC delay circuit according to a second embodiment of the present invention.
5 is a diagram showing waveforms of input / output voltages by simulation when the threshold value of the PMOS transistor and the threshold value of the NMOS transistor in the RC delay circuit of FIG. 4 are the design values and two cases in which the threshold values vary in opposite directions.
6 is a diagram illustrating waveforms of voltages of main nodes by simulation in the RC delay circuit of FIG. 4 when the threshold value of the PMOS transistor and the threshold value of the NMOS transistor are design values and when the threshold value varies in opposite directions.
FIG. 7 is a circuit diagram showing an RC delay circuit according to a third embodiment of the present invention.
8 is a diagram showing waveforms of input / output voltages by simulation when the threshold value of the PMOS transistor and the threshold value of the NMOS transistor in the RC delay circuit of FIG. 7 are the design values and two cases in which the threshold values vary in opposite directions.
9 is a diagram showing waveforms of voltages of main nodes by simulation in the RC delay circuit of FIG. 7 when the threshold values of the PMOS transistor and the NMOS transistor are designed values and when the threshold values of the NMOS transistor vary in opposite directions.
FIG. 10 is a circuit diagram showing an RC delay circuit according to a fourth embodiment of the present invention.
11 is a diagram showing input / output voltage waveforms by simulation when the threshold value of the PMOS transistor and the threshold value of the NMOS transistor in the RC delay circuit of FIG. 10 are the design values and two cases where the threshold values vary in opposite directions.
12 is a diagram showing waveforms of voltages of main nodes by simulation in the RC delay circuit of FIG. 10 when the threshold value of the PMOS transistor and the threshold value of the NMOS transistor are design values and when the threshold value varies in opposite directions.
13 is a circuit diagram showing an RC delay circuit of Conventional Example 1. FIG.
14 is a diagram showing waveforms of input / output voltages by simulation when the threshold value of the PMOS transistor and the threshold value of the NMOS transistor in the RC delay circuit of FIG. 13 are the design values and two cases in which the threshold values vary in opposite directions.
15 is a diagram showing waveforms of voltages of main nodes by simulation in the RC delay circuit of FIG. 13 when the threshold value of the PMOS transistor and the threshold value of the NMOS transistor are the design values and when there are two cases where the threshold values vary in opposite directions.
FIG. 16 is a circuit diagram showing an RC delay circuit of Conventional Example 2;
FIG. 17 is a diagram showing input / output voltage waveforms by simulation when the threshold value of the PMOS transistor and the threshold value of the NMOS transistor in the RC delay circuit of FIG.
FIG. 18 is a diagram showing waveforms of voltages at main nodes by simulation in the RC delay circuit of FIG. 16 when the threshold value of the PMOS transistor and the threshold value of the NMOS transistor are the design values and when the threshold value varies in the opposite direction.
FIG. 19 is a circuit diagram showing an RC delay circuit of Conventional Example 3;
20 is a diagram showing input / output voltage waveforms by simulation in the RC delay circuit of FIG. 19 when the threshold value of the PMOS transistor and the threshold value of the NMOS transistor are the design values and when the threshold value varies in opposite directions.
FIG. 21 is a diagram showing the voltage waveform of the voltage at the main node by simulation when the threshold value of the PMOS transistor and the threshold value of the NMOS transistor are the design values in the RC delay circuit of FIG.
FIG. 22 is a circuit diagram showing an RC delay circuit of Conventional Example 4;
FIG. 23 is a diagram showing waveforms of input / output voltages by simulation when the threshold value of the PMOS transistor and the threshold value of the NMOS transistor in the RC delay circuit of FIG. 22 are the design values and two cases in which the threshold values vary in opposite directions.
FIG. 24 is a diagram showing the voltage waveform of the voltage at the main node by simulation when the threshold value of the PMOS transistor and the threshold value of the NMOS transistor are the design values in the RC delay circuit of FIG.
FIG. 25 is a circuit diagram showing an example of a CMOS inverter used in a conventional example and an example.
[Explanation of symbols]
11: first delay circuit,
110: first RC circuit;
12 ... Second delay circuit,
120 ... the second RC circuit,
13, IV1, IV2 ... inverter circuit,
R: resistance element,
Cn: NMOS capacitor,
Cp: PMOS capacitor.

Claims (15)

At least one set of unit delay circuits in which the first delay circuit and the second delay circuit are connected in series is provided,
The first delay circuit includes:
A first input circuit;
A first RC circuit in which a first resistance element and a first capacitor are connected in series to an output node of the first input circuit;
A first CMOS inverter circuit having an input node connected to a series connection node of the first resistance element and the first capacitor;
The second delay circuit includes:
A second input circuit;
A second RC circuit in which a second resistance element and a second capacitor are connected in series to an output node of the second input circuit;
A second CMOS inverter circuit having an input node connected to a series connection node of the second resistance element and the second capacitor;
An RC delay circuit characterized in that the transition direction of the input potential of the first CMOS inverter circuit and the transition direction of the input potential of the second CMOS inverter circuit accompanying the transition of the logic level of the input signal are opposite to each other. . The RC delay circuit according to claim 1, wherein
The first input circuit includes a first NMOS transistor connected between an output node and a discharge potential node, and the first capacitor and the first NMOS transistor are connected to the first capacitor. The input potential of the first CMOS inverter circuit transitions from the “H” level to the “L” level when discharged through the first CMOS inverter circuit, and the second input circuit is connected between the output node and the charge potential node. A first PMOS transistor, and when the second capacitor is charged from the second capacitor through the second resistance element and the first PMOS transistor, the input potential of the second CMOS inverter circuit is changed from the “L” level. An RC delay circuit which transits to an “H” level. The RC delay circuit according to claim 2, wherein
The first input circuit is a CMOS inverter circuit in which the drain and gate of the second PMOS transistor are connected corresponding to the drain and gate of the first NMOS transistor, or CMOS logic for logically processing a plurality of input signals. Circuit,
The second input circuit is a CMOS inverter circuit in which the drain and gate of the second NMOS transistor are connected corresponding to the drain and gate of the first PMOS transistor, or CMOS logic for logically processing a plurality of input signals. An RC delay circuit which is a circuit. At least one set of unit delay circuits in which the first delay circuit and the second delay circuit are connected in series is provided,
The first delay circuit includes:
A first input circuit in which a first resistance element is inserted between the drains of the first PMOS transistor and the first NMOS transistor, and the gates of the first PMOS transistor and the first NMOS transistor are connected to each other; ,
A first capacitor connected between a drain of the first PMOS transistor and a discharge potential node and forming a first RC circuit together with the first resistance element;
A first CMOS inverter circuit having an input node connected to the drain of the first PMOS transistor;
The second delay circuit includes:
A second input circuit in which a second resistance element is inserted between the drains of the second PMOS transistor and the second NMOS transistor, and the gates of the second PMOS transistor and the second NMOS transistor are connected to each other; ,
A second capacitor connected between the drain of the second NMOS transistor and a charging potential node and forming a second RC circuit together with the second resistance element;
An RC delay circuit comprising: a second CMOS inverter circuit having an input node connected to a drain of the second NMOS transistor. At least one set of unit delay circuits in which the first delay circuit and the second delay circuit are connected in series is provided,
The first delay circuit includes:
A first resistance element and a second resistance element are inserted in series between the drains of the first PMOS transistor and the first NMOS transistor, and the gates of the first PMOS transistor and the first NMOS transistor are connected to each other. A first input circuit,
A first capacitor connected between a series connection node of the first resistance element and the second resistance element and a discharge potential node;
A second capacitor connected between a series connection node of the first resistance element and the second resistance element and a charging potential node;
A first CMOS inverter circuit having an input node connected to a series connection node of the first resistance element and the second resistance element;
The second delay circuit includes:
A third resistance element and a fourth resistance element are inserted in series between the drains of the second PMOS transistor and the second NMOS transistor, and the gates of the second PMOS transistor and the second NMOS transistor are connected to each other. A second input circuit,
A third capacitor connected between a series connection node and a discharge potential node of the third resistance element and the fourth resistance element;
A fourth capacitor connected between a series connection node of the third resistance element and the fourth resistance element and a charging potential node;
An RC delay circuit comprising: a second CMOS inverter circuit having an input node connected to a series connection node of the third resistance element and the fourth resistance element. The RC delay circuit according to any one of claims 1, 4, and 5,
The RC delay circuit, wherein the first delay circuit and the second delay circuit are connected via an odd number of stages of CMOS inverter circuits. The RC delay circuit according to any one of claims 1 to 6,
The first capacitor is an NMOS capacitor connected between one end side node of the first resistance element and the discharge potential node;
The RC delay circuit, wherein the second capacitor is a PMOS capacitor connected between one end side node of the second resistance element and a charging potential node. The RC delay circuit according to any one of claims 1 to 7,
The product of the resistance value of the first resistance element and the sum of the capacitance value of the first capacitor and the input gate capacitance value of the first CMOS inverter circuit is the resistance value of the second resistance element and the second capacitor. RC delay circuit characterized by being approximately equal to the product of the capacitance value of the second and the sum of the input gate capacitance values of the second CMOS inverter circuit. The RC delay circuit according to claim 8,
An RC delay circuit, wherein a resistance value of the first resistance element is substantially equal to a resistance value of the second resistance element. The RC delay circuit according to claim 8 or 9,
The RC delay circuit, wherein a capacitance value of the first capacitor and a capacitance value of the second capacitor are substantially equal. The RC delay circuit according to claim 1,
The first capacitor is connected between the one end node of the first resistance element and a discharge potential node and between the one end node of the first resistance element and a charge potential node. PMOS capacitor,
The second capacitor includes a PMOS capacitor connected between one end side node of the second resistance element and the charging potential node and between one end side node of the second resistance element and the discharge potential node. An RC delay circuit, characterized in that it is an NMOS capacitor connected to. The RC delay circuit according to claim 5, wherein
The third capacitor is an NMOS capacitor connected between one end side node of the third resistance element and the discharge potential node;
The RC delay circuit, wherein the fourth capacitor is a PMOS capacitor connected between one end side node of the fourth resistance element and a charging potential node. The RC delay circuit according to any one of claims 3 to 12,
The RC delay circuit according to claim 1, wherein a size of the first PMOS transistor is substantially equal to a size of the second PMOS transistor. The RC delay circuit according to any one of claims 3 to 13,
The RC delay circuit according to claim 1, wherein a size of the first NMOS transistor is substantially equal to a size of the second NMOS transistor. A first delay circuit and a second delay circuit each including an RC circuit in which a resistance element and a capacitor are connected in series are connected in series in the integrated circuit ,
The first delay circuit includes a first RC circuit in which a first resistor element and a first capacitor are connected in series, and an input node connected to a series connection node of the first resistor element and the first capacitor. And a first CMOS inverter connected to
The second delay circuit includes a second RC circuit in which a second resistor element and a second capacitor are connected in series, and an input node connected to a series connection node of the second resistor element and the second capacitor. And a second CMOS inverter connected to
Along with the transition of the logic level of the input signal, the potential of the first connection node of the first RC circuit and the first capacitor and the second resistance element of the second RC circuit and the second RC delay circuit, wherein a potential of the connection node between the second capacitor are configured to transition in the opposite direction.

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