CN106712496B - Charge pump and charge pump circuit - Google Patents

Charge pump and charge pump circuit Download PDF

Info

Publication number
CN106712496B
CN106712496B CN201611250342.4A CN201611250342A CN106712496B CN 106712496 B CN106712496 B CN 106712496B CN 201611250342 A CN201611250342 A CN 201611250342A CN 106712496 B CN106712496 B CN 106712496B
Authority
CN
China
Prior art keywords
nmos tube
voltage doubling
node
module
inverter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201611250342.4A
Other languages
Chinese (zh)
Other versions
CN106712496A (en
Inventor
方海彬
刘铭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhaoyi Innovation Technology Group Co ltd
Hefei Geyi Integrated Circuit Co Ltd
Original Assignee
Zhaoyi Innovation Technology Group Co ltd
Hefei Geyi Integrated Circuit Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhaoyi Innovation Technology Group Co ltd, Hefei Geyi Integrated Circuit Co Ltd filed Critical Zhaoyi Innovation Technology Group Co ltd
Priority to CN201611250342.4A priority Critical patent/CN106712496B/en
Publication of CN106712496A publication Critical patent/CN106712496A/en
Application granted granted Critical
Publication of CN106712496B publication Critical patent/CN106712496B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The embodiment of the invention provides a charge pump and a charge pump circuit, wherein the charge pump comprises n stages of voltage doubling modules which are sequentially connected, n is an integer greater than or equal to 2, each voltage doubling module comprises a first capacitor and a second capacitor, and each voltage doubling module further comprises a first double-well NMOS tube, a first PMOS tube, a second double-well NMOS tube and a second double-well NMOS tube. When the voltage doubling module is a1 st-stage voltage doubling module, the drain end of the first double-well NMOS tube and the drain end of the second double-well NMOS tube are connected with the input voltage supply end of the charge pump, and when the voltage doubling module is not the 1 st-stage voltage doubling module, the drain end of the first double-well NMOS tube and the drain end of the second double-well NMOS tube are connected with the output end of the front-stage voltage doubling module. Compared with the charge pump in the prior art, the charge pump provided by the embodiment of the invention can reduce the power consumption of the charge pump under the same output current capacity.

Description

Charge pump and charge pump circuit
Technical Field
The present invention relates to the field of circuit technology, and in particular, to a charge pump and a charge pump circuit.
Background
In a system, ICs (integrated circuits) with different functions are usually included, and some ICs require a higher voltage than an external power source to operate normally, so a charge pump circuit is usually used by the system to boost the voltage of the external power source to the voltage required by the ICs to enable the ICs to operate normally.
In the prior art, when a charge pump in a charge pump circuit works, an NMOS transistor of a voltage doubling module in the charge pump has a liner bias effect, and when the output voltage of the charge pump is higher, the turn-on voltage of the NMOS transistor is larger, so that the NMOS transistor needs to be turned on with a higher turn-on voltage, which results in high power consumption of the charge pump in the prior art.
Disclosure of Invention
In view of the foregoing, an object of an embodiment of the present invention is to provide a charge pump and a charge pump circuit, so as to solve the problem of high power consumption of a charge pump in the prior art.
In order to solve the above problems, an embodiment of the present invention discloses a charge pump, including n-stage voltage doubling modules connected in sequence, where n is an integer greater than or equal to 2, the voltage doubling modules include a first capacitor and a second capacitor, and the voltage doubling modules further include: the voltage doubling module is characterized by comprising a first double-well NMOS tube and a second double-well NMOS tube, wherein when the voltage doubling module is a1 st-stage voltage doubling module, the drain end of the first double-well NMOS tube and the drain end of the second double-well NMOS tube are respectively connected with the input voltage supply end of a charge pump, and when the voltage doubling module is not the 1 st-stage voltage doubling module, the drain end of the first double-well NMOS tube and the drain end of the second double-well NMOS tube are respectively connected with the output end of a previous-stage voltage doubling module; the drain end of the first PMOS tube is connected with the source end of the first double-well NMOS tube, the gate end of the first PMOS tube is connected with the gate end of the first double-well NMOS tube, a first node is arranged between the drain end of the first PMOS tube and the source end of the first double-well NMOS tube, the first node is connected with the first capacitor, and a second node is arranged between the gate end of the first PMOS tube and the gate end of the first double-well NMOS tube; the drain end of the second PMOS tube is connected with the source end of the second double-well NMOS tube, the gate end of the second PMOS tube is connected with the gate end of the second double-well NMOS tube, a third node is arranged between the drain end of the second PMOS tube and the source end of the second double-well NMOS tube, the third node is respectively connected with the second capacitor and the second node, a fourth node is arranged between the gate end of the second PMOS tube and the gate end of the second double-well NMOS tube, the fourth node is connected with the first node, the source end of the second PMOS tube is connected with the source end of the first PMOS tube, and the source end of the second PMOS tube and the source end of the first PMOS tube are used as output ends of the voltage doubling modules.
Optionally, when the voltage doubling module is an mth stage voltage doubling module, m is greater than 1 and m is less than or equal to n, and the voltage doubling module further includes: the input end of the first power supply conversion unit receives a first clock signal, the power supply end of the first power supply conversion unit is connected with a first node in the m-1 stage voltage doubling module, the output end of the first power supply conversion unit is connected with the first capacitor, the first power supply conversion unit is used for outputting a first voltage signal, and the maximum voltage of the first voltage signal is m times of the input voltage provided by the input voltage providing end; the input end of the second power conversion unit receives a second clock signal, the power end of the second power conversion unit is connected with a third node in the m-1 th-stage voltage doubling module, the output end of the second power conversion unit is connected with the second capacitor, the second power conversion unit is used for outputting a second voltage signal, and the maximum voltage of the second voltage signal is m times of the input voltage provided by the input voltage providing end; the second clock signal and the first clock signal are differential clock signals to each other.
Optionally, the first power conversion unit includes: the source end of the third PMOS tube is connected with a first node in the m-1 stage voltage doubling module; the source end of the fourth PMOS tube is connected with a first node in the m-1 stage voltage doubling module; the gate end of the first NMOS tube receives the first clock signal, the source end of the first NMOS tube is grounded, the drain end of the first NMOS tube is connected with the drain end of the third PMOS tube, a fifth node is arranged between the drain end of the first NMOS tube and the drain end of the third PMOS tube, and the fifth node is connected with the gate end of the fourth PMOS tube; the source end of the second NMOS tube is grounded, the drain end of the second NMOS tube is connected with the drain end of the fourth PMOS tube, a sixth node is arranged between the drain end of the second NMOS tube and the drain end of the fourth PMOS tube, the sixth node is connected with the gate end of the third PMOS tube, and the sixth node is used as the output end of the first power conversion unit; the input end of the first inverter receives the first clock signal, the power end of the first inverter is connected with a power supply, the output end of the first inverter is connected with the gate end of the second NMOS tube, and the gate end of the first NMOS tube and the input end of the first inverter serve as the input end of the first power supply conversion unit.
Optionally, the second power conversion unit includes: the source end of the fifth PMOS tube is connected with a third node in the m-1 stage voltage doubling module; the source end of the sixth PMOS tube is connected with a third node in the m-1 stage voltage doubling module; the gate end of the third NMOS tube receives the second clock signal, the source end of the third NMOS tube is grounded, the drain end of the third NMOS tube is connected with the drain end of the fifth PMOS tube, a seventh node is arranged between the drain end of the third NMOS tube and the drain end of the fifth PMOS tube, and the seventh node is connected with the gate end of the sixth PMOS tube; the source end of the fourth NMOS tube is grounded, the drain end of the fourth NMOS tube is connected with the drain end of the sixth PMOS tube, an eighth node is arranged between the drain end of the fourth NMOS tube and the drain end of the sixth PMOS tube, the eighth node is connected with the gate end of the fifth PMOS tube, and the eighth node is used as the output end of the second power conversion unit; the input end of the second inverter receives the second clock signal, the power end of the second inverter is connected with a power supply, the output end of the second inverter is connected with the gate end of the fourth NMOS tube, and the gate end of the third NMOS tube and the input end of the second inverter serve as the input ends of the second power conversion unit.
Optionally, the voltage doubling module further includes: the input end of the first driving module receives the first clock signal, the power end of the first driving module is connected with a power supply, when the voltage doubling module is the 1 st-stage voltage doubling module, the output end of the first driving module is connected with the first capacitor, and when the voltage doubling module is not the 1 st-stage voltage doubling module, the output end of the first driving module is connected with the input end of the first power conversion unit; the input end of the second driving module receives the second clock signal, the power end of the second driving module is connected with the power supply, when the voltage doubling module is the 1 st-stage voltage doubling module, the output end of the second driving module is connected with the second capacitor, and when the voltage doubling module is not the 1 st-stage voltage doubling module, the output end of the second driving module is connected with the input end of the second power conversion unit.
Optionally, the first driving module includes: the power end of the third inverter is connected with the power supply, the input end of the third inverter receives the first clock signal, and the third inverter performs inversion processing on the first clock signal; the power supply end of the fourth inverter is connected with the power supply, the input end of the fourth inverter receives the first clock signal after the inversion processing, the fourth inverter performs the inversion processing on the first clock signal after the inversion processing, and the output end of the fourth inverter is used as the output end of the first driving module.
Optionally, the second driving module includes: the power supply end of the fifth inverter is connected with the power supply, the input end of the fifth inverter receives the second clock signal, and the fifth inverter performs inversion processing on the second clock signal; the power supply end of the sixth inverter is connected with the power supply, the input end of the sixth inverter receives the second clock signal after the inversion processing, the sixth inverter performs the inversion processing on the second clock signal after the inversion processing, and the output end of the sixth inverter is used as the output end of the second driving module.
In order to solve the above problems, an embodiment of the invention discloses a charge pump circuit, which comprises the charge pump.
The embodiment of the invention has the following advantages:
firstly, connecting n-level voltage doubling modules in sequence to obtain a high-voltage charge pump;
secondly, a first double-well NMOS tube and a second double-well NMOS tube are adopted in a differential cross coupling circuit of the voltage doubling module, the double-well NMOS tube has no lining bias effect, the starting voltage of the double-well NMOS tube does not change along with the output voltage of the charge pump, and compared with the prior art, the embodiment of the invention can greatly reduce the power consumption of the charge pump;
thirdly, when the voltage doubling module is a1 st-stage voltage doubling module, a power supply conversion unit is added in the voltage doubling module, and the maximum voltage of a differential cross coupling circuit in the voltage doubling module is increased through a voltage signal output by the power supply conversion unit, so that the power consumption of a charge pump can be further reduced;
fourth, the first driving module and the second driving module are added in the voltage doubling module, so that the driving capability of a clock signal can be enhanced, and the input resistance of the voltage doubling module can be reduced.
Drawings
FIG. 1 is a schematic diagram of one embodiment of a charge pump of the present invention;
FIG. 2 is a schematic diagram of another charge pump embodiment of the present invention;
FIG. 3 is a schematic diagram of a first power conversion unit in a stage 2 voltage doubling module according to another embodiment of the present invention;
FIG. 4 is a schematic diagram of a second power conversion unit in a stage 2 voltage doubling module according to another embodiment of the present invention;
fig. 5 is a signal waveform diagram of another charge pump embodiment of the present invention.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
Referring to fig. 1, which shows a block diagram of an embodiment of a charge pump according to the present invention, the charge pump includes n stages of voltage doubling modules connected in sequence, where n is an integer greater than or equal to 2, and the voltage doubling modules may include a first capacitor C1 and a second capacitor C2, and the voltage doubling modules may further include: the drain end of the first double-well NMOS tube N11 and the drain end of the second double-well NMOS tube N12 are respectively connected with an input voltage supply end of the charge pump when the voltage doubling module is a1 st-stage voltage doubling module 1, the input voltage supply end supplies an input voltage Vin, and the drain end of the first double-well NMOS tube N11 and the drain end of the second double-well NMOS tube N12 are respectively connected with the output end of a previous-stage voltage doubling module when the voltage doubling module is not the 1 st-stage voltage doubling module 1; the drain end of the first PMOS tube P1 is connected with the source end of the first double-well NMOS tube N11, the gate end of the first PMOS tube P1 is connected with the gate end of the first double-well NMOS tube N11, a first node is arranged between the drain end of the first PMOS tube P1 and the source end of the first double-well NMOS tube N11, the first node is connected with the first capacitor C1, and a second node is arranged between the gate end of the first PMOS tube P1 and the gate end of the first double-well NMOS tube N11; the drain end of the second PMOS tube P2 is connected with the source end of the second double-well NMOS tube N12, the gate end of the second PMOS tube P2 is connected with the gate end of the second double-well NMOS tube N12, a third node is arranged between the drain end of the second PMOS tube P2 and the source end of the second double-well NMOS tube N12 and is respectively connected with the second capacitor C2 and the second node, a fourth node is arranged between the gate end of the second PMOS tube P2 and the gate end of the second double-well NMOS tube N12 and is connected with the first node, the source end of the second PMOS tube P2 is connected with the source end of the first PMOS tube P1, and the source end of the second PMOS tube P2 and the source end of the first PMOS tube P1 serve as output ends of the voltage doubling module. The charge pump shown in fig. 1 includes 2-stage voltage doubling modules, namely a first-stage voltage doubling module 1 and a 2-stage voltage doubling module 2, which are sequentially connected.
In fig. 1, the first capacitor C1 may receive the first clock signal CLK, the second capacitor C2 may receive the second clock signal CLKB, the second clock signal CLKB and the first clock signal CLK are differential clock signals, and the output terminal of the charge pump outputs the voltage Out.
Specifically, when the voltage doubling module is a kth stage voltage doubling module, k is greater than or equal to 1 and k is smaller than or equal to n, the voltage doubling module continuously charges a first node and a fourth node through the high-pass characteristic of the first capacitor C1, and the range of voltage signals at the first node and the fourth node is k times of input voltage Vin to k+1 times of input voltage Vin; and the second node and the third node are continuously charged through the high-pass characteristic of the second capacitor C2, and the range of voltage signals at the second node and the third node is k times of the input voltage Vin-k+1 times of the input voltage Vin, so that the voltage of the output end of the voltage doubling module is maintained to be k+1 times of the input voltage Vin provided by the input voltage providing end. For example, in fig. 1, the voltage signals na1 at the first node and the fourth node in the 1 st stage voltage doubling module range from Vin to 2Vin, the voltage signals na2 at the second node and the third node range from Vin to 2Vin, the voltage signals na3 at the first node and the fourth node in the 2 nd stage voltage doubling module range from 2Vin to 3Vin, and the voltage signals na4 at the second node and the third node range from 2Vin to 3Vin.
According to the embodiment of the invention, the n-level voltage doubling modules are sequentially connected, so that a high-voltage charge pump can be obtained, and the output voltage Out of the high-voltage charge pump is n+1 times of the input voltage Vin provided by the input voltage providing end. In addition, the differential cross-coupling circuit (composed of the first double-well NMOS tube N11, the second double-well NMOS tube N12, the first PMOS tube P1 and the second PMOS tube P2) of the voltage doubling module adopts the first double-well NMOS tube N11 and the second double-well NMOS tube N12, so that the power consumption of the charge pump can be effectively reduced.
In one embodiment of the present invention, the input voltage supply terminal may be a power supply, the power supply voltage is VCC, the output terminal voltage of the 1 st stage voltage doubling module 1 is maintained at 2VCC, the output terminal voltage of the 2 nd stage voltage doubling module is maintained at 3VCC, … …, and the output terminal voltage Out of the nth stage voltage doubling module is maintained at (n+1) VCC.
Alternatively, in another embodiment of the present invention, referring to fig. 2, when the voltage doubling module is an mth stage voltage doubling module, m is greater than 1 and m is less than or equal to n, the voltage doubling module may further include: the first power conversion unit 10, the input end of the first power conversion unit 10 receives a first clock signal CLK, the power end of the first power conversion unit 10 is connected with a first node in the m-1 stage voltage doubling module, the output end of the first power conversion unit 10 is connected with the first capacitor C1, the first power conversion unit 10 is used for outputting a first voltage signal clk_d, the maximum voltage of the first voltage signal clk_d is m times of an input voltage Vin provided by the input voltage providing end, and the voltage range of the first voltage signal clk_d is 0-m times of the input voltage Vin; the second power conversion unit 20, the input end of the second power conversion unit 20 receives the second clock signal CLKB, the power end of the second power conversion unit 20 is connected with the third node in the m-1 level voltage doubling module, the output end of the second power conversion unit 20 is connected with the second capacitor C2, the second power conversion unit 20 is used for outputting the second voltage signal clkb_d, the maximum voltage of the second voltage signal clkb_d is m times of the input voltage Vin provided by the input voltage providing end, and the voltage range of the second voltage signal clkb_d is 0-m times of the input voltage Vin; the second clock signal CLKB and the first clock signal CLK are differential clock signals to each other. The charge pump shown in fig. 2 includes 2-stage voltage doubling modules, namely a first-stage voltage doubling module 1 and a 2-stage voltage doubling module 2, which are sequentially connected.
Alternatively, referring to fig. 3, the first power conversion unit 10 may include: the source end of the third PMOS tube P3 is connected with a first node in the m-1 stage voltage doubling module; the source end of the fourth PMOS tube P4 is connected with a first node in the m-1 stage voltage doubling module; the gate end of the first NMOS tube N1 receives a first clock signal CLK, the source end of the first NMOS tube N1 is grounded, the drain end of the first NMOS tube N1 is connected with the drain end of the third PMOS tube P3, a fifth node is arranged between the drain end of the first NMOS tube N1 and the drain end of the third PMOS tube P3, and the fifth node is connected with the gate end of the fourth PMOS tube P4; the source end of the second NMOS tube N2 is grounded, the drain end of the second NMOS tube N2 is connected with the drain end of the fourth PMOS tube P4, a sixth node is arranged between the drain end of the second NMOS tube N2 and the drain end of the fourth PMOS tube P4, the sixth node is connected with the gate end of the third PMOS tube P3, and the sixth node is used as the output end of the first power conversion unit 10; the input end of the first inverter F1 receives the first clock signal CLK, the power end of the first inverter F1 is connected with a power supply, the output end of the first inverter F1 is connected with the gate end of the second NMOS tube N2, and the gate end of the first NMOS tube N1 and the input end of the first inverter F1 serve as the input ends of the first power conversion unit 10. Fig. 3 is a schematic diagram of the structure of the first power conversion unit 10 in the 2 nd stage voltage doubler module 2.
Alternatively, referring to fig. 4, the second power conversion unit 20 may include: the source end of the fifth PMOS tube P5 is connected with a third node in the m-1 stage voltage doubling module; a sixth PMOS tube P6, wherein the source end of the sixth PMOS tube P6 is connected with a third node in the m-1 stage voltage doubling module; the gate end of the third NMOS tube N3 receives the second clock signal CLKB, the source end of the third NMOS tube N3 is grounded, the drain end of the third NMOS tube N3 is connected with the drain end of the fifth PMOS tube P5, a seventh node is arranged between the drain end of the third NMOS tube N3 and the drain end of the fifth PMOS tube P5, and the seventh node is connected with the gate end of the sixth PMOS tube P6; the source end of the fourth NMOS tube N4 is grounded, the drain end of the fourth NMOS tube N4 is connected with the drain end of the sixth PMOS tube P6, an eighth node is arranged between the drain end of the fourth NMOS tube N4 and the drain end of the sixth PMOS tube P6, the eighth node is connected with the gate end of the fifth PMOS tube P5, and the eighth node is used as the output end of the second power conversion unit 20; the input end of the second inverter F2 receives the second clock signal CLKB, the power supply end of the second inverter F2 is connected with the power supply, the output end of the second inverter F2 is connected with the gate end of the fourth NMOS transistor N4, and the gate end of the third NMOS transistor N3 and the input end of the second inverter F2 serve as the input ends of the second power conversion unit 20. Fig. 4 is a schematic diagram of the structure of the second power conversion unit 20 in the 2 nd stage voltage doubling module 2.
Since the power supply of the power conversion unit in the 2 nd stage voltage multiplying module 2 is the signal na1 at the first node or the signal na2 at the third node, if the swing of the first clock signal CLK and the second clock signal CLKB is 0 to VCC, the swing of the signal na1 and the signal na2 is VCC to 2VCC, the phase of the signal na1 is synchronized with the first clock signal CLK, and the phase of the signal na2 is synchronized with the second clock signal CLKB.
For the power conversion unit in the 2 nd stage voltage doubling module 2, when the power conversion unit pulls down, the power of the power conversion unit is VCC instead of 2VCC, so the power conversion unit only needs to pull down VCC to 0, and the power consumption of the whole circuit can be saved. When the power conversion unit is pulled up, the power of the power conversion unit is increased from VCC to 2VCC, and the power consumption of the whole circuit can be saved. For the power conversion unit in the 2 nd stage voltage doubling module 2, the output swing of the power conversion unit is 0-2 VCC, namely, the swings of clk_d and clkb_d are 0-2 VCC. Fig. 5 is a waveform diagram of signals in the charge pump shown in fig. 2.
Therefore, when the voltage doubling module is not the 1 st stage voltage doubling module 1, the power conversion unit is added in the voltage doubling module, and the maximum voltage of the differential cross coupling circuit in the voltage doubling module is increased through the voltage signal output by the power conversion unit, so that the power consumption of the charge pump can be further reduced.
Optionally, referring to fig. 2, the voltage doubler module may further include: the input end of the first driving module 30 receives the first clock signal CLK, the power end of the first driving module 30 is connected with the power supply, when the voltage doubling module is the 1 st stage voltage doubling module 1, the output end of the first driving module 30 is connected with the first capacitor C1, when the voltage doubling module is not the 1 st stage voltage doubling module 1, the output end of the first driving module 30 is connected with the input end of the first power conversion unit 10, and the first driving module 30 is used for reducing the output resistance of the first clock signal CLK; the second driving module 40, the input end of the second driving module 40 receives the second clock signal CLKB, the power end of the second driving module 40 is connected with the power supply, when the voltage doubling module is the 1 st stage voltage doubling module 1, the output end of the second driving module 40 is connected with the second capacitor C2, when the voltage doubling module is not the 1 st stage voltage doubling module 1, the output end of the second driving module 40 is connected with the input end of the second power conversion unit 20, and the second driving module 40 is used for reducing the output resistance of the second clock signal CLKB.
The first driving module 30 and the second driving module 40 are added in the voltage doubling module, so that the driving capability of the clock signal can be enhanced, and the input resistance of the voltage doubling module can be reduced.
Alternatively, referring to fig. 2, the first driving module 30 may include: the third inverter F3, the power end of the third inverter F3 is connected with power, the input end of the third inverter F3 receives the first clock signal CLK, the third inverter F3 inverts the first clock signal CLK; the power supply terminal of the fourth inverter F4 is connected to the power supply, the input terminal of the fourth inverter F4 receives the first clock signal CLK after the inversion, the fourth inverter F4 inverts the first clock signal CLK after the inversion, and the output terminal of the fourth inverter F4 serves as the output terminal of the first driving module 30.
Alternatively, referring to fig. 2, the second driving module 40 may include: the fifth inverter F5, the power end of the fifth inverter F5 is connected with power, the input end of the fifth inverter F5 receives the second clock signal CLKB, the fifth inverter F5 carries on the inversion processing to the second clock signal CLKB; the sixth inverter F6, the power source terminal of the sixth inverter F6 is connected to the power source, the input terminal of the sixth inverter F6 receives the inverted second clock signal CLKB, the sixth inverter F6 inverts the inverted second clock signal CLKB, and the output terminal of the sixth inverter F6 serves as the output terminal of the second driving module 40.
In summary, the charge pump according to the embodiment of the invention has the following advantages:
firstly, connecting n-level voltage doubling modules in sequence to obtain a high-voltage charge pump;
secondly, a first double-well NMOS tube and a second double-well NMOS tube are adopted in a differential cross coupling circuit of the voltage doubling module, the double-well NMOS tube has no lining bias effect, the starting voltage of the double-well NMOS tube does not change along with the output voltage of the charge pump, and compared with the prior art, the embodiment of the invention can greatly reduce the power consumption of the charge pump;
thirdly, when the voltage doubling module is a1 st-stage voltage doubling module, a power supply conversion unit is added in the voltage doubling module, and the maximum voltage of a differential cross coupling circuit in the voltage doubling module is increased through a voltage signal output by the power supply conversion unit, so that the power consumption of a charge pump can be further reduced;
fourth, the first driving module and the second driving module are added in the voltage doubling module, so that the driving capability of a clock signal can be enhanced, and the input resistance of the voltage doubling module can be reduced.
The embodiment of the invention also discloses a charge pump circuit comprising the charge pump.
The charge pump circuit of the embodiment of the invention has the following advantages: by adopting the charge pump, the power consumption of the charge pump can be effectively reduced while the high-voltage charge pump is obtained, and after the first driving module and the second driving module are added in the voltage doubling module, the driving capacity of a clock signal can be enhanced, and the input resistance of the voltage doubling module can be reduced.
For the charge pump circuit embodiment, since it includes a charge pump, the description is relatively simple, and reference is made to a partial description of the charge pump embodiment.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.
The foregoing has outlined a charge pump and a charge pump circuit according to the present invention, wherein specific examples are provided herein to illustrate the principles and embodiments of the invention, and the above examples are only for the purpose of aiding in the understanding of the method and core concept of the invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.

Claims (8)

1. The utility model provides a charge pump, its characterized in that includes n grades of voltage doubling module that connects gradually, and n is greater than or equal to 2 integers, voltage doubling module includes first electric capacity and second electric capacity, voltage doubling module still includes:
the voltage doubling module is characterized by comprising a first double-well NMOS tube and a second double-well NMOS tube, wherein when the voltage doubling module is a1 st-stage voltage doubling module, the drain end of the first double-well NMOS tube and the drain end of the second double-well NMOS tube are respectively connected with the input voltage supply end of a charge pump, and when the voltage doubling module is not the 1 st-stage voltage doubling module, the drain end of the first double-well NMOS tube and the drain end of the second double-well NMOS tube are respectively connected with the output end of a previous-stage voltage doubling module;
the drain end of the first PMOS tube is connected with the source end of the first double-well NMOS tube, the gate end of the first PMOS tube is connected with the gate end of the first double-well NMOS tube, a first node is arranged between the drain end of the first PMOS tube and the source end of the first double-well NMOS tube, the first node is connected with the first capacitor, and a second node is arranged between the gate end of the first PMOS tube and the gate end of the first double-well NMOS tube;
the drain end of the second PMOS tube is connected with the source end of the second double-well NMOS tube, the gate end of the second PMOS tube is connected with the gate end of the second double-well NMOS tube, a third node is arranged between the drain end of the second PMOS tube and the source end of the second double-well NMOS tube, the third node is respectively connected with the second capacitor and the second node, a fourth node is arranged between the gate end of the second PMOS tube and the gate end of the second double-well NMOS tube, the fourth node is connected with the first node, the source end of the second PMOS tube is connected with the source end of the first PMOS tube, and the source end of the second PMOS tube and the source end of the first PMOS tube are used as output ends of the voltage doubling modules;
when the voltage doubling module is an mth-stage voltage doubling module, m is greater than 1 and m is less than or equal to n, and the voltage doubling module further comprises:
the input end of the first power supply conversion unit receives a first clock signal, the power supply end of the first power supply conversion unit is connected with a first node in the m-1 stage voltage doubling module, the output end of the first power supply conversion unit is connected with the first capacitor, the first power supply conversion unit is used for outputting a first voltage signal, the maximum voltage of the first voltage signal is m times of the input voltage provided by the input voltage providing end, and the second clock signal and the first clock signal are differential clock signals.
2. The charge pump of claim 1, wherein the voltage doubling module further comprises:
the input end of the second power conversion unit receives the second clock signal, the power end of the second power conversion unit is connected with a third node in the m-1 th-stage voltage doubling module, the output end of the second power conversion unit is connected with the second capacitor, the second power conversion unit is used for outputting a second voltage signal, and the maximum voltage of the second voltage signal is m times of the input voltage provided by the input voltage providing end.
3. The charge pump of claim 2, wherein the first power conversion unit comprises:
the source end of the third PMOS tube is connected with a first node in the m-1 stage voltage doubling module;
the source end of the fourth PMOS tube is connected with a first node in the m-1 stage voltage doubling module;
the gate end of the first NMOS tube receives the first clock signal, the source end of the first NMOS tube is grounded, the drain end of the first NMOS tube is connected with the drain end of the third PMOS tube, a fifth node is arranged between the drain end of the first NMOS tube and the drain end of the third PMOS tube, and the fifth node is connected with the gate end of the fourth PMOS tube;
the source end of the second NMOS tube is grounded, the drain end of the second NMOS tube is connected with the drain end of the fourth PMOS tube, a sixth node is arranged between the drain end of the second NMOS tube and the drain end of the fourth PMOS tube, the sixth node is connected with the gate end of the third PMOS tube, and the sixth node is used as the output end of the first power conversion unit;
the input end of the first inverter receives the first clock signal, the power end of the first inverter is connected with a power supply, the output end of the first inverter is connected with the gate end of the second NMOS tube, and the gate end of the first NMOS tube and the input end of the first inverter serve as the input end of the first power supply conversion unit.
4. The charge pump of claim 2, wherein the second power conversion unit comprises:
the source end of the fifth PMOS tube is connected with a third node in the m-1 stage voltage doubling module;
the source end of the sixth PMOS tube is connected with a third node in the m-1 stage voltage doubling module;
the gate end of the third NMOS tube receives the second clock signal, the source end of the third NMOS tube is grounded, the drain end of the third NMOS tube is connected with the drain end of the fifth PMOS tube, a seventh node is arranged between the drain end of the third NMOS tube and the drain end of the fifth PMOS tube, and the seventh node is connected with the gate end of the sixth PMOS tube;
the source end of the fourth NMOS tube is grounded, the drain end of the fourth NMOS tube is connected with the drain end of the sixth PMOS tube, an eighth node is arranged between the drain end of the fourth NMOS tube and the drain end of the sixth PMOS tube, the eighth node is connected with the gate end of the fifth PMOS tube, and the eighth node is used as the output end of the second power conversion unit;
the input end of the second inverter receives the second clock signal, the power end of the second inverter is connected with a power supply, the output end of the second inverter is connected with the gate end of the fourth NMOS tube, and the gate end of the third NMOS tube and the input end of the second inverter serve as the input ends of the second power conversion unit.
5. The charge pump of claim 1, wherein the voltage doubling module further comprises:
the input end of the first driving module receives the first clock signal, the power end of the first driving module is connected with a power supply, when the voltage doubling module is the 1 st-stage voltage doubling module, the output end of the first driving module is connected with the first capacitor, and when the voltage doubling module is not the 1 st-stage voltage doubling module, the output end of the first driving module is connected with the input end of the first power conversion unit;
the input end of the second driving module receives the second clock signal, the power end of the second driving module is connected with the power supply, when the voltage doubling module is the 1 st-stage voltage doubling module, the output end of the second driving module is connected with the second capacitor, and when the voltage doubling module is not the 1 st-stage voltage doubling module, the output end of the second driving module is connected with the input end of the second power conversion unit.
6. The charge pump of claim 5, wherein the first drive module comprises:
the power end of the third inverter is connected with the power supply, the input end of the third inverter receives the first clock signal, and the third inverter performs inversion processing on the first clock signal;
the power supply end of the fourth inverter is connected with the power supply, the input end of the fourth inverter receives the first clock signal after the inversion processing, the fourth inverter performs the inversion processing on the first clock signal after the inversion processing, and the output end of the fourth inverter is used as the output end of the first driving module.
7. The charge pump of claim 5, wherein the second drive module comprises:
the power supply end of the fifth inverter is connected with the power supply, the input end of the fifth inverter receives the second clock signal, and the fifth inverter performs inversion processing on the second clock signal;
the power supply end of the sixth inverter is connected with the power supply, the input end of the sixth inverter receives the second clock signal after the inversion processing, the sixth inverter performs the inversion processing on the second clock signal after the inversion processing, and the output end of the sixth inverter is used as the output end of the second driving module.
8. A charge pump circuit comprising a charge pump according to any one of claims 1-7.
CN201611250342.4A 2016-12-29 2016-12-29 Charge pump and charge pump circuit Active CN106712496B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201611250342.4A CN106712496B (en) 2016-12-29 2016-12-29 Charge pump and charge pump circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201611250342.4A CN106712496B (en) 2016-12-29 2016-12-29 Charge pump and charge pump circuit

Publications (2)

Publication Number Publication Date
CN106712496A CN106712496A (en) 2017-05-24
CN106712496B true CN106712496B (en) 2024-03-01

Family

ID=58904044

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201611250342.4A Active CN106712496B (en) 2016-12-29 2016-12-29 Charge pump and charge pump circuit

Country Status (1)

Country Link
CN (1) CN106712496B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112003471B (en) * 2020-09-01 2022-03-25 歌尔微电子有限公司 Voltage-adjustable cross-coupling charge pump circuit, ASIC chip and microphone

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003234408A (en) * 2002-02-08 2003-08-22 Rohm Co Ltd Semiconductor device having booster circuit
CN1734908A (en) * 2004-07-16 2006-02-15 精工电子有限公司 Charge pump circuit
CN105227167A (en) * 2015-09-21 2016-01-06 温州大学 A kind of cmos switch circuit
CN106026637A (en) * 2016-07-06 2016-10-12 西安紫光国芯半导体有限公司 Charge pump circuit and its single-stage circuits
CN206686078U (en) * 2016-12-29 2017-11-28 北京兆易创新科技股份有限公司 A kind of charge pump and charge pump circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130257522A1 (en) * 2012-03-30 2013-10-03 Tyler Daigle High input voltage charge pump

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003234408A (en) * 2002-02-08 2003-08-22 Rohm Co Ltd Semiconductor device having booster circuit
CN1734908A (en) * 2004-07-16 2006-02-15 精工电子有限公司 Charge pump circuit
CN105227167A (en) * 2015-09-21 2016-01-06 温州大学 A kind of cmos switch circuit
CN106026637A (en) * 2016-07-06 2016-10-12 西安紫光国芯半导体有限公司 Charge pump circuit and its single-stage circuits
CN206686078U (en) * 2016-12-29 2017-11-28 北京兆易创新科技股份有限公司 A kind of charge pump and charge pump circuit

Also Published As

Publication number Publication date
CN106712496A (en) 2017-05-24

Similar Documents

Publication Publication Date Title
CN108964446B (en) Charge pump unit and charge pump circuit
US10177764B2 (en) Input/output circuit
US8049553B2 (en) High-voltage CMOS charge pump
CN101026332B (en) Charging pump circuit
US20160197551A1 (en) Charge pump circuit capable of reducing reverse currents
CN106712495B (en) Charge pump circuit
CN105281564A (en) Four-phase charge pump circuit
KR102122304B1 (en) Voltage level shifter with a low-latency voltage boost circuit
CN102419949A (en) Shift register circuit
US7714636B2 (en) Charge pump circuit and cell thereof
CN106910451B (en) Gate drive circuit and drive method of gate drive circuit
JP2016535487A (en) Latch comparator circuit and method
KR20230088805A (en) high-speed sampling circuit
CN106712496B (en) Charge pump and charge pump circuit
CN108809084B (en) Charge pump circuit
TWI439840B (en) Charge pump
CN106787690B (en) Charge pump and charge pump circuit
WO2018036475A1 (en) Clock voltage step-up circuit
CN112769319B (en) Level conversion module, drive circuit and control chip
CN113126534B (en) Logic control circuit
JP3469838B2 (en) Level shift circuit
JP2017169322A (en) Step-down circuit
CN109756104B (en) Two-phase dynamic synchronous clock generation circuit applied to charge pump system
US10305482B2 (en) Voltage level shifter
JP2010207092A (en) Four-phase clock driven charge pump circuit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information
CB02 Change of applicant information

Address after: Room 101, Floor 1-5, Building 8, Yard 9, Fenghao East Road, Haidian District, Beijing 100094

Applicant after: Zhaoyi Innovation Technology Group Co.,Ltd.

Applicant after: HEFEI GEYI INTEGRATED CIRCUIT Co.,Ltd.

Address before: 100083 12 Floors, Block A, Tiangong Building, Science and Technology University, 30 College Road, Haidian District, Beijing

Applicant before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc.

Applicant before: HEFEI GEYI INTEGRATED CIRCUIT Co.,Ltd.

GR01 Patent grant
GR01 Patent grant