JP5376414B2 - メモリアレイの操作方法 - Google Patents

メモリアレイの操作方法 Download PDF

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Publication number
JP5376414B2
JP5376414B2 JP2006000964A JP2006000964A JP5376414B2 JP 5376414 B2 JP5376414 B2 JP 5376414B2 JP 2006000964 A JP2006000964 A JP 2006000964A JP 2006000964 A JP2006000964 A JP 2006000964A JP 5376414 B2 JP5376414 B2 JP 5376414B2
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layer
memory
voltage
memory cells
erase
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JP2006216215A (ja
JP2006216215A5 (enExample
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ルー ハン−ティン
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マクロニクス インターナショナル カンパニー リミテッド
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  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)
JP2006000964A 2005-01-27 2006-01-05 メモリアレイの操作方法 Active JP5376414B2 (ja)

Applications Claiming Priority (2)

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US64701205P 2005-01-27 2005-01-27
US60/647012 2005-01-27

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JP2011032065A Division JP5712420B2 (ja) 2005-01-27 2011-02-17 不揮発性メモリセル、これを有するメモリアレイ、並びに、セル及びアレイの操作方法

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JP2006216215A JP2006216215A (ja) 2006-08-17
JP2006216215A5 JP2006216215A5 (enExample) 2010-04-22
JP5376414B2 true JP5376414B2 (ja) 2013-12-25

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JP2011032065A Active JP5712420B2 (ja) 2005-01-27 2011-02-17 不揮発性メモリセル、これを有するメモリアレイ、並びに、セル及びアレイの操作方法

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Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7811890B2 (en) 2006-10-11 2010-10-12 Macronix International Co., Ltd. Vertical channel transistor structure and manufacturing method thereof
US8772858B2 (en) * 2006-10-11 2014-07-08 Macronix International Co., Ltd. Vertical channel memory and manufacturing method thereof and operating method using the same
US7851848B2 (en) * 2006-11-01 2010-12-14 Macronix International Co., Ltd. Cylindrical channel charge trapping devices with effectively high coupling ratios
US7619919B2 (en) * 2007-01-12 2009-11-17 Marvell World Trade Ltd. Multi-level memory
TWI374448B (en) * 2007-08-13 2012-10-11 Macronix Int Co Ltd Charge trapping memory cell with high speed erase
US7816727B2 (en) * 2007-08-27 2010-10-19 Macronix International Co., Ltd. High-κ capped blocking dielectric bandgap engineered SONOS and MONOS
EP2063459A1 (en) * 2007-11-22 2009-05-27 Interuniversitair Microelektronica Centrum vzw Interpoly dielectric for a non-volatile memory device with a metal or p-type control gate
JP2009163782A (ja) 2007-12-13 2009-07-23 Toshiba Corp 半導体記憶装置
US7995392B2 (en) 2007-12-13 2011-08-09 Kabushiki Kaisha Toshiba Semiconductor memory device capable of shortening erase time
US8068370B2 (en) * 2008-04-18 2011-11-29 Macronix International Co., Ltd. Floating gate memory device with interpoly charge trapping structure
JP5443873B2 (ja) 2008-07-28 2014-03-19 株式会社東芝 半導体装置及びその製造方法
US8254175B2 (en) 2008-12-16 2012-08-28 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
JP2011071334A (ja) * 2009-09-25 2011-04-07 Toshiba Corp 不揮発性半導体記憶装置
TWI473253B (zh) 2010-04-07 2015-02-11 Macronix Int Co Ltd 具有連續電荷儲存介電堆疊的非揮發記憶陣列
JP5865214B2 (ja) 2012-09-06 2016-02-17 株式会社東芝 半導体装置及びその製造方法
JP7038607B2 (ja) * 2018-06-08 2022-03-18 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01152672A (ja) * 1987-12-09 1989-06-15 Sharp Corp 不揮発性半導体記憶装置
JPH0536991A (ja) * 1991-07-31 1993-02-12 Nippon Steel Corp 半導体記憶装置
JP3061924B2 (ja) * 1992-03-02 2000-07-10 日本電気株式会社 不揮発性記憶装置の消去方法
JPH06291332A (ja) * 1993-04-06 1994-10-18 Nippon Steel Corp 半導体記憶装置及びその使用方法
JPH0992738A (ja) * 1995-09-28 1997-04-04 Toshiba Corp 半導体装置およびその製造方法
US6002610A (en) * 1998-04-30 1999-12-14 Lucent Technologies Inc. Non-volatile memory element for programmable logic applications and operational methods therefor
JP2000216271A (ja) * 1999-01-22 2000-08-04 Sony Corp 不揮発性半導体記憶装置
JP4040534B2 (ja) * 2003-06-04 2008-01-30 株式会社東芝 半導体記憶装置

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JP5712420B2 (ja) 2015-05-07
JP2006216215A (ja) 2006-08-17
JP2011155266A (ja) 2011-08-11

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