JP5365931B2 - LIGHT EMITTING DRIVE DEVICE, LIGHT EMITTING DEVICE, ITS DRIVE CONTROL METHOD, AND ELECTRONIC DEVICE - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a light emission driving device which restrains occurrence of luminance unevenness and screen flickering due to waveform distortion of a driving signal in a light emitting panel which is ready for an active matrix type driving system; and to provide a light emitting device and a method for controlling the drive of the same, and electronic equipment equipped with the light emitting device. <P>SOLUTION: An additional period Tad, during which a pixel PIX is set to a selective state, is provided in a selection period Tsel of each line prior to a writing operation period Twrt during which display data are written into the pixel PIX. During the additional period Tad, a selection line voltage gradually approaches the voltage value of a selection signal Ssel, and when the writing operation period Twrt starts (when the additional period Tad ends), the selection signals Ssel of nearly uniform voltage values are applied to the pixels PIX connected to any position of a selection line Ls. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a light emission drive device, a light emission device, a drive control method thereof, and an electronic device, and in particular, a light emission drive device for driving a light emission panel (including a display panel) compatible with an active matrix drive method, The present invention relates to a light emitting device including the light emission driving device, a drive control method thereof, and an electronic apparatus including the light emitting device.

  In recent years, as a next-generation display device, a light-emitting element type display device (light-emitting device) including a display panel in which self-light-emitting elements such as organic electroluminescence elements (organic EL elements) are arranged in a matrix has been attracting attention. Such a display device is currently put into practical use as a relatively small display device such as a mobile phone, a digital audio player, and a car navigation monitor.

  Here, in a light emitting element type display device, an active matrix type driving method is widely adopted. According to such a light emitting element type display device, the display response speed is higher than that of a known liquid crystal display device, and there is almost no viewing angle dependence. Further, high brightness and high contrast and display image quality are achieved. It has excellent display characteristics that high definition can be achieved. In addition, the light emitting element type display device does not require a backlight or a light guide plate unlike a liquid crystal display device, and thus has a feature that the device configuration can be further reduced in thickness and weight. Therefore, it is expected to be applied to various electronic devices in the future, and research and development for increasing the size of the display screen is being conducted.

  In general, a drive control method in an active matrix display device is such that display pixels in each row are sequentially set to a selected state, and a gradation voltage corresponding to display data is applied in synchronization with the selection timing (display data is written). Thus, gradation control is performed based on the voltage component held in each display pixel. In such a light emitting element type display device (for example, organic EL display device), as described in, for example, Patent Document 1 and Patent Document 2, a pixel circuit including two or more thin film transistors in each pixel. (Light emission drive circuit) is provided.

JP-A-8-330600 JP 2001-147659 A

  By the way, not only the light emitting element type display device but also a known liquid crystal display device, when the display screen is enlarged, the wiring length from the driver for driving the pixel to the pixel becomes long. It is generally known that the magnitude of the load varies depending on the waveform, and the drive signal waveform is rounded or delayed. Here, in the liquid crystal display device, since the switching element provided in each pixel usually has only one thin film transistor (TFT), for example, the parasitic capacitance (wiring capacitance) generated in the gate line is relatively small.

  On the other hand, in a light emitting element type display device (for example, an organic EL display device) that employs an active matrix type driving method, as described in Patent Document 1 and Patent Document 2 described above, Since a plurality of thin film transistors are provided in a pixel, a parasitic capacitance generated in a wiring such as a scanning line (a gate line; referred to as a “selection line” in the embodiments described later) becomes large, and the time is based on the wiring resistance and the parasitic capacitance. Depending on the constant, there has been a problem that waveform rounding generated in a drive signal such as a scanning signal (gate signal; referred to as “selection signal” in the embodiments described later) becomes significant. For this reason, the substantial selection period of each pixel becomes relatively short, and insufficient writing of image data occurs, resulting in luminance unevenness and screen flickering.

  In particular, in a display device having a large display screen, when a display operation such as a double speed drive (120 Hz drive) is performed, the influence of such rounding of the drive signal tends to become more prominent. Note that the waveform rounding of the scanning signal in the organic EL display device will be described in detail in an embodiment described later.

  Therefore, in view of the above-described problems, the present invention is a light emitting drive that can suppress occurrence of luminance unevenness and screen flicker due to waveform rounding of a drive signal in a light emitting panel that supports an active matrix driving method. An object of the present invention is to provide a light-emitting device having good and uniform light emission characteristics, a drive control method thereof, and an electronic apparatus including the light-emitting device.

According to a first aspect of the present invention, there is provided a light emitting drive circuit having a light emitting element, a drive transistor for controlling a current supplied to the light emitting element, and a switching transistor for controlling the operation of the drive transistor, and extending along the row direction. Light emission that is connected to a plurality of scanning lines provided adjacent to each other, drives a plurality of pixels arranged along the extending direction of each scanning line, and controls light emission of the light emitting element of each pixel In the driving device, a selection signal having a first voltage value is applied to one end of each of the plurality of scanning lines at a predetermined timing, thereby operating the switching transistor of each pixel for each scanning line. A selection driving circuit that sequentially sets the selected state, and a signal driving circuit that generates a gradation voltage based on the image data and writes the gradation voltage to each pixel according to the timing. When, and a voltage measuring circuit connected to a particular scan line in the plurality of scan lines, the timing, application period in which the selection signal is applied to each of the plurality of scanning lines, the 1 period and a second period following the first period, the second period of the selection signal applied to one scanning line, adjacent to the scanning line, and then the The selection signal is applied so as to have a period that overlaps the first period of the selection signal applied to the other scanning line to which the selection signal is applied, and the plurality of pixels are arranged along the specific scanning line. A first pixel located at a position where the distance from the one end of the specific scanning line is the shortest and a second pixel located at a position where the distance from the one end is the longest; A first current composed of a voltage in the vicinity of the first pixel of the specific scanning line. And a voltage value of a second voltage consisting of a voltage in the vicinity of the second pixel of the specific scanning line is measured at the start of the second period, and the time of the first period is measured. Is set based on the voltage value of the first voltage and the voltage value of the second voltage, and the signal driving circuit is configured such that the application period of the selection signal applied to each scanning line is the second period. In some cases, the gradation voltage is applied to each pixel corresponding to the scanning line.

According to a second aspect of the invention, the light emission drive device according to claim 1, wherein the time of the first period, the voltage value of the second voltage and the voltage value of the first voltage and the value within the permissible range The allowable range is a value of 80% to 100% of the first voltage value.
According to a third aspect of the present invention, in the light emission driving device according to the first or second aspect, the time of the first period varies depending on the load of the scanning line to which the selection signal is applied. The length is set.
The invention of claim 4, wherein, in the light emission drive device according to claim 1, based on a comparison of a voltage value of the first voltage and the second voltage measured by the voltage measurement circuit, of the first period A control circuit for setting time is provided.

According to a fifth aspect of the present invention, a light emitting device includes a plurality of pixels each having a light emitting element, a light emitting driving circuit having a driving transistor for controlling a current supplied to the light emitting element, and a switching transistor for controlling an operation of the driving transistor. And a plurality of scanning lines connected to the switching transistors of the plurality of pixels and adjacent to each other in the row direction, and the light-emitting elements of the plurality of pixels of the light-emitting panel A light emission drive device that drives the scanning line, and the light emission drive device applies a selection signal having a first voltage value to each one end of each of the plurality of scanning lines at a predetermined timing, so that each scanning line has A selection drive circuit for sequentially setting the selection state for operating the switching transistor of each pixel, and a gradation voltage based on image data Form, comprising a signal driving circuit for writing the gray-scale voltage to the pixels in accordance with said timing, and a voltage measuring circuit connected to a particular scan line in the plurality of scan lines, wherein the timing The application period in which the selection signal is applied to each of the plurality of scan lines has a first period and a second period following the first period, and is applied to one of the scan lines. The second period of the selection signal overlaps with the first period of the selection signal applied to the other scanning line that is adjacent to the scanning line and is next applied with the selection signal. The plurality of pixels are arranged along the specific scanning line, and the first pixel located at the shortest distance from the one end of the specific scanning line and the one end from the one end A second pixel at a position having the longest distance, The pressure measurement circuit includes a voltage value of a first voltage including a voltage in the vicinity of the first pixel on the specific scanning line and a second voltage including a voltage in the vicinity of the second pixel on the specific scanning line. Is measured at the start of the second period, and the time of the first period is set based on the voltage value of the first voltage and the voltage value of the second voltage, and the signal The drive circuit applies the gradation voltage to each pixel corresponding to the scanning line when an application period of the selection signal applied to each scanning line is the second period. And

According to a sixth aspect of the invention, the light-emitting device according to claim 5, wherein the time of the first period, the voltage value of the second voltage and the voltage value of the first voltage has a value within the permissible range The allowable range is set to a length of 80% to 100% of the first voltage value.
According to a seventh aspect of the present invention, in the light emitting device according to the fifth or sixth aspect , the time of the first period varies depending on the load of the scanning line to which the selection signal is applied. It is characterized by being set.
According to an eighth aspect of the present invention, in the light emitting device according to the fifth aspect , the voltage values of the first voltage and the second voltage measured by the voltage measurement circuit are compared with the first voltage value. And a control circuit for setting the time of the first period.
According to a ninth aspect of the present invention, in the light emitting device according to any of the fifth to eighth aspects, the light emitting element is an organic electroluminescence element.
An electronic device according to a tenth aspect of the invention is characterized in that the light emitting device according to any one of the fifth to ninth aspects is mounted.

According to an eleventh aspect of the present invention, there are provided a plurality of pixels each including a light emitting element including a light emitting element, a light emitting driving circuit having a driving transistor for controlling a current supplied to the light emitting element, and a switching transistor for controlling an operation of the driving transistor. A plurality of scanning lines connected to the switching transistors of the pixels and adjacent to each other in the row direction, and the light emission of the plurality of pixels at a luminance gradation according to image data A drive control method of a light emitting device for causing an element to emit light, wherein the plurality of pixels are arranged along one specific scanning line in the plurality of scanning lines, and the distance from the one end of the specific scanning line setting step but which has a second pixel that is a distance from the one end and the first pixel in the shortest position is the longest position, to set the time of the first time period And a selection signal for operating the switching transistor of each pixel is set to a first voltage value at one end of each scanning line, and the application period is the first period and the first period. A selection step of sequentially applying a second period following the selection period, and a writing step of writing a gradation signal based on the image data to the pixels in accordance with the timing. The timing in the step is applied to the second period of the selection signal applied to one scanning line and to the other scanning line adjacent to the scanning line and then applied with the selection signal. The selection signal is applied so that the first period of the selection signal overlaps the first period, and the writing step is applied to each of the scanning lines at the timing. When it is the second period, applying the tone signal to each pixel corresponding to the scanning line, said setting step, the time of the first period, the selection signal by the selection step A voltage value of a first voltage consisting of a voltage in the vicinity of the first pixel of the specific scanning line, measured at the start of the second period when applied to one end of the specific scanning line; It is set based on a voltage value of a second voltage composed of a voltage of the second pixel of the specific scanning line .

Invention of claim 12, wherein, in the drive control method of a light emitting device according to claim 11, wherein the setting step, the time of the first period, the voltage value of the voltage value and the second voltage of the first voltage Is set to a length that is a value within the allowable range, and the allowable range is 80% to 100% of the first voltage value.
In a thirteenth aspect of the present invention, in the drive control method for a light emitting device according to the twelfth aspect , the setting step includes an initialization step of setting a time of the first period to a predetermined initial value, and the selection signal. A selection signal applying step to be applied to one end of the specific scanning line, a voltage measuring step for measuring the voltage value of the first voltage and the voltage value of the second voltage, the measured voltage value of the first voltage, and A voltage comparison step of comparing the voltage value of the second voltage with the first voltage value, and an application time adjustment step of adjusting the time of the first period based on the comparison result in the voltage comparison step; In the voltage comparison step, the time of the first period when the voltage value of the first voltage and the voltage value of the second voltage become values within the allowable range with respect to the first voltage value, selection And application period determination step of setting the time of the second period in step, characterized in that it comprises a.
In a fourteenth aspect of the present invention, in the driving control method for a light emitting device according to the eleventh or thirteenth aspect , in the setting step, the time of the first period is set to the load of the scanning line to which the selection signal is applied. The length is set differently depending on the size.

  According to the present invention, in a light-emitting panel that supports an active matrix driving method, it is possible to suppress occurrence of luminance unevenness and screen flicker due to waveform rounding of a driving signal.

It is a schematic block diagram which shows an example of the display apparatus to which the light-emitting device based on this invention is applied. It is a principal part block diagram which shows an example of the display panel applied to the display apparatus which concerns on 1st Embodiment, and its periphery circuit. It is the schematic which shows the structural example of the data driver applied to the display apparatus which concerns on 1st Embodiment. It is a circuit block diagram which shows an example of the pixel applied to the display panel which concerns on 1st Embodiment. 5 is a timing chart showing basic operations in display pixels applied to the display device according to the first embodiment. 4 is a timing chart illustrating an example of setting control of output timing of a selection signal in a selection driver applied to the display device according to the first embodiment. It is a conceptual diagram which shows the write-in operation | movement and light emission operation | movement in the display pixel which concerns on 1st Embodiment. 5 is a timing chart illustrating an example of a drive control method for a display device to be compared in the first embodiment. It is a figure which shows an example of the change of the selection line voltage at the time of applying the drive control method used as a comparison object. It is a figure for demonstrating the setting method of the selection period (addition period and write-in operation period) in the drive control method which concerns on 1st Embodiment. It is a schematic block diagram which shows the measuring mechanism of the selection line voltage applied to the display apparatus which concerns on 1st Embodiment. It is a flowchart which shows an example of the setting method of the additional period applied to the display apparatus which concerns on 1st Embodiment. 12 is a timing chart illustrating another example of setting control of output timing of a selection signal in a selection driver applied to the display device according to the first embodiment. It is the schematic which shows the 1st structural example of the selection driver applied to the display apparatus which concerns on 2nd Embodiment. 10 is a timing chart illustrating setting control of output timing of a selection signal in the selection driver according to the first configuration example of the second embodiment. It is the schematic which shows the 2nd structural example of the selection driver applied to the display apparatus which concerns on 2nd Embodiment. 10 is a timing chart illustrating setting control of output timing of a selection signal in a selection driver according to a second configuration example of the second embodiment. It is a schematic block diagram which shows an example of the display apparatus which concerns on 3rd Embodiment. It is the schematic which shows the selection driver applied to the display apparatus which concerns on 3rd Embodiment. 10 is a timing chart illustrating setting control of output timing of a selection signal in a selection driver according to a third embodiment. It is a schematic block diagram (the 1) which shows the structural example of the display apparatus which concerns on 4th Embodiment. It is a schematic block diagram (the 2) which shows the structural example of the display apparatus which concerns on 4th Embodiment. It is a perspective view which shows the structural example of the thin-type television to which the display apparatus (light-emitting device) concerning 1st thru | or 4th embodiment is applied.

DESCRIPTION OF EMBODIMENTS Hereinafter, a light emission drive device, a light emission device, a drive control method thereof, and an electronic device according to the present invention will be described in detail with reference to embodiments.
<First Embodiment>
First, a schematic configuration of a light emitting device including a light emission driving device according to the present invention will be described with reference to the drawings. Here, a case where the light-emitting device according to the present invention is applied as a display device will be described.

(Display device)
FIG. 1 is a schematic block diagram showing an example of a display device to which the light emitting device according to the present invention is applied, and FIG. 2 is an example of a display panel and its peripheral circuit applied to the display device according to the first embodiment. FIG.

  As shown in FIGS. 1 and 2, a display device (light emitting device) 100 according to the present embodiment is schematically shown as a display panel (light emitting panel) 110, a selection driver (selection drive circuit) 120, and a power supply driver (power supply drive). Circuit) 130, a data driver (signal drive circuit) 140, and a controller (control circuit) 150. Here, the selection driver 120, the power supply driver 130, the data driver 140, and the controller 150 correspond to the light emission driving device in the present invention.

  As shown in FIGS. 1 and 2, the display panel 110 includes a plurality of pixels PIX, a plurality of selection lines (scanning lines) Ls connected to each pixel PIX, a plurality of power supply lines La, and a plurality of pixels on the panel substrate. Data line (signal line) Ld and common electrode Ec. The plurality of pixels PIX are two-dimensionally arranged (for example, n rows × m columns; n and m are positive integers) in a row direction (horizontal direction in the drawing) and a column direction (vertical direction in the drawing) on the panel substrate. Each pixel PIX has a light emission drive circuit and a light emitting element, as will be described later. The plurality of selection lines Ls and the plurality of power supply lines La are arranged so as to be connected to the pixels PIX arranged in the row direction of the panel substrate for each row. The plurality of data lines Ld are arranged so as to be connected to the pixels PIX arranged in the column direction of the panel substrate for each column. The common electrode Ec is provided so as to be commonly connected to all the pixels PIX.

  The selection driver 120 is connected to each selection line Ls arranged on the display panel 110 described above. The selection driver 120 applies a selection signal Ssel having a predetermined voltage value (selection level or non-selection level) to the selection line Ls of each row at a predetermined timing based on a selection control signal supplied from the controller 150 described later. Thus, the pixels PIX in each row are set to the selected state. Specifically, the selection driver 120 sequentially shifts and applies the selection signal Ssel to the selection lines Ls of each row at a predetermined timing, thereby sequentially setting the pixels PIX of each row arranged on the display panel 110 to a selected state. Set.

  The selection driver 120 includes a shift register 121 and an output circuit 122, as shown in FIG. The shift register 121 sequentially outputs a shift signal corresponding to the selection line Ls of each row based on the selection control signal (scanning clock signal SCK, scanning start signal SST) supplied from the controller 150. The output circuit 122 converts the shift signal from the shift register 121 into a predetermined signal level (selection level; high level), and selects each row based on the selection control signal (output enable signal SOE) supplied from the controller 150. The selection signal Ssel is sequentially output to the line Ls. Here, the output circuit 122 includes, for example, a level shifter and a buffer. The specific configuration of the selection driver 120 will be described later in detail.

  Here, when the selection driver 120 according to the present embodiment outputs the selection signal Ssel of the selection level to the selection line Ls of each row and sets the pixel PIX of each row to the selection state, the selection line of the adjacent row The output timing of the selection signal Ssel is controlled so that a part of the selection level period of the selection signal Ssel output to Ls (that is, the period in which the selection state is set; the selection period) overlaps each other.

  Specifically, in the selection period in which the pixel PIX is set to the selected state, a gradation signal is supplied from the data driver 140 and the image data is substantially written into the pixel PIX (in a writing operation period described later). Prior to (corresponding to), the output period of the selection signal Ssel is set such that a predetermined period (hereinafter referred to as “addition period”) is added. That is, each selection period set by outputting a selection signal to a specific row has a writing operation period (second period) and an additional period (first period). In the selection period, a part or all of the additional period is set so as to overlap with the writing operation period of the selection period set in at least adjacent rows. The output timing of the selection signal Ssel is set and controlled based on, for example, a selection control signal supplied from the controller 150 described later. Note that the method for setting and controlling the output timing of the selection signal Ssel is not limited to the method using the selection control signal from the controller 150, and the present invention is applied to the selection driver 120 in addition to the selection control signal, as shown in an embodiment described later. It may have a specific configuration.

  The power driver 130 is connected to each power line La provided on the display panel 110. The power supply driver 130 applies a power supply voltage Vsa having a predetermined voltage value (light emission level or non-light emission level) to the power supply line La of each row at a predetermined timing based on a power supply control signal supplied from the controller 150 described later. Specifically, the power supply driver 130 applies a high-level power supply voltage (to the power supply line La of the pixels PIX in each row only during the light emission operation (light emission operation period) in a display drive operation (drive control method) described later. A third voltage value Vsa is applied. On the other hand, the power supply driver 130 performs the power supply line La of the pixels PIX in each row during a non-light emitting operation including a writing operation period (specifically, a selection period including an additional period and a writing operation period) to the pixels PIX in each row. In contrast, a low-level power supply voltage (second voltage value) Vsa is applied.

  The data driver 140 is connected to each data line Ld of the display panel 110 and generates a gradation signal (gradation voltage Vdata) corresponding to image data based on a data control signal supplied from a controller 150 described later. , And supplied to the pixel PIX via each data line Ld.

  FIG. 3 is a schematic diagram illustrating a configuration example of a data driver applied to the display device according to the present embodiment. Note that the configuration of the data driver shown in FIG. 3 is merely an example that can generate the gradation voltage Vdata having a voltage value corresponding to the display data, and the present invention is not limited to this. Absent.

  For example, as shown in FIG. 3, the data driver 140 includes a shift register circuit 141, a data register circuit 142, a data latch circuit 143, and a digital-analog conversion circuit (denoted as “D / A converter” in the figure) 144. And a buffer circuit 145.

  The shift register circuit 141 sequentially generates and outputs shift signals based on the data control signals (shift clock signal CLK, sampling start signal STR) supplied from the controller 150. The data register circuit 142 sequentially takes in display data D0 to Dm for one row supplied from the controller 150 based on the input timing of the shift signal. The data latch circuit 143 holds display data D0 to Dm composed of one row of digital data fetched by the data register circuit 142 based on the data control signal (data latch signal STB). The D / A converter 144 converts the held display data D0 to Dm into a predetermined analog signal voltage (grayscale voltage Vpix) based on the grayscale reference voltages V0 to VP supplied from power supply means (not shown). ). The buffer circuit 145 generates a gradation voltage Vdata corresponding to the gradation voltage Vpix. The buffer circuit 145 simultaneously outputs the gradation voltage Vdata to the data line Ld of the column corresponding to the display data at a timing based on the data control signal (output enable signal OE) supplied from the controller 150. .

  The controller 150 generates display data including digital data including luminance gradation data based on image data supplied from the outside of the display device 100 and supplies the display data to the data driver 140. In addition, the controller 150 controls the operation states of the selection driver 120, the power supply driver 130, and the data driver 140 described above based on a timing signal generated or extracted based on the image data, and performs predetermined driving on the display panel 110. A selection control signal, a power supply control signal, and a data control signal for executing the control operation are generated and output.

  In addition, the controller 150 according to the present embodiment supplies a selection control signal to the selection driver 120 described above, thereby writing a gradation signal (gradation voltage Vdata) corresponding to image data into the pixel PIX. Control is performed so that the selection signal Ssel is applied to the selection line Ls in the additional period preceding the insertion operation period. At this time, the controller 150 sets a part or all of the additional period so as to overlap in time with at least the writing operation period set in the adjacent row.

(Pixel)
Next, a configuration example of the pixels PIX arranged in the display panel 110 according to the present embodiment will be specifically described.

  FIG. 4 is a circuit configuration diagram illustrating an example of a pixel applied to the display panel according to the present embodiment. Note that the configuration of the pixel shown in FIG. 4 is merely an example of a pixel circuit (light emission driving circuit) applicable to the active matrix driving method, and the present invention is not limited to this. . That is, as long as the pixel circuit includes a plurality of thin film transistors, those described in Patent Documents 1 and 2 described above may be used. In this embodiment, as an example of a pixel, by supplying a gradation voltage having a voltage value corresponding to display data, a light emission driving current corresponding to display data is supplied to the light emitting element provided in each pixel. The case where a circuit configuration corresponding to a voltage designation type gradation control method for performing light emission operation (display operation) at a desired luminance gradation is described, but the present invention is not limited to this. That is, the pixel applicable to this embodiment supplies a light emission driving current corresponding to the display data to the light emitting element of each pixel by supplying a gradation current having a current value corresponding to the display data, for example. It may be provided with a circuit configuration corresponding to a current designation type gradation control method in which a light emission operation is performed at a luminance gradation.

  As shown in FIG. 4, the pixel PIX applied to the display panel 110 according to the present embodiment is near each intersection of the selection line Ls connected to the selection driver 120 and the data line Ld connected to the data driver 140. Has been placed. Each pixel PIX includes an organic EL element OEL, which is a current-driven light emitting element, and a light emission drive circuit (pixel circuit) DC that generates a current for driving the organic EL element OEL to emit light.

  Here, the light emission drive circuit DC sets the pixel PIX to the selected state based on the selection signal Ssel applied from the selection driver 120 during the write operation in the display drive operation described later, and is supplied from the data driver 140. A gradation signal (gradation voltage Vdata) is taken in. Further, during the light emission operation, the light emission drive circuit DC generates a light emission drive current corresponding to the captured gradation signal and supplies it to the organic EL element OEL.

  The light emission drive circuit DC shown in FIG. 4 has a circuit configuration including three transistors (thin film transistors) Tr11 to Tr13 and a capacitor Cs. The transistor (switching transistor) Tr11 has a gate terminal connected to the selection line Ls, a drain terminal connected to the power supply line La, and a source terminal connected to the contact N11. The transistor (switching transistor) Tr12 has a gate terminal connected to the selection line Ls, a source terminal connected to the data line Ld, and a drain terminal connected to the contact N12. The transistor (drive transistor) Tr13 has a gate terminal connected to the contact N11, a drain terminal connected to the power supply line La, and a source terminal connected to the contact N12. The capacitor (capacitance element) Cs is connected between the gate terminal (contact N11) and the source terminal (contact N12) of the transistor Tr13. The capacitor Cs may be a parasitic capacitance formed between the gate and the source terminal of the transistor Tr13, or in addition to the parasitic capacitance, a separate capacitance element is connected in parallel between the contact N11 and the contact N12. May be.

  The organic EL element OEL has an anode (anode electrode) connected to the contact N12 of the light emission drive circuit DC and a cathode (cathode electrode) connected to the common electrode Ec. The common electrode Ec is connected to a constant voltage source (not shown), and a predetermined low-potential common voltage Vcom (for example, a ground potential Vgnd) is applied to the common electrode Ec.

  In FIG. 4, the transistors Tr11 to Tr13 are not particularly limited, but for example, thin film transistors having the same channel type can be applied. The transistors Tr11 to Tr13 may be amorphous silicon thin film transistors or polysilicon thin film transistors.

  In particular, when an n-channel thin film transistor is applied as the transistors Tr11 to Tr13 and an amorphous silicon thin film transistor is applied as the transistors Tr11 to Tr13, an amorphous silicon manufacturing technique that has already been established is applied. Compared with a single crystal silicon thin film transistor, a transistor with uniform and stable operation characteristics (such as electron mobility) can be realized with a simple manufacturing process.

(Display device drive control method)
Next, a drive control method (image display operation) in the display device according to the present embodiment will be described with reference to the drawings.

  FIG. 5 is a timing chart showing the basic operation in the display pixel applied to the display device according to the present embodiment. FIG. 6 is a timing chart illustrating an example of setting control of the output timing of the selection signal in the selection driver applied to the display device according to the present embodiment. In FIG. 5, the operation will be described focusing on the pixels PIX in a specific row among the pixels PIX two-dimensionally arranged on the display panel 110. FIG. 7 is a conceptual diagram showing a writing operation and a light emitting operation in the display pixel according to the present embodiment.

  The drive control method (image display operation) of the display device 100 according to the present embodiment is, as shown in FIG. 5, schematically, by setting the pixels PIX in each row to a selected state within a predetermined one processing cycle period Tcyc. It is set so as to include a selection period Tsel for writing display data and a light emission operation period (display operation period) Temp that causes all the pixels PIX to simultaneously emit light at a luminance gradation corresponding to the display data ( Tcyc ≧ Tsel + Tem). Here, the selection period Tsel has a writing operation period (second period) Twrt for writing display data, and an additional period (first period) Tad set prior to the writing operation period Twrt. doing. Further, in the selection period Tsel, the organic EL elements OEL of all the pixels PIX are set to a non-light emitting state in which the light emitting operation is not performed.

(Write operation)
In the selection period Tsel including the additional period Tad and the writing operation period Twrt, as shown in FIG. 5, the selection signal set to a predetermined selection level (high level) from the selection driver 120 to each selection line Ls. By sequentially applying Ssel, the pixel PIX connected to the selection line Ls is set to the selected state. At this time, the power supply driver 130 applies the power supply voltage Vsa of the non-light emitting level (low level; potential equal to or lower than the common voltage Vcom) to the power supply line La of each row.

  Here, as shown in FIGS. 5 and 6, in the selection period Tsel of each row, a write operation for writing display data by supplying a predetermined gradation voltage Vdata from the data driver 140 via each data line Ld. Prior to the period Twrt, an additional period Tad for setting the pixel PIX in the row to the selected state is provided. The additional period Tad and the write operation period Twrt are set continuously, and the pixels PIX are continuously held in the selected state during the selection period Tsel.

  Specifically, in the timing chart shown in FIG. 6, focusing on the pixel PIX in the first row, the additional period Tad is based on the selection control signal supplied from the controller 150 to the selection driver 120 described above. When the start signal SST is in the high level and the clock signal SCK rises, the selection signal Ssel of the selection level (high level Vsh: first voltage value) is sent from the selection driver 120 to the selection line in the first row. Applied to Ls. As a result, the pixel PIX connected to the selection line Ls is set to the selected state, the transistors Tr11 and Tr12 provided in the light emission drive circuit DC are turned on, the gate and drain of the transistor Tr13 are short-circuited, and the diode Set to connected state.

  Next, in the write operation period Twrt, the start signal SST supplied from the controller 150 to the selection driver 120 is in a high level state with the above-described pixel PIX in the first row held in the selected state, and In synchronization with the next rise of the clock signal SCK, the data driver 140 supplies the gradation voltage Vdata having a voltage value corresponding to the display data to each data line Ld. Here, the gradation voltage Vdata is set to a negative voltage value corresponding to the luminance gradation value included in the display data written to each pixel PIX. Here, the gradation voltage Vdata is a negative voltage, and a write current Ia, which will be described later, is a negative current. However, in FIG.

  Thus, by supplying the negative gradation voltage Vdata to the data line Ld, a voltage lower than the low-level power supply voltage Vsa is applied to the source terminal (contact N12; the other end of the capacitor Cs) of the transistor Tr13. Side).

  Accordingly, a potential difference is generated between the contacts N11 and N12 (between the gate and source of the transistor Tr13), so that the transistor Tr13 is turned on. As shown in FIG. 7A, the transistor Tr13, the contact N12, A write current Ia corresponding to the gradation voltage Vdata flows in the direction of the data driver 140 via the transistor Tr12 and the data line Ld.

  At this time, charges corresponding to the potential difference generated between the contacts N11 and N12 (between the gate and source of the thin film transistor Tr13) are accumulated in the capacitor Cs and held as a voltage component. In addition, since the potential applied to the anode (contact N12) of the organic EL element OEL is lower than the cathode potential (common voltage Vcom), no current flows through the organic EL element OEL and no light emission operation is performed (non-light emission operation). .

  Then, the writing operation to the pixels PIX in each row as described above is repeatedly executed by setting the writing operation period Twrt and the additional period Tad to overlap each other between adjacent rows. Specifically, as shown in FIG. 6, in the selection period Tsel for the selection line Ls of the first row, the selection driver 120 for the selection line Ls of the second row during the write operation period Twrt as described above. Then, the selection signal Ssel of the selection level is applied to set the pixel PIX in the row to the selected state, and the additional period Tad is started. In the present embodiment, as shown in the timing chart of FIG. 6, the start timing of the write operation period Twrt for the pixel PIX in the first row (the start signal SST is in the high level state and the rising timing of the clock signal SCK). The additional period Tad for the pixel PIX in the second row is started in synchronization with (). In the present embodiment, the additional period Tad for the pixel PIX in the second row ends in synchronization with the end timing of the write operation period Twrt for the pixel PIX in the first row (next rising timing of the clock signal SCK). Then, the write operation period Twrt is started. In this case, the additional period Tad and the write operation period Twrt provided in the selection period Tsel are both set based on the rising timing of the clock signal SCK supplied as a selection control signal from the controller 150. The ratio is set to 1: 1.

  Note that, during the period in which the writing operation is repeatedly performed on the pixels PIX in each row, the power source driver 130 applies the non-light emitting level power supply voltage Vsa to the power source line La in each row. The organic EL element OEL of the pixel PIX is set to a non-light emitting state where the light emitting operation is not performed.

(Light emission operation)
Next, in the light emission operation period (display operation period) Tem after the writing operation of the display data to the pixels PIX in each row, as shown in FIG. 5, the selection driver 120 applies non-selection to the selection line Ls in each row. A selection signal Ssel of a selection level (low level Vsl) is applied. Accordingly, each pixel PIX is set to a non-selected state, the transistors Tr11 and Tr12 provided in the light emission drive circuit DC of each pixel PIX are turned off, and the connection between the data line Ld and each pixel PIX is cut off. . At this time, the capacitor Cs holds the charge accumulated in the above-described write operation period Twrt.

  In this state, the power supply driver 130 applies the power supply voltage Vsa of the light emission level (high level; potential higher than the common voltage Vcom) to the power supply line La of each row. As a result, the potential difference between the gate and source of the transistor Tr13 (both ends of the capacitor Cs) of the transistor provided in each pixel PIX is maintained, the transistor Tr13 is maintained in the ON state, and the organic EL element OEL The potential applied to the anode (contact N12) is higher than the cathode potential (ground potential).

  Therefore, as shown in FIG. 7B, in each pixel PIX, a current substantially equal to the write current Ia from the power supply line La to the organic EL element OEL through the transistor Tr13 and the contact N12 in the forward bias direction. The light emission drive current Ib of the value flows, and the organic EL element OEL emits light. Thereby, the organic EL element OEL of each pixel PIX continues the operation of emitting light with a luminance gradation corresponding to the display data (gradation voltage Vdata) written in the writing operation period Twrt.

(Comparison verification)
Next, operational effects of the display device (light emitting device) and the drive control method thereof according to the present embodiment will be described in detail with reference to comparison targets.

  FIG. 8 is a timing chart showing an example of a drive control method for a display device to be compared in the present embodiment. FIG. 9 is a diagram illustrating an example of a change in the selection line voltage when the drive control method to be compared is applied. FIG. 10 is a diagram for explaining a method for setting the selection period (addition period and writing operation period) in the drive control method according to the present embodiment.

  First, as a comparison target, in the display device 100 including the pixel PIX as shown in FIG. 4, as shown in FIG. 8, the selection signal Ssel of the selection level is applied only during the writing operation period Twrt without providing the additional period Tad. A case where the pixel PIX is selected by being applied to the selection line Ls will be described. In this case, the length of the write operation period Twrt (that is, the time during which the selection level selection signal Ssel is applied) corresponds to the length of the write operation period Twrt in the first embodiment described above. The write operation period Twrt is set to start and end in synchronization with the rising timing of the clock signal SCK.

  In the case of using such a drive control method, a simulation experiment was performed on the change in the selection line voltage when the selection signal Ssel of the high level Vsh (first voltage value) was applied to the selection line Ls. According to this, as shown in FIG. 9, the selection line voltage (normalized detection voltage in the figure) in the vicinity of the pixel PIX in the first column with the shortest distance from the selection driver 120 is represented by a characteristic line SPX ( As shown in 1), with respect to the selection signal Ssel output from the selection driver 120, the voltage value (high level Vsh: standard in the figure) in a relatively short time (0 to about 2.0 μsec). Asymptotic value 1.0) and then (approximately from 2.0 μsec), the voltage gradually converged to the voltage value of the selection signal Ssel with time.

  On the other hand, the selection line voltage in the vicinity of the pixel PIX in the m-th column having the longest distance from the selection driver 120 is applied with the selection signal Ssel from the selection driver 120 as shown by the characteristic line SPX (m) in the figure. It gradually increased immediately after that, and showed a tendency to converge to the voltage value (normalized value 1.0) of the selection signal Ssel over a sufficient time (approximately 15.0 μsec or more). That is, it can be seen that the waveform rounding of the selection line voltage (detection voltage) with respect to the selection signal Ssel increases as the distance from the selection driver 120 increases. Of the pixels PIX connected to the selection line Ls, the selection line in the vicinity of the pixel PIX arranged in the middle j column (a positive integer satisfying 1 <j <m) of the first column and the m column. As shown by the characteristic line SPX (j) in the figure, the voltage showed a changing tendency between the characteristic lines SPX (1) and SPX (m) described above.

  As shown in FIG. 9, the cause of the difference in waveform shape (waveform rounding) of the selection signal Ssel for each column is the distance of the selection line Ls from the selection driver 120, which is the output source of the selection signal Ssel, to each pixel PIX. This is due to the time constant based on the wiring resistance caused and the parasitic capacitance caused by the number of transistor elements provided in the light emission drive circuit DC of each pixel PIX. Here, this time constant corresponds to the load of the pixel PIX in each column, if reduced.

  Here, in order to improve the display characteristics when the display panel is enlarged, when the double-speed driving is performed with the operating frequency being 120 Hz, for example, the length of the writing operation period Twrt allowed for the pixels PIX in each row is Therefore, it is set to a short time of about 10 μsec. From this point of view, when the simulation result shown in FIG. 9 is verified, the selection line voltage is equal to the voltage value of the selection signal Ssel at any pixel PIX position from the first column to the m-th column in about 10 μsec. It can be seen that the standardized value 1.0) is not reached and the stable selection state is not set. In particular, at the position of the pixel PIX in the middle j-th column to the m-th column, the selection line voltage is equal to the voltage value of the selection signal Ssel (normalized value 1.0) even when 10 μsec has elapsed since the writing operation period Twrt ends. There is a possibility that the selected state becomes extremely unstable. That is, in the drive control method to be compared, the transition of the pixel PIX to the selection state is greatly delayed, and the period during which the substantial selection state is set in the writing operation period Twrt becomes relatively short. For this reason, there is a problem in that luminance unevenness and screen flickering due to insufficient writing of display data occur and image quality is deteriorated.

  On the other hand, in the drive control method for the display device 100 according to the present embodiment, the selection level from the selection driver 120 to the selection line Ls (high level Vsh: first voltage value) prior to the writing operation period Twrt. The selection signal Ssel is applied to provide an additional period Tad for setting the pixel PIX to the selected state. Specifically, as shown in FIG. 10, an additional period Tad is provided in a period of 0 to 10 μsec, and thereafter a write operation period Twrt is provided in a period of 10 to 20 μsec. Here, the continuous additional period Tad and the write operation period Twrt are set as the selection period Tsel shown in FIGS.

  Thus, in the drive control method according to the present embodiment, by providing the additional period Tad prior to the write operation period Twrt, the selection line voltage is selected in the additional period Tad (a period of 0 to 10 μsec). Asymptotically approaching the voltage value of Ssel (high level Vsh), with respect to the pixel PIX connected to any position of the selection line Ls at the start of the write operation period Twrt (at the time when 10 μsec when the additional period Tad ends) In addition, a selection signal Ssel having a substantially uniform voltage value (approximately a normalized value of 0.85 to 1.0) is applied.

  Therefore, according to the drive control method according to the present embodiment, the waveform rounding of the selection signal Ssel applied to the pixels PIX in each column is improved, and a state in which there is almost no difference in signal delay is realized in the writing operation period Twrt. Is done. This makes it possible to stabilize the selection state of the pixel PIX in each column in the write operation period Twrt regardless of the distance from the selection driver 120 (in other words, the load of the pixel PIX in each column). Therefore, it is possible to suppress the occurrence of uneven brightness and flickering of the screen due to insufficient writing of display data, thereby realizing a good image quality. At this time, the additional period Tad in each row overlaps with the selection period Tsel of the adjacent row in time, but the write operation period Twrt is set so as not to overlap in time with each other. The gradation voltage Vdata is not supplied to the pixels PIX in the row to be written, and erroneous writing can be prevented.

  Such setting control of the selection period Tsel (particularly, the additional period Tad) can set the length of the additional period Tad based on the above-described simulation experiment or the like, but the following configuration is used. Can also be set.

FIG. 11 is a schematic configuration diagram showing a selection line voltage measuring mechanism applied to the display device according to the present embodiment.
The selection line voltage measurement mechanism applied to the display device 100 according to the present embodiment includes, for example, measurement wirings Lms (1) and Lms (m) connected to the selection line Ls, as shown in FIG. And a selection line voltage measurement circuit 160 connected to the measurement wirings Lms (1) and Lms (m).

  The measurement wiring Lms (1) is connected in the vicinity of the position where the pixel PIX in the first column is connected in the selection line Ls of a specific row. The measurement wiring Lms (m) is connected in the vicinity of the position where the mth column pixel PIX of the selection line Ls is connected. Accordingly, the selection line voltage measurement circuit 160 measures the voltage value of the selection signal Ssel that is applied to the pixels PIX of the first column and the m-th column as the final column via the selection line Ls.

  The selection line voltage measurement circuit 160 compares the magnitude relationship of the measured selection line voltage, for example, and outputs the result to the controller 150 as a detection result. Based on the detection result, the controller 150 executes, for example, feedback control as described below, and sets the length of the additional period Tad in the selection period Tsel described above.

FIG. 12 is a flowchart illustrating an example of an additional period setting method applied to the display device according to the present embodiment.
For example, as shown in FIG. 12, the setting operation of the additional period Tad provided in the selection period Tsel is first performed by the selection driver 120 in accordance with a selection control signal from the controller 150, which is set prior to the writing operation period Twrt. The length of the period Tad is set to an initial value (for example, “0”) (initialization step S101). In this state, a selection signal Ssel is applied from the selection driver 120 to the selection line Ls (selection signal application step S102). Here, when the initial value is set to “0”, the additional period Tad is not set (Tad = 0), so that the selection period Tsel is substantially similar to the case shown in the comparison target (see FIG. 8). The write operation period Twrt is started simultaneously with the start.

  Next, selection is performed at a predetermined timing after application of the selection signal Ssel (specifically, any timing within the selection period Tsel; for example, timing immediately before the end of the additional period Tad or timing immediately after the start of the write operation period Twrt). The line voltage measurement circuit 160 individually measures the voltage value of the selected line voltage at the position of the pixel PIX in the first column and the m-th column as a measurement voltage via the measurement wirings Lms (1) and Lms (m). (Voltage measurement step S103).

  Next, the selection line voltage measurement circuit 160 compares the magnitude value of the measurement voltage with the voltage value of the selection level (high level Vsh) of the selection signal Ssel, and outputs the result to the controller 150 (voltage comparison). Step S104). In this comparison, it is determined whether or not the voltage value of the measurement voltage is within a preset allowable range with respect to the voltage value of the high level Vsh of the selection signal Ssel. Here, the allowable range is set to a value of 80% to 100% of the voltage value of the high level Vsh of the selection signal Ssel, for example. In this case, when the measured voltage value is 80% to 100% of the voltage value of the high level Vsh of the selection signal Ssel, it is determined that it is within the allowable range. Here, the voltage value comparison processing may be executed in the state of an analog voltage, or converted into a digital signal by an analog-digital conversion circuit (hereinafter referred to as “ADC”) (not shown). It may be executed later. The voltage value comparison process may be executed in the selected line voltage measurement circuit 160 or may be executed in the controller 150. When the voltage value comparison processing is executed in the controller 150, the selection line voltage measurement circuit 160 converts the measurement voltage composed of an analog voltage into a digital signal, for example, by an ADC provided therein, and outputs the digital signal to the controller 150.

  Next, when the voltage value of the measurement voltage is not within the allowable range (voltage comparison step S104: No), the controller 150 adds a fixed unit time Tu to the additional period Tad (application period adjustment step S106). Then, the controller 150 generates a selection control signal in which the signal width is set so as to correspond to the additional period Tad to which the unit time Tu is added, and outputs the selection control signal to the selection driver 120. As a result, the process returns to the selection signal applying step S102 again, the selection signal Ssel is applied to the selection line Ls, and first, the additional period Tad having a time width to which the unit time Tu is added is set, and then the writing is performed. Setting operation period Twrt is set.

  In this way, a series of processing operations including the selection signal application step, the voltage measurement step, the voltage comparison step, and the application period adjustment step are repeatedly executed, and in the voltage comparison step S104, the measurement voltage in the first column and m, which is the final column. The measurement voltage in the column is approximate or equal, the voltage values of both measurement voltages are within the allowable range (voltage comparison step S104: Yes), and the voltage value of the measurement voltage is the voltage of the high level Vsh of the selection signal Ssel. The time width (signal width) when the voltage value is 80% to 100% of the value is determined as the length of the additional period Tad and stored in the memory (application period determining step S105).

  As a result, as shown in FIG. 6, in the selection period Tsel, the controller 150 first supplies the selection control signal based on the signal width stored in the memory to the selection driver 120. An additional period Tad having a predetermined length obtained by the control is set, and then a predetermined write operation period Twrt is set.

  Here, in the present embodiment, the start timing and end timing of the additional period Tad and the write operation period Twrt are both set based on the rising timing of the clock signal SCK supplied as a selection control signal from the controller 150. . From this, in this embodiment, the signal width for one cycle of the clock signal SCK can be used as the unit time Tu in the feedback control. In the present embodiment, as shown in FIG. 6, the case where the ratio of the length of the additional period Tad and the write operation period Twrt set in the selection period Tsel is 1: 1 has been described. Is not limited to this. For example, as shown in FIG. 13, the length ratio of the additional period Tad and the write operation period Twrt can be set to 2: 1. The ratio of the length of the additional period Tad and the write operation period Twrt is not limited to this, and may be set to be another integer ratio. FIG. 13 is a timing chart showing another example of setting control of the output timing of the selection signal in the selection driver applied to the display device according to the present embodiment.

  In the present embodiment, the configuration (selection line voltage measurement mechanism) for realizing the drive control method shown in the flowchart of FIG. 12 is not limited to that shown in FIG. A configuration equivalent to the present embodiment (FIG. 11) and still another configuration will be described in detail in a fourth embodiment (see FIGS. 21 and 22) described later.

<Second Embodiment>
Next, a display device (light emitting device) and a drive control method thereof according to a second embodiment of the present invention will be described with reference to the drawings.

  In the first embodiment described above, the case where the length of the additional period Tad in the selection period Tsel is set based on the selection control signal (start signal SST, clock signal SCK) supplied from the controller 150 has been described. That is, in the first embodiment, as shown in FIGS. 6 and 13, the length of the additional period Tad is adjusted based on the cycle of the clock signal SCK. The second embodiment is characterized by having a configuration of a display device that can adjust the length of the additional period Tad with a high degree of freedom (in other words, finer adjustment).

  FIG. 14 is a schematic diagram illustrating a first configuration example of a selection driver applied to the display device according to the present embodiment. FIG. 15 is a timing chart showing the setting control of the output timing of the selection signal in the selection driver according to the first configuration example. Here, in the timing chart shown in FIG. 15, signals equivalent to those in the first embodiment are described with the same reference numerals.

  As shown in FIG. 14, the selection driver 120 according to the first configuration example includes flip-flop circuits F / F0, F / F1 to F / Fn (hereinafter referred to as “F”) constituting the shift register 121 of the selection driver 120. / Fx ". Here, x is an integer of 1 to n), and logic circuits LG1 to LGn (hereinafter referred to as" LGx ") for setting the output timing of the shift signal are provided. . Each logic circuit LGx includes an OR circuit (hereinafter referred to as “AND circuit”) and an AND circuit (hereinafter referred to as “OR circuit”), and is provided so as to correspond to the selection line Ls of each row. Yes.

  As shown in FIG. 14, the flip-flop circuits F / F0 and F / Fx are arranged in series so as to correspond to the selection line Ls, and a start signal SST supplied as a selection control signal from the controller 150 is used as a clock signal. The data is sequentially transferred to the next stage based on the rising timing of SCK. Specifically, as shown in FIG. 15 described later, the flip-flop circuit F / F0 outputs the start signal SST as the output signal Q0 at the rising timing of the clock signal SCK. Next, the output signal Q0 (or Qx-1) sent to the flip-flop circuit F / Fx in the next stage is output as the output signal Q1 (or Qx) at the rising timing of the clock signal SCK. By repeating such an operation, output signals Q0 to Qn are sequentially generated from the flip-flop circuits F / F0 and F / Fx and supplied to the logic circuit LGx in the output stage. Here, the signal widths of the output signals Q0 to Qn are set to the length of one cycle of the clock signal SCK, and are set so that the output signals Q0 to Qn do not overlap each other.

  In the logic circuit LGx provided corresponding to the selection line Ls of each row, the AND circuit, as shown in FIG. 14, is supplied with a reset signal RES supplied as a selection control signal from the controller 150 and a flip of the previous stage (previous stage). A logical sum is calculated using the output signal Qx-1 of the flop circuit F / Fx-1 as an input. The OR circuit calculates a logical product using the output (logical sum) from the AND circuit and the output signal Qx of the flip-flop circuit FFx corresponding to the logic circuit LGx as inputs. Then, as shown in FIG. 14, the output of the OR circuit is converted to a predetermined signal level (selection level; high level) via the level shifter 122a and the buffer 122b, and the selection signal Lsel is supplied to the selection line Ls of each row. Output sequentially. Here, the level shifter 122a and the buffer 122b correspond to the output circuit 122 shown in FIG.

  As shown in FIG. 15, the drive control method (particularly the write operation) of the display device including such a selection driver 120 includes a reset signal RES and output signals Q0 of the flip-flop circuits F / F0 and F / Fx. The start and end timings of the selection period Tsel (that is, the length of the selection period Tsel) are controlled based on the signal levels of .about.Qn. Here, the start timing of the selection period Tsel corresponds to the start timing of the additional period Tad, and the end timing of the selection period Tsel corresponds to the end timing of the write operation period Twrt.

  Specifically, the reset signal RES supplied as a selection control signal from the controller 150 and the output signal Qx-1 of the preceding flip-flop circuit F / Fx-1 are both at the timing when they become high level. The selection signal Ssel at the selection level is applied to the selection line Ls in the row, and the selection period Tsel (addition period Tad) is started. In addition, at the timing when both the reset signal RES and the output signal Qx of the flip-flop circuit F / Fx at the corresponding stage are at the low level, the selection signal of the non-selection level with respect to the selection line Ls of the x-th row. Ssel is applied, and the selection period Tsel (writing operation period Twrt) ends. Here, the reset signal RES is an inverted signal of the clock signal SCK.

  Accordingly, in this configuration example, as shown in FIG. 15, in the selection period Tsel, the half cycle of the clock signal SCK precedes the write operation period Twrt set to the length of one cycle of the clock signal SCK. The additional period Tad set to the minute length is executed. Further, the additional period Tad of each row is set so as to overlap with the writing operation period Twrt of the adjacent row in time. Therefore, according to the present configuration example, the length of the additional period Tad can be adjusted (finely adjusted) more finely than when the length of one cycle of the clock signal SCK is adjusted as a unit period. Thus, the degree of freedom can be increased.

  FIG. 16 is a schematic diagram illustrating a second configuration example of the selection driver applied to the display device according to the present embodiment. FIG. 17 is a timing chart illustrating setting control of the selection signal output timing in the selection driver according to the second configuration example. Here, components equivalent to those in the first configuration example described above are described with the same reference numerals. In the timing chart shown in FIG. 17, signals equivalent to those in the first embodiment are described with the same reference numerals.

  In the logic circuit LGx provided in the output stage of each flip-flop circuit F / F0, F / Fx constituting the shift register 121 shown in FIG. As shown in FIG. 16, either a reset signal RES1 or RES2 supplied as a selection control signal from the controller 150 is input. Specifically, the reset signal RES1 is input to the AND circuit of the logic circuit LGx provided corresponding to the odd-numbered selection line Ls, and provided corresponding to the even-numbered selection line Ls. The reset signal RES2 is input to the AND circuit of the logic circuit LGx. Here, the reset signals RES1 and RES2 are set to have different signal widths at different timings as shown in FIG. 17 described later. That is, in this configuration example, the length of the additional period Tad set in each row is adjusted by supplying reset signals RES1 and RES2 set to different signal widths from the controller 150.

  As shown in FIG. 17, the drive control method (particularly the write operation) of the display device provided with such a selection driver 120 includes a reset signal RES1, flip-flop circuits F / F0, F / F2,. Based on the signal level of the output signals Q0, Q2,..., Qn-1 of the F / Fn-1, the selection period Tsel set in the odd-numbered rows (1, 3,... N-1 rows). The start and end timing (the length of the selection period Tsel) is controlled. Further, based on the signal level of the reset signal RES2 and the output signals Q1, Q3,... Qn of the flip-flop circuits F / F1, F / F3,. ... the start and end timings (the length of the selection period Tsel) of the selection period Tsel set in the nth line) are controlled.

  Specifically, as in the first configuration example described above, the reset signal RES1 or RES2 supplied as a selection control signal from the controller 150 and the output signal Qx-1 of the preceding flip-flop circuit F / Fx-1 The selection level selection signal Ssel is applied to the selection line Ls in the x-th row at the timing when both become high level, and the selection period Tsel (addition period Tad) is started. In addition, at the timing when both the reset signal RES1 and the output signal Qx of the flip-flop circuit F / Fx at the corresponding stage are at the low level, the selection signal of the non-selection level with respect to the selection line Ls of the x-th row. Ssel is applied, and the selection period Tsel (writing operation period Twrt) ends.

  Here, the reset signal RES1 is a signal having a cycle twice that of the clock signal SCK and having the same signal width as the clock signal SCK. The reset signal RES2 is a signal having an arbitrary signal width which is twice as long as that of the clock signal SCK and is different from the clock signal SCK. Further, the reset signal RES2 is set to a signal width that does not overlap with the reset signal RES1 in terms of time.

  Thereby, in this configuration example, as shown in FIG. 17, prior to the write operation period Twrt set to the length of one cycle of the clock signal SCK, in the odd-numbered selection line Ls, the additional period Tad is set to be short (the length corresponding to a half cycle of the clock signal SCK) based on the signal width of the reset signal RES1. On the other hand, in the even-numbered selection line Ls, the additional period Tad is set to be long based on the signal width of the reset signal RES2 (arbitrary length). The additional period Tad for each row is set so as to overlap in time with the write operation period Twrt for the adjacent row.

  As described above, according to this configuration example, it is possible to set the additional periods Tad having different lengths in the odd and even rows. In other words, the additional period Tad can be set short in the selection line Ls with a small load, and the additional period Tad can be set long in the selection line Ls with a large load. That is, in this configuration example, by increasing the number (types) of reset signals supplied from the controller 150 and varying the signal width, the additional period Tad can be further increased according to the load of the selection line Ls of each row. It can be set by fine adjustment (fine adjustment). Therefore, according to this configuration example, it is possible to further stabilize the selection state of the pixels PIX in each column during the writing operation period Twrt, and thus it is possible to prevent luminance unevenness and screen flickering due to insufficient writing of display data. Suppressing and realizing a good image quality.

  In this configuration example, the case where the additional period Tad is different between the odd-numbered rows and the even-numbered rows has been described. However, if the same technical idea is used, for example, as shown in a third embodiment described later, The display area of the display panel may be divided into a plurality of areas, and an additional period Tad having a different length may be set for each area.

<Third Embodiment>
Next, a display device (light emitting device) and a drive control method thereof according to a third embodiment of the present invention will be described with reference to the drawings.

  In the first and second embodiments described above, the distance from the end of the display panel 110 to the selection driver 120 is assumed to be the same in each row, and the length of the additional period Tad provided during the selection period Tsel is set. The case of setting uniformly or according to the load has been described. In the third embodiment, it corresponds to the case where the length of the connection wiring (leading wiring) from the end of the display panel 110 to the selection driver 120 (or the selection / data 1 chip driver having the selection driver function) is different. As described above, the display device drive control method according to the second embodiment described above is applied.

  FIG. 18 is a schematic block diagram illustrating an example of a display device according to the third embodiment. Here, only the configuration peculiar to the present embodiment is shown in the overall configuration of the display device shown in FIG. 1, and other configurations are omitted. FIG. 19 is a schematic diagram illustrating a selection driver applied to the display device according to the present embodiment. FIG. 20 is a timing chart showing the setting control of the output timing of the selection signal in the selection driver according to the present embodiment. Here, components and signals equivalent to those in the first and second embodiments described above will be described with the same reference numerals.

  In a display device having a large-screen display panel, the size of an IC chip (driver chip) equipped with a driver function is generally relatively smaller than the screen size of the display panel. In such a case, the distance from the end of the selection line arranged in each row of the display panel to the selection driver is not uniform. For example, as shown in FIG. 18 (a), in the configuration in which the selection driver 120 is arranged biased to the lower outer side (the last row side) in the row direction (left-right direction in the drawing) of the display panel 110, the selection drivers 120 and 1 The length of the routing wiring Lrt (1) connecting the selection line Ls (1) in the row is compared with the length of the routing wiring Lrt (n) connected to the selection line Ls (n) in the nth row. Is significantly longer. That is, the distance from the selection driver 120 to the pixel PIX connected to the selection line Ls is different for each row.

  Further, as shown in FIG. 18B, a one-chip driver having a selection driver function and a data driver function (hereinafter referred to as “selection / data 1 chip”) is provided on the outer side (lower side of the drawing) of the display panel 110 in the column direction. In the configuration in which the driver ") 170 is arranged, the length of the routing wiring Lrt (1) connecting the selection / data 1-chip driver 170 and the selection line Ls (1) in the first row is the selection line in the nth row. This is significantly longer than the length of the routing wiring Lrt (n) connected to Ls (n). That is, in any of the configurations shown in FIGS. 18A and 18B, the distance from the drivers 120 and 170 to the pixel PIX connected to the selection line Ls is different for each row.

  As described in the first embodiment, the waveform rounding of the selection signal Ssel is based on the wiring resistance caused by the wiring length of the selection line Ls and the parasitic capacitance caused by the number of transistor elements provided in the pixel PIX. Influenced by time constant. As shown in FIGS. 18A and 18B, even when the wiring length of the selection line Ls including the routing wiring is different for each row, the time constants in the selection line Ls of each row are also different. Therefore, the rounding of the waveform of the selection signal Ssel applied to the selection line Ls (1) in the first row becomes conspicuous compared to the selection line Ls (n) in the nth row, and the first row having a long wiring length. Insufficient writing tends to occur in the pixel PIX connected to the selection line Ls (1).

  Therefore, in the present embodiment, as shown in FIGS. 18A and 18B, the display area of the display panel 110 is changed to an area on the upper screen side (area including the first to n / 2th rows; group) RGa. Are divided into regions (groups) RGb on the lower screen side (regions including n / 2 + 1 to nth row), and the lengths of the additional periods Tad are adjusted to be different in the regions RGa and RGb. Specifically, by applying the technical idea described in the second embodiment described above, as shown in FIG. 19, the logic circuit LG1 provided corresponding to the selection line Ls in the first to n / 2th rows. The output signal Qx-1 and the reset signal RES2 of the preceding flip-flop circuit F / Fx-1 and the reset signal RES2 are input to the AND circuit of .about.LGn / 2, and the selection signal Ssel applied to each row is generated. On the other hand, the AND circuit of the logic circuits LGn / 2 + 1 to LGn provided corresponding to the selection line Ls in the n / 2 + 1 to nth rows has an output signal Qx− of the flip-flop circuit F / Fx−1 in the previous stage. 1 and the reset signal RES1 are input, and the selection signal Ssel applied to each row is generated.

  Here, as shown in FIG. 20, the reset signal RES1 is a signal having a cycle twice that of the clock signal SCK and having the same signal width as the clock signal SCK. The reset signal RES2 is a signal having a cycle twice as long as that of the clock signal SCK and having a longer signal width than the clock signal SCK. Further, the reset signals RES1 and RES2 are set to signal widths that do not overlap in time.

  As shown in FIG. 20, the drive control method (particularly the write operation) of the display device having such a configuration is as follows. First, the reset signal RES2 and the flip-flop circuits F / F0, F / F1 to F / Fn / Based on the signal levels of the two output signals Q0 and Q1 to Qn / 2, the start and end of the selection period Tsel set in each row (1st to 2nd rows) of the region RGa on the upper screen side of the display panel 110 Timing (the length of the selection period Tsel) is controlled.

  Next, each row of the region RGb on the lower screen side of the display panel 110 based on the signal level of the reset signal RES1 and the output signals Qn / 2 + 1 to Qn of the flip-flop circuits F / Fn / 2 + 1 to F / Fn. The start and end timings (the length of the selection period Tsel) of the selection period Tsel set in (n / 2 + 1 to nth row) are controlled.

  Accordingly, in the present embodiment, as shown in FIG. 20, prior to the write operation period Twrt set to the length of one cycle of the clock signal SCK, the wiring length including the routing wiring Lrt (1) is reduced. In the selection lines Ls in the first to n / 2th rows arranged in the region RGa on the upper screen side including the longest selection line Ls (1), the additional period Tad is the signal width of the reset signal RES2. Is set to be long (arbitrary length) based on. On the other hand, the n / 2 + 1 to nth selection lines disposed in the region RGb on the lower screen side including the nth selection line Ls (n) having the shortest wiring length including the routing wiring Lrt (n). In Ls, the additional period Tad is set to be short (a length corresponding to a half cycle of the clock signal SCK) based on the signal width of the reset signal RES1. The additional period Tad for each row is set so as to overlap in time with the write operation period Twrt for the adjacent row.

  Thus, according to the present embodiment, a plurality of additional periods Tad having different lengths can be set in accordance with the length of the lead wiring from the selection driver to the end of the display panel. In other words, in the selection line Ls of the region RGa on the upper screen side where the load is large, the additional period Tad is set longer, and in the selection line Ls of the region RGb on the lower screen side where the load is small, the additional period Tad is set. Can be set short. That is, in the present embodiment, the number (types) of reset signals supplied from the controller 150 is increased and the signal widths thereof are varied, so that the selection line Ls in each region into which the display panel is divided is loaded according to the load. The additional period Tad can be set by fine adjustment (fine adjustment). Therefore, according to the present embodiment, the selection state of the pixels PIX in each column in the writing operation period Twrt can be further stabilized regardless of the distance from the selection driver, which results from insufficient writing of display data. It is possible to achieve good image quality by suppressing the occurrence of uneven brightness and screen flicker.

  In the present embodiment, the display panel 110 is divided into two regions (groups), the region RGa on the upper screen side and the region RGb on the lower screen side, and an additional period Tad having a different length is set in each region. Explained the case. The present invention is not limited to this, and the display panel 110 may be divided into a larger number of regions, and additional periods Tad having different lengths may be set in the respective regions. In that case, the controller 150 supplies a reset signal corresponding to the number of divided areas to the selection driver as a selection control signal.

  Moreover, the drive control method (refer to the flowchart of FIG. 12) shown in the first embodiment is applied to the method for setting the length of the additional period Tad as shown in the second and third embodiments. be able to. That is, the time width when the measured voltages in the first column and the last column (m column) are equal (or substantially equal) and there is no difference between them (becomes 0) is set as the additional period Tad. A series of processing operations (steps S101 to S106), which are determined as the length of, are executed for each row or each region.

  Also in the second and third embodiments described above, the selection line voltage measuring mechanism has the same configuration as that of the first embodiment (see FIG. 11), or a fourth embodiment described later (FIG. 21). The configuration shown in FIG. 22) can be applied.

<Fourth Embodiment>
Next, a display device (light emitting device) and a drive control method thereof according to a fourth embodiment of the present invention will be described with reference to the drawings.

  In the above-described first to third embodiments, the selection line voltage measurement mechanism shown in FIG. 11 is used to perform the processing of each row according to the series of processing operations (steps S101 to S106) shown in the flowchart of FIG. The method for setting the length of the additional period Tad included in the selection period Tsel has been described. In the fourth embodiment, still another configuration of the selection line voltage measurement mechanism will be described.

  21 and 22 are schematic block diagrams illustrating a configuration example of the display device according to the fourth embodiment. Here, only the configuration peculiar to the present embodiment is shown in the overall configuration of the display device shown in FIG. 1, and other configurations are omitted. Moreover, about the structure equivalent to each embodiment mentioned above, the same code | symbol is attached | subjected and the description is simplified or abbreviate | omitted. Here, a case where the present embodiment is applied to the display device including the selection / data 1-chip driver shown in FIG. 18B will be described.

  The display device 100 shown in FIG. 21A includes a selection / data 1 chip driver 170 arranged outside the display panel 110 in the column direction (downward in the drawing), and routing wirings Lrt (Lrt (1) to Lrt ( n)), measurement wirings Lms (1) and Lms (m), and an ADC 161. Here, the measurement wirings Lms (1) and Lms (m) are for measuring the selected line voltage at a predetermined position of the selected line, as in the configuration shown in the first embodiment (see FIG. 11). Is. The ADC 161 converts a selection line voltage composed of analog voltages individually measured via the measurement wirings Lms (1) and Lms (m) into a digital signal, and outputs the digital signal to the controller 150 as a detection result.

  Note that the ADC 161 according to the present embodiment may be provided independently as a configuration separate from the selection / data 1 chip driver 170, or the ADC 161 may select / data as shown in FIG. It may be provided inside the one-chip driver 170. That is, the ADC 161 shown in FIGS. 21A and 21B corresponds to the selection line voltage measurement circuit 160 shown in the first embodiment.

  Further, the display device 100 shown in FIG. 22 is different from the configuration in which the measurement wirings Lms (1), Lms (m) and the ADC 161 are connected in advance as shown in FIG. Only the measurement terminal pads Pms (1) and Pms (m) formed so as to be able to detect the voltage of the selection line Ls from the outside of 100 are provided. Here, the probe needles connected to the ADC 162 are in contact with the measurement terminal pads Pms (1) and Pms (m) when the voltage of the selection line Ls is detected. As a result, the ADC 162 converts the selection line voltage composed of the analog voltage measured via the measurement terminal pads Pms (1) and Pms (m) into a digital signal and outputs the digital signal to the controller 150. That is, the ADC 162 shown in FIG. 22 corresponds to the selection line voltage measurement circuit 160 shown in the first embodiment described above, and is provided in a prober equipped with, for example, a probe needle.

  In the display device 100 including the ADC 161 shown in FIGS. 21A and 21B, the selection line voltage measurement mechanism is integrally incorporated, so that the selection line voltage measurement operation is executed at an arbitrary timing. Thus, the length of the additional period Tad can be readjusted at an arbitrary timing. Therefore, the display device having these configurations is effective when the display image quality is expected to deteriorate over time. On the other hand, in the display device shown in FIG. 22, since the measurement mechanism for the selected line voltage is not incorporated in the display device, the device configuration and drive control of the display device can be simplified. Therefore, the display device having this configuration is effective when the selection line voltage measurement operation (setting operation for the additional period Tad) needs to be executed only once before the display device is shipped.

<Application examples of electronic devices>
Next, electronic devices to which the display device and the drive control method according to each embodiment described above are applied will be described.

  As shown in the first to fourth embodiments described above, the display device 100 including the display panel 110 having the light emitting elements composed of the organic EL elements OEL in each pixel PIX is a large screen such as a thin television or a monitor. The present invention can be applied to an electronic apparatus including the display device.

FIG. 23 is a perspective view showing a configuration example of a thin television to which the display device (light emitting device) according to the first to fourth embodiments is applied.
In FIG. 23, the flat-screen television 200 roughly includes a main body 201, a display unit 202 including the display device 100 including the display panel 110 of the present embodiment, and an operation controller (remote controller) 203. . In this case, in the display unit 202, the light emitting element of each pixel of the display panel 110 can emit light with an appropriate luminance gradation according to the image data, so that a good and uniform image quality can be realized.

DESCRIPTION OF SYMBOLS 100 Display apparatus 110 Display panel 120 Selection driver 121 Shift register 122a Level shifter 122b Buffer 130 Power supply driver 140 Data driver 150 Controller 160 Selection line voltage measurement circuit 161, 162 ADC
170 Selection / data 1 chip driver PIX pixel DC light emission drive circuit OEL organic EL element

Claims (14)

A plurality of light-emitting drive circuits each having a light-emitting element, a drive transistor that controls a current supplied to the light-emitting element, and a switching transistor that controls the operation of the drive transistor; A plurality of pixels connected along the extending direction of each scanning line and controlling light emission of the light emitting element of each pixel,
A selection signal having a first voltage value is applied to one end of each of the plurality of scanning lines at a predetermined timing, thereby sequentially setting the selection state in which the switching transistor of each pixel for each scanning line is operated. A selective drive circuit;
A signal drive circuit that generates a gradation voltage based on image data and writes the gradation voltage to each pixel according to the timing;
A voltage measuring circuit connected to one specific scanning line of the plurality of scanning lines;
With
The timing is such that an application period in which the selection signal is applied to each of the plurality of scanning lines has a first period and a second period following the first period, The second period of the selection signal to be applied and the first period of the selection signal applied to the other scanning line that is adjacent to the scanning line and is next applied with the selection signal. Set to have overlapping periods,
The plurality of pixels are arranged along the specific scanning line, and the first pixel at the shortest distance from the one end of the specific scanning line is at the longest distance from the one end. Having a second pixel;
The voltage measurement circuit includes a voltage value of a first voltage including a voltage in the vicinity of the first pixel on the specific scanning line and a second voltage including a voltage in the vicinity of the second pixel on the specific scanning line. Measuring the voltage value of the voltage at the start of the second period;
The time of the first period is set based on the voltage value of the first voltage and the voltage value of the second voltage,
The signal driving circuit applies the gradation voltage to each pixel corresponding to the scanning line when an application period of the selection signal applied to each scanning line is the second period. A light emission driving device characterized by the above. The time of the first period, the voltage value of the voltage value and the second voltage of the first voltage and is set to a length which is a value within the allowable range, the allowable range, the first voltage value The light emission driving device according to claim 1, wherein the light emission driving device has a value of 80% to 100%.   3. The light emission drive according to claim 1, wherein the time of the first period is set to a different length depending on a load of the scanning line to which the selection signal is applied. apparatus. Based on the comparison of the voltage value of the first voltage and the second voltage measured by the voltage measuring circuit, according to claim 1, further comprising a control circuit for setting the time of the first time period Light emission drive device. A plurality of pixels each having a light emitting element, a light emission driving circuit having a driving transistor for controlling a current supplied to the light emitting element, and a switching transistor for controlling an operation of the driving transistor, and connected to the switching transistor of the plurality of pixels A plurality of scanning lines provided adjacent to each other along the row direction, and a light-emitting panel,
A light emission driving device for driving the light emitting elements of the plurality of pixels of the light emitting panel;
With
The light emission driving device includes:
A selection signal having a first voltage value is applied to one end of each of the plurality of scanning lines at a predetermined timing, thereby sequentially setting the selection state in which the switching transistor of each pixel for each scanning line is operated. A selective drive circuit;
A signal drive circuit that generates a gradation voltage based on image data and writes the gradation voltage to each pixel according to the timing;
A voltage measuring circuit connected to one specific scanning line of the plurality of scanning lines;
With
The timing includes an application period in which the selection signal is applied to each of the plurality of scan lines, a first period, and a second period following the first period, and the timing is applied to one scan line. The second period of the selection signal applied and the first period of the selection signal applied to the other scanning line adjacent to the scanning line and to which the selection signal is applied next. Set to have overlapping periods,
The plurality of pixels are arranged along the specific scanning line, and the first pixel at the shortest distance from the one end of the specific scanning line is at the longest distance from the one end. Having a second pixel;
The voltage measurement circuit includes a voltage value of a first voltage including a voltage in the vicinity of the first pixel on the specific scanning line and a second voltage including a voltage in the vicinity of the second pixel on the specific scanning line. Measuring the voltage value of the voltage at the start of the second period;
The time of the first period is set based on the voltage value of the first voltage and the voltage value of the second voltage,
The signal driving circuit applies the gradation voltage to each pixel corresponding to the scanning line when an application period of the selection signal applied to each scanning line is the second period. A light emitting device characterized by the above. The time of the first period, the voltage value of the voltage value and the second voltage of the first voltage and is set to a length which is a value within the allowable range, the allowable range, the first voltage value The light emitting device according to claim 5 , wherein the light emitting device has a value of 80% to 100%. The time of the first period, the selection signal in response to the magnitude of the load of the scan line is applied, the light-emitting device according to claim 5 or 6, characterized in that it is set to a different length . A control circuit configured to set the time of the first period based on a comparison between the first voltage value and the voltage values of the first voltage and the second voltage measured by the voltage measurement circuit; The light-emitting device according to claim 5 . The light emitting device, light emitting device according to any one of claims 5 to 8, characterized in that an organic electroluminescence element. Electronic apparatus, characterized in that the light-emitting device according to any one of claims 5 to 9 is mounted. A plurality of pixels each having a light emitting element, a light emission driving circuit having a driving transistor for controlling a current supplied to the light emitting element, and a switching transistor for controlling an operation of the driving transistor, and connected to the switching transistor of the plurality of pixels And a plurality of scanning lines provided adjacent to each other along the row direction, and a light emitting device that causes the light emitting elements of the plurality of pixels to emit light at a luminance gradation corresponding to image data. A drive control method comprising:
The plurality of pixels are arranged along one specific scanning line in the plurality of scanning lines, and the first pixel at a position where the distance from the one end of the specific scanning line is the shortest and the one end from the one end Having a second pixel at the longest distance;
A setting step for setting the time of the first period;
At one end of each scanning line, a selection signal for operating the switching transistor of each pixel is set to a first voltage value, and an application period follows the first period and the first period. A selection step of sequentially applying the second period at a predetermined timing;
A writing step of writing a gradation signal based on the image data to the pixels according to the timing;
Including
The timing in the selection step is the second period of the selection signal applied to one scanning line, and the other scanning line to which the selection signal is applied next, adjacent to the scanning line. The first period of the selection signal applied is set to have an overlapping period;
In the writing step, when the application period of the selection signal applied to each scanning line is the second period at the timing, the gradation signal is output to each pixel corresponding to the scanning line. Applied ,
In the setting step, the time of the first period is measured at a start time of the second period when the selection signal is applied to one end of the specific scanning line in the selection step. A voltage value of a first voltage composed of a voltage in the vicinity of the first pixel on the scanning line and a voltage value of a second voltage composed of the voltage of the second pixel on the specific scanning line are set . A drive control method for a light-emitting device. Said setting step, the time of the first period, the voltage value of the second voltage and the voltage value of the first voltage is set to a value to become the length of the allowable range, the allowable range is the first 12. The drive control method for a light emitting device according to claim 11 , wherein the voltage control value is 80% to 100% of the voltage value of 1. The setting step includes
An initialization step of setting the time of the first period to a predetermined initial value;
A selection signal applying step of applying the selection signal to one end of the specific scanning line;
A voltage measuring step of measuring a voltage value of the first voltage and a voltage value of the second voltage;
A voltage comparison step of comparing the measured voltage value of the first voltage and the voltage value of the second voltage with the first voltage value;
An application time adjustment step of adjusting the time of the first period based on the comparison result in the voltage comparison step;
In the voltage comparison step, the time of the first period when the voltage value of the first voltage and the voltage value of the second voltage become values within the allowable range with respect to the first voltage value, An application period determining step for setting the time of the second period in the selection step;
The drive control method of the light-emitting device according to claim 12 , comprising: Said setting step, the time of the first period, the selection signal in response to the magnitude of the load of the scan line to be applied, in claim 11 or 13 and sets different lengths The drive control method of the light-emitting device of description.

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