JP2003302935A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that an afterimage can be seen when optical elements set to high brightness data are rewritten with low brightness data. <P>SOLUTION: When a signal in a 1st selection line SL10 becomes high, a 1st transistor Tr10 is turned on. An initializing data made to flow in a 1st data line DL10 is written to a 2nd transistor Tr11, and thereafter the brightness data made to flow in the 1st data line DL10 are written thereto. When the brightness data are written, a 2nd selection line SL20 becomes high, and a 3rd transistor Tr20 is turned on, and an initializing data made to flow in a 2nd data line DL11 are written to a 4th transistor Tr. Immediately thereafter, the brightness data made to flow in the 2nd data line DL11 are written thereto. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a display device. The present invention particularly relates to a technique for improving the display quality of an active matrix type display device.

[0002]

2. Description of the Related Art Notebook type personal computers and portable terminals are becoming widespread. Currently, liquid crystal displays are mainly used in these display devices, and organic EL (El
ectro Luminescence) display. The active matrix drive system is central to the display method of these displays. A display using this method is called an active matrix type display, in which a large number of pixels are arranged vertically and horizontally to form a matrix, and a switch element is arranged in each pixel. Video data is sequentially written for each scanning line by the switch element.

The practical design of an organic EL display is in its infancy, and various pixel circuits have been proposed. As an example of such a circuit, a pixel circuit disclosed in Japanese Patent Laid-Open No. 11-219146 will be briefly described with reference to FIG.

This circuit includes first and second transistors Tr50 and Tr51 which are two n-channel transistors.
And OLED50 which is an optical element, and storage capacitor C50
A selection line SL50 for transmitting a selection signal and a power supply line Vd
d50 and a data line DL50 for transmitting the luminance data.

The operation of this circuit is such that, for writing the brightness data of the OLED 50, the selection signal of the selection line SL50 becomes high, the first transistor Tr50 is turned on, and the brightness data input to the data line DL50 is stored. The second transistor Tr51 and the storage capacitor C50 are set, and a current according to the brightness data flows to cause the OLED 50 to emit light. When the selection signal of the selection line SL50 becomes low, the first transistor Tr50 is turned off, the gate voltage of the second transistor Tr51 is maintained, and light emission is continued according to the set brightness data.

[0006]

When the brightness data of the optical element is large, even if an attempt is made to set a small brightness data by rewriting the brightness data, the charge corresponding to the previous large brightness data will escape from the optical element. In some cases, the residual image does not remain, and accurate luminance data cannot be set, and an afterimage phenomenon may occur. In particular, when displaying a fast-moving moving image, the visibility may be reduced. Further, since the optical element uses a light-emitting material that varies depending on the color of light emitted,
The deterioration rate varies depending on the emission color, and there is a possibility that the luminance may vary.

The present invention has been made in view of such a situation, and an object thereof is to propose a new circuit for reducing an afterimage phenomenon. Another object of the present invention is to propose a new circuit capable of adjusting brightness. Still another object is to propose a new circuit that reduces the variation in brightness. Still another object is to realize the above object with a simple configuration.

[0008]

One embodiment of the present invention is a display device. This device includes a plurality of pixel circuits, first and second sub-lines obtained by dividing a data line that propagates luminance data to be written to these pixel circuits, and a plurality of pixel circuits that should be originally connected to the same data line. Among the pixel circuits connected to the first sub line, while writing the luminance data to the pixel circuit connected to the first sub line, the second sub line is connected to the pixel circuit connected to the second sub line. A display control circuit for writing initialization data via the display control circuit.

The "pixel circuit" includes an optical element, a drive element for driving the optical element, and a switch element for switching ON / OFF of light emission of the optical element. The "luminance data" is data relating to the luminance information set in the drive element, and is distinguished from the light intensity emitted by the optical element. As an optical element,
Organic Light Emitting Diode.
Hereinafter, it is simply referred to as “OLED”. ) Is mainly assumed. A metal oxide film (M
An OS (Metal Oxide Semiconductor) transistor and a thin film transistor (TFT: Thin Film Transistor) are mainly assumed.

The "data line" is, for example, 2 for each pixel column in a display device in which a plurality of pixel circuits are arranged in a matrix.
Books are provided one by one. “Initialization” means discharging the electric charge remaining in the optical element by writing the initialization data. “Initialization data” is data corresponding to zero if it is luminance data, and such dummy data may be propagated through the data line. The “data corresponding to zero” may be zero or a sufficiently low value.

Another form of the present invention is also a display device.
This device is configured such that while writing luminance data to a plurality of pixel circuits arranged in a matrix and pixel circuits included in any row via a data line, the row to which the luminance data is to be written next. And a display control circuit for writing initialization data to the pixel circuit included in the pixel circuit via a data line different from the data line.

Yet another aspect of the present invention is also a display device. This device has a plurality of pixel circuits each of which emits light of any one of a plurality of colors, and a period from writing of luminance data to writing of initialization data to these pixel circuits according to the emission color. And a display control circuit that is individually set.

Yet another aspect of the present invention is also a display device. In this device, the first half of the period in which the plurality of pixel circuits and the selection signal that determines the writing timing of the luminance data to the pixel circuits are activated corresponds to zero if the luminance data is the initialization data. A display control circuit that outputs the data and the brightness data that should be actually set in the latter half,
Have. The “selection signal” is a signal for controlling on / off of the switch element, and its signal line is provided individually for each row of pixels, for example. The "activated" state differs depending on the characteristics of the switch element to which the selection signal is input, and indicates a state in which a high signal is sent to the switch element of the n-channel transistor, and the switch element of the p-channel transistor. Shows the state of sending a low signal.

Yet another form of the present invention is also a display device. This device is configured such that while writing luminance data to a plurality of pixel circuits arranged in a matrix and a pixel circuit included in an upper region of the matrix of pixel circuits via a first data line. And a display control circuit for writing the initialization data to the pixel circuit included in the lower region through the second data line different from the first data line.
As a result, the inside of the display control circuit and the configuration or arrangement of the data lines can be simplified, which contributes to both downsizing of the device and improvement of the display quality. It should be noted that any combination or rearrangement of the above components is also effective as an aspect of the present invention.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION In the embodiments, an active matrix type organic EL display is assumed as a display device. Hereinafter, some embodiments will be described separately.

(First Embodiment) In the present embodiment,
Prior to setting the brightness data to the drive element, zero or a sufficiently low value is set in advance as the dummy brightness data to change the gate voltage of the drive element to a value at which the optical element is turned off. The dummy luminance data is written via the data line. As a result, the optical element is temporarily disconnected from the power source immediately before the brightness data is set in the drive element, so that the optical element is extinguished and the residual charge is eliminated.

FIG. 1 shows a display device 2 according to the present embodiment.
The circuit structure for pixels is shown. In this display device, a plurality of pixel circuits are arranged in a matrix. The first pixel Pix10,
Each second pixel Pix20 is a circuit for one pixel. The first pixel Pix10 includes a first transistor Tr10 as a switching element, a second transistor Tr11 as a driving element, and a first O 2 as an optical element.
Including LED 10. Similarly, the second pixel Pix20
It includes a third transistor Tr20 as a switch element, a fourth transistor Tr21 as a drive element, and a second OLED20 as an optical element. The power supply line Vdd supplies electric power for causing the first and second OLEDs 10 and 20 to emit light.

First and second data lines DL10 and DL11
Propagates the luminance data to be written in each pixel circuit.
The brightness data is the first and second basic data lines DL100, D.
It is sent from L101 and distributed to each column by the data control circuit 104. Pixel circuits included in the same column are originally connected to the same data line, but in the present embodiment, the data line is divided into two sub lines. The pixel circuits included in the odd-numbered rows are connected to the first sub line, and the pixel circuits included in the even-numbered rows are connected to the second sub line. In the figure, the first pixel Pix10 is connected to the first data line DL10, and the second pixel Pix20 is the second pixel Pix20.
Is connected to the data line DL20. First data line DL
Reference numeral 10 supplies a signal of brightness data to be set to the second transistor Tr11. The second data line DL11 has a fourth
A signal of luminance data to be set is supplied to the transistor Tr21.

First selection line SL10 and second selection line SL
Reference numeral 20 denotes first and third transistors Tr10 and T, respectively.
A selection signal for controlling on / off of r20 is propagated. The selection signals of the first and second selection lines SL10 and SL20 become high at the timing at which the first and second OLEDs 10 and 20 should emit light, respectively. As shown in the figure, a plurality of selection lines and a first or second sub-line are provided vertically and horizontally, and pixel circuits are respectively arranged at the intersections thereof.

The display control circuit 100 controls writing of brightness data to each pixel circuit. Display control circuit 100
Is the first data line DL for the first pixel Pix10.
While the brightness data is being written via 10, the control is performed to write the initialization data to the second pixel Pix 20 via the second data line DL 11. The display control circuit 100 includes a selection control circuit 102 and a data control circuit 104.
including. The selection control circuit 102 controls output of a selection signal to each pixel circuit. The data control circuit 104 controls the output of brightness data to each pixel circuit.

The selection control circuit 102 sets the write timing of the initialization data for the pixel circuit based on the write timing of the luminance data for the pixel circuit. The selection control circuit 102 in the present embodiment controls so that the initialization data writing is performed immediately before the luminance data writing.

First and second transistors Tr10 and Tr1
1 is an n-channel transistor. The first transistor Tr10 has a gate electrode connected to the first selection line SL10, a drain (or source) electrode connected to the first data line DL10, and a source (or drain) electrode connected to the second transistor Tr11. It is connected to the gate electrode. The third and fourth transistors Tr20 and Tr21 are also n-channel transistors. Third transistor T
In r20, the gate electrode is connected to the second select line SL20, and the drain (or source) electrode is the second data line D.
It is connected to L11 and the source (or drain) electrode is connected to the gate electrode of the fourth transistor Tr21.

In the second transistor Tr11, the source electrode is connected to the power supply line Vdd and the drain electrode is the first
Is connected to the anode electrode of the OLED 10. The source electrode of the fourth transistor Tr21 is also the power supply line V.
The drain electrode is connected to the anode electrode of the second OLED 20. The first and second OLEDs 10,
Each cathode electrode of 20 is set to the same potential as the ground potential.

The operation procedure performed by the above configuration will be described below. First, when the selection signal of the first selection line SL10 becomes high, the first transistor Tr10 is turned on, and the potential of the first data line DL10 and the gate potential of the second transistor Tr11 become the same potential. At this time, the data control circuit 104 uses the data corresponding to zero if it is the brightness data as the first data line DL as the initialization data.
10 and the value is written in the second transistor Tr11. As a result, the first OLED 10 is disconnected from the power supply line Vdd and initialized. Shortly thereafter,
The brightness data to be actually set is the first data line DL10.
To the second transistor Tr11 and the value is written to the second transistor Tr11. As a result, a current according to the gate-source voltage of the second transistor Tr11 flows, and the first OLED 10 emits light according to the amount of the current.

Next, when the brightness data is written in the second transistor Tr11, the signal of the second selection line SL20 becomes high, and the third transistor Tr20 is turned on. At this time, the initialization data flows through the second data line DL11, and the value is written in the fourth transistor Tr21. The second OLED 20 has a power supply line Vdd
It is shut off from and initialized. Immediately after that, the luminance data to be actually set flows to the second data line DL11, and the value is written to the fourth transistor Tr21. Fourth
A current corresponding to the gate-source voltage of the transistor Tr11 flows, and the second OLED 20 emits light according to the amount of the current.

FIG. 2 illustrates the internal structure of the selection control circuit. The selection control circuit 102 includes shift registers for the number of rows of pixels, an OR circuit, an AND circuit, and an inversion circuit. Here, the number of rows is m. The first to mth selection shift registers SR10 to SRm output high to the first to mth selection lines SL10 to SLm at two timings, respectively. In this embodiment, each selection soft register outputs a high level for two consecutive clocks so that the brightness data is written after the initialization data. The clock CLK is input to each selection shift register.

The second clock data CD20 is input to the first selection shift register SR10. The second
Of the clock data CD20 of the first and second AND circuits AN
It is inputted to the first selection shift register SR10 via either the D10 or AND20 or the OR circuit OR. However, initially, it is input via the second AND circuit AND20. First and second AND circuit AND10,
A set signal ST for switching from which the clock data is output is input to the AND 20. Since the set signal ST is input to the first AND circuit AND10 via the inverting circuit NOT, the first AND circuit AND10 is selected when the set signal ST is low, and the second AND circuit AND10 is selected when the set signal ST is high. The AND circuit AND20 is selected.

The high set signal ST and the high first clock data CD10 are both the second AND circuit AND2.
When input to 0, high second clock data CD20 is output via the OR circuit OR. Here, the first clock data CD10 that is high for two clocks is input to the second AND circuit AND20 so that the high second clock data CD20 is output for two consecutive clocks. The first selection shift register SR10 includes a first selection line SL10 and a second selection shift register SR20.
It outputs high for two consecutive clocks. The output of the second selection shift register SR20 to the second selection line SL20 is also output to the third selection shift register SR30, and thus the first to mth selection shift registers SR10 to SR are provided.
m outputs high in stages. The output of the m-th selection shift register SRm is input to the first AND circuit AND10.

When the set signal ST becomes low, it is inverted and the high set signal ST is input to the first AND circuit A.
The ND10 is switched to output the second clock data CD20. The m-th logical AND circuit AND10
When a high level is input from the selection shift register SRm, a high second clock data CD20 is output to the first selection shift register 10 via the OR circuit OR. While the set signal ST is low, the output of the second clock data CD20 via the first AND circuit AND10 is periodically repeated.

With these configurations, the first select line SL is used as the write timing of the initialization data and the brightness data.
10, second selection line SL20, third selection line SL30,
High is output in the order of the fourth selection line SL40 to the m-th selection line SLm. In addition, switching by the set signal ST and the first
By adjusting the timing when the clock data CD10 goes high, it is possible to output a selection signal that goes high for two clocks at an arbitrary timing.

FIG. 3 illustrates the internal structure of the data control circuit. The data control circuit 104 has a shift register and a switch element that are twice the number of pixel columns. Here, the number of pixel columns is n. First and second basic data lines DL100, DL
In 101, luminance data to be distributed to each data line as a sub-line serially flows. The signal propagated through the first basic data line DL100 is distributed to the first, third to 2n-1th data lines DL10 and DL20 to DL2n-1. The signal propagated through the second basic data line DL101 is
Second, fourth to 2n-th data lines DL11, DL21 to DL
It is distributed to 2n.

First to 2nth data shift registers SR
A clock is input to 11 to SR2n. First of all,
3 to 2n-1 data shift registers SR11 and SR
13 to SR2n-1 output high in that order.
These signals are transmitted to the first, third to 2n-1th transistors Tr.
100, Tr102 to Tr2n-1 are input to the gate electrodes and turned on in that order. First transistor Tr1
When 00 is turned on, the first data line DL10
Luminance data is sent from the basic data line DL100.
Next, when the third transistor Tr102 is turned on, the third basic data line DL10 is connected to the third data line DL20.
Luminance data is sent from 0. This is repeated until the 2n−1th transistor Tr2n−1 is turned on and the luminance data is sent to the 2n−1th data line DL2n−1.

The output of the (2n-1) th data shift register is input to the first data shift register SR11, where it is maintained at least until the number of clocks reaches n. Meanwhile, the first, third to 2n-1th data lines DL1
0, DL20, DL2n-1 are in a state in which data corresponding to zero flows as initialization data, and the second, 4-2nth data shift registers SR12, SR
14 to SR2n output high in that order. These signals are transmitted to the second, fourth to 2nth transistors Tr101,
It is input to the gate electrodes of Tr103 to Tr2n and turned on in that order. When the second transistor Tr101 is turned on, the brightness data is sent to the second data line DL11 from the second basic data line DL101. Next, when the fourth transistor Tr103 is turned on, luminance data is sent to the fourth data line DL21 from the second basic data line DL101. This is the 2nth transistor Tr2n
Is turned on and the luminance data is sent to the 2n-th data line DL2n. The output of the 2n-th data shift register is input to the 2nd data shift register SR12, where it is maintained at least until the number of clocks reaches n. Meanwhile, the second and fourth to 2nth data lines DL1
The data corresponding to zero flows into 1, DL21, DL2n as initialization data.

With these configurations, the first, third to 2n-1 th
While the luminance data flows through the data lines DL10 and DL20 to DL2n−1, the second and fourth to 2nth data lines DL11,
Initialization data flows through DL21 to DL2n. First,
3 to 2n-1 data lines DL10 and DL20 to DL2n
While the initialization data flows to -1, the brightness data flows to the second, fourth to 2nth data lines DL11 and DL21 to DL2n.

FIG. 4 shows a circuit configuration for eight pixels of the display device. In this figure, a pixel circuit for 4 rows and 2 columns is shown.
Illustration of a detailed configuration for each pixel is simplified. The first and third data lines DL10 and DL20 propagate the luminance data to the pixel circuits included in the odd-numbered rows, and the second and fourth data lines DL11 and 21 to the pixel circuits included in the even-numbered rows. Propagate luminance data. First, the first selection line S
The selection signal of L10 becomes high, and the first and fifth pixels Pix
First and third data lines DL to 10 and Pix 11, respectively.
After the initialization data flowing to 10, DL20 is written, the brightness data flowing to the first and third data lines DL10, DL20 is written.

When the luminance data is written in the first and fifth pixels Pix10 and Pix11, the second selection line SL2
The 0 select signal goes high. Meanwhile, the second and sixth pixels P
Second and fourth data lines DL with respect to ix20 and Pix21
After the initialization data flowing in 11 and DL21 are written, the brightness data flowing in the second and fourth data lines DL11 and DL21 are written.

After that, the third and fourth selection lines SL30 and SL4
0 sequentially becomes high, and after the initialization data is written in each row, the luminance data is sequentially written. Thus, while the initialization data is written in a certain row, the brightness data is written in the next row in which the brightness data is to be written via different data lines.

FIG. 5 is a time chart showing the relationship between the states of signals flowing through the select line and the data line. The states of the selection signals of the first to fourth selection lines SL10 to SL40 are shown by high and low. The first to fourth data lines DL10 to DL21 include
Luminance data and initialization data to be written to each pixel flow, but they are simply shown as high and low in the figure. In the present embodiment, the initialization data and the brightness data alternately flow through each data line.

When the signal on the first selection line SL10 goes high, the initialization data flows through the first basic data line DL100 and is written in the pixel circuits in the first row. Immediately after that, the luminance data flows to the first basic data line DL100 and is written in the pixel circuit of the first row. When the brightness data is written, the second selection line SL20 becomes high, and the initialization data flows to the second selection line SL20, and the initialization data is written in the pixel circuit in the second row. Immediately after that, the second basic data line DL10
Luminance data flows to 1 and is written in the pixel circuit of the second row. Thus, the first selection line SL10, the second selection line SL20, the third selection line SL30, and the fourth selection line SL4.
It becomes high in the order of 0, and the initialization data and the luminance data are sequentially written into the pixel circuit in the order of the first row, the second row, the third row, and the fourth row.

According to the above configuration, by performing the initialization before writing the brightness data, the residual charge in the OLED can be eliminated and the afterimage phenomenon can be reduced. Further, since two data lines as sub-lines are provided in each column, it is possible to simultaneously write the initialization data to the pixels of the next row while writing the luminance data to the pixels of a certain row. Further, the afterimage phenomenon can be reduced without increasing the number of new elements.

(Second Embodiment) In the present embodiment,
The writing of the initialization data is performed not only immediately before the writing of the luminance data but at an arbitrary timing. This makes it possible to adjust the brightness by arbitrarily setting the light emission time from light emission to extinction. The configuration of the display device according to this embodiment is the same as that of the first embodiment, and thus the description thereof is omitted. Hereinafter, differences from the first embodiment will be mainly described.

FIG. 6 is a time chart showing the relationship between the states of signals flowing through the selection lines and the data lines in the display device of this embodiment. The selection control circuit 102 sets the write timing of the initialization data so as to adjust the brightness according to the light emission time. As shown, the first select line SL10
When the signal on the first line goes high, the first basic data line DL10
Luminance data flows to 0 and is written in the pixels in the first row.
After that, the signal of the first selection line SL10 becomes high again at the timing when a predetermined period has elapsed. At that time, the initialization data flows through the first basic data line DL100.
It is written in the pixel of the row. The first selection line SL10, the second selection line SL20, the third selection line SL30, and the fourth selection line SL40 become high in this order, and the writing of the luminance data or the writing of the initialization data is performed in that order. Done. Since the light emission brightness changes according to the light emission time, if the delay amount n set in the selection control circuit 102 is adjusted as the time from writing the brightness data to writing the initialization data, the brightness of each pixel is digitally displayed. Can be adjusted.

(Third Embodiment) In the display device of this embodiment, three selection lines are provided for each row of pixels. Each of these three selection lines corresponds to one of the three primary colors of RGB, and each pixel has R (red), G (green), B
It emits light in one of the colors (blue). The display control device according to the present embodiment can individually adjust the luminance for each emission color by individually setting the time from the writing of the luminance data to the writing of the initialization data for each emission color.

FIG. 7 shows a display device 6 according to this embodiment.
The circuit structure for pixels is shown. The first to third pixels Pi in the first row
x10, Pix11, and Pix12 are arranged, and the fourth to sixth pixels Pix20, Pix21, and Pix22 are arranged in the second row. The first to third selection lines SL1 are provided for the pixels on the first row.
0, SL11, SL12 are connected. First pixel Pi
The first selection line SL10 is connected to x10, the second selection line SL11 is connected to the second pixel Pix11, and the third selection line SL12 is connected to the third pixel Pix12. The fourth to sixth select lines SL20, S are provided for the pixels in the second row.
L21 and SL22 are connected. Fourth pixel Pix20
Is connected to the fourth selection line SL20, and the fifth pixel Pi
The fifth selection line SL21 is connected to x21, and the sixth selection line SL22 is connected to the sixth pixel Pix22.

Two data lines are connected to each pixel column. In the first column, the first data line DL10 is connected to the first pixel Pix10, and the second data line DL11 is connected to the fourth pixel Pix20. In the second column, the third data line DL20 is connected to the second pixel Pix11, and the fourth data line DL is connected to the fifth pixel Pix21.
21 is connected. In the third column, the third pixel Pi
The fifth data line DL30 is connected to x12, and the sixth data line DL31 is connected to the sixth pixel Pix22.

Regarding the first row, the selection control circuit 102 outputs high to the first to third selection lines SL10, SL11, SL12 at the same timing for writing the luminance data,
After that, high is output for writing the initialization data at different timings. Similarly for the second row, the selection control circuit 102 includes the fourth to sixth selection lines SL20, SL21,
High is output to SL22 for writing luminance data at the same timing, and thereafter, high is output for writing initialization data at different timings.

FIG. 8 is a time chart showing the relationship between the states of signals flowing through the select line and the data line. Regarding the first row, the signals of the first to third selection lines SL10, SL11, SL12 become high at the same timing. At that time, the luminance data flows in the signal of the first basic data line DL100, and 1
It is written in each pixel of the row. Next, regarding the second line, the fourth
The signals on the selection lines SL20, SL21, and SL22 of ~ 6 become high at the same timing. At that time, the luminance data flows in the signal of the second basic data line DL101 and is written in each pixel in the second row.

After the elapse of a predetermined period, the selection signal becomes high for writing the initialization data at a different timing for each emission color. That is, for the first row, the signal of the third selection line SL12 first becomes high, and then the first selection line SL10 and the second selection line SL11 become high in this order. When these selection lines become high, the initialization data flows in the signal of the first basic data line DL100, so that the pixels connected to the respective selection lines are initialized in that order.

Also for the second row, the third select line SL2
2, the fourth select line SL20, and the fifth select line SL21 become high in this order, and at that time, the second basic data line DL101.
Since the initialization data flows in the signal of, the pixels connected to the respective selection lines are initialized in that order.

As described above, the brightness is adjusted for each emission color by performing initialization at different timings for each emission color. The timing of writing the initialization data can be adjusted by setting the delay amount n in the selection control circuit 102. For example, the initialization data write timing may be set according to the degree of deterioration of the optical element. Since different luminescent materials are used for each luminescent color, the degree of deterioration may differ, but in the present embodiment, the color balance can be corrected later.

(Fourth Embodiment) In the present embodiment,
The difference from the first embodiment is that each column has one data line. Hereinafter, differences from the first embodiment will be mainly described.

FIG. 9 shows a display device 2 according to the present embodiment.
The circuit structure for pixels is shown. The first data line DL10 is
It is connected to both the first and second pixels Pix10 and Pix20. The first select line SL10 goes high and the data line D
Initialization data flows to L10, and immediately after that data line D
Luminance data flows to L10. After that, the second selection line S
L20 becomes high, initialization data flows through the data line DL10, and immediately after that, luminance data flows through the data line DL10.

FIG. 10 is a time chart showing the relationship between the states of signals flowing through the select line and the data line. The data control circuit 104 outputs the initialization data in the first half of the period in which the selection signal is activated, and outputs the luminance data to be actually set in the second half. In the first half of the period when the selection signal of the first selection line SL10 becomes high, the basic data line DL1
Initialization data flows in 00, and luminance data flows in the latter half. After that, the selection signal of the second selection line SL20 becomes high, and in the period in which the selection signal becomes high, the initialization data flows to the basic data line DL100 in the first half, and the luminance data flows in the second half. After that, the third and fourth selection lines DL30 and DL4
The selection signal of 0 sequentially becomes high, and the same processing is performed.

Also with the above configuration, since the initialization is performed immediately before writing the luminance data, the residual charge on the OLED is eliminated and the afterimage phenomenon is reduced.

(Fifth Embodiment) The data control circuit 104 in the present embodiment differs from the first embodiment in that the number of shift registers included in this circuit is the same as the number of pixel columns. Hereinafter, differences from the first embodiment will be mainly described.

FIG. 11 illustrates the internal structure of the data control circuit. The number of pixel columns is n. Data control circuit 104
Are the first to n-th data shift registers SR11 to SRn, which are the same in number as the number of pixel columns, and the first to second, which is twice the number of pixel columns.
n transistors Tr100 to Tr2n are included.

First to nth data shift registers SR1
1 to SRn are the first and second transistors Tr100 and T100.
After outputting a high signal to the gate electrode of r101, the third and fourth transistors Tr102 and Tr103
Up to n−1, 2n transistors Tr2n−1, Tr2n, a high signal is sequentially output to their gate electrodes.
During that time, luminance data flows through the first basic data line DL100, which is the first, third to 2n-1th data lines D.
It flows in order to L10, DL20, DL2n-1. On the other hand, since data corresponding to zero flows as the initialization data in the second basic data line DL101,
Second and fourth to 2nth transistors Tr101 and Tr103
To Tr2n are turned on, the second, fourth to 2nth data lines D
The pixels connected to L11, DL21, and DL2n are initialized.

From the nth data shift register SRn to the 2n-1, 2n transistors Tr2n-1, Tr2.
The output to n is the first data shift register SR11.
Entered in. After that, again, after outputting a high signal to the gate electrodes of the first and second transistors Tr100 and Tr101, the third and fourth transistors Tr102 and Tr101 are output.
103 to 2n-1, 2n-th transistor Tr2n-
Up to 1 and Tr2n, a high signal is sequentially output to those gate electrodes. Meanwhile, the second basic data line DL101
Since luminance data flows to the second to fourth data lines DL11, DL21, and DL2n in order. On the other hand, since data corresponding to zero flows in the first basic data line DL100 as initialization data, the first, third to 2n−1th transistors Tr100,
Even if Tr102 to Tr2n-1 are turned on, the first, third and second
Pixels connected to the n-1 data lines DL10, DL20, DL2n-1 are initialized.

According to the configuration of this embodiment, the operation of the data control circuit 104 can be realized with a simpler configuration than that of the first embodiment. In the data control circuit 104 of the first embodiment shown in FIG. 3, a data shift register corresponding to each transistor is provided. In that case, since each selection transistor does not output high to the transistor of the data line to which the brightness data is not written, the data output is dispersed, so that the power supply voltage for the data output is more than that of the present embodiment. The influence of fluctuation can be reduced.

(Sixth Embodiment) In this embodiment,
This is different from the first to fourth embodiments in that each of the two sub-lines provided in each column divides the pixel circuit to which the luminance data is to be propagated into two regions, an upper region and a lower region. The display device of this embodiment includes pixel circuits for 256 rows. Hereinafter, differences from the first embodiment will be mainly described.

FIG. 12 shows a circuit configuration for 7 pixels of the display device in this embodiment. As shown in the figure, the plurality of pixel circuits arranged in a matrix are divided into upper and lower regions. The upper region 200 and the lower region 202 each include a pixel circuit for 128 rows. In the pixel circuit included in the row of the upper region 200, the luminance data or the initialization data is written via the left subline of the two sublines provided in each column. Specifically, the first to third pixels Pix1, Pix2, and Pix3 are written from the first data line DL10.

In the pixel circuit included in the row of the lower region 202, the luminance data or the initialization data is written via the right subline of the two sublines provided in each column. Specifically, 129th, 130th, 13th
1, 256 pixels Pix129, Pix130, Pix
131 and Pix256 are written from the second data line DL11.

Since it is sufficient to write the luminance data or the initialization data only in the upper area 200, the first data line 10 may have a length of about half the entire pixel area.
Therefore, the structure is simplified and the aperture ratio is improved.

While the brightness data flows through the first data line DL10, the initialization data flows through the second data line DL11. For example, when the brightness data is written in the first pixel Pix1, the initialization data is written in the 129th pixel Pix129. The selection control circuit 102 simultaneously outputs a high level to any one selection line that selects the pixel circuit in the upper region 200 and any one selection line that selects the pixel circuit in the lower region 202.

The selection control circuit 102 of this embodiment includes the same number of selection shift registers as the number of rows of pixel circuits. Since the display device of this embodiment includes 256 rows of pixel circuits, the number of shift registers for selection is also 256. The internal configuration of the selection control circuit 102 is as shown in FIG. However, it differs from the first embodiment in that the first clock data CD10 outputs high to the second AND circuit AND20 twice at the start of operation and 128 clocks later. First, the second AND circuit AN is initially set.
The first shift register SR10, to which high has been input from the OR circuit OR via D20, outputs high to the first select line SL1. Subsequently, a high level is output stepwise from the second to 127th selection shift registers SR20 to SR1270 to the second to 127th selection lines SL20 to SL1270.
When high is input to the 128th shift register SR1280 for selection, the first clock data CD10 becomes high again, and the second AND circuit AND20 causes the OR circuit OR to output the first shift register for selection. High is input to SR10. Thus, the series of the first to 128th selection shift registers SR10 to SR1280 and the first series
29-256 selection shift registers SR1290-S
Each of the R2560 series outputs a high in a stepwise manner in parallel with each other.

Since two rows of pixel circuits are selected at a time, even if the clock frequency of the clock CLK, the set signal, and the first clock data CD10 is set to 1/2 of the clock frequency in the first embodiment. The writing speed of one frame can be made the same, which can reduce the power consumption.

FIG. 13 is a time chart showing the relationship between the states of signals flowing through the select line and the data line in this embodiment. As shown, the first select line SL1 and the twelfth select line SL1
The selection line SL129 of 9 becomes high at the same time, and the second selection line SL129
The select lines SL2 and SL130 of 130 become high, and the select lines SL3 and SL131 of the third and 131 become high simultaneously.

The first basic data line DL100 includes the first to first
While the high level is sequentially output to each of the 128 selection lines SL1 to SL128, the luminance data is continuously propagated to the pixels of the upper region 200 to which they are connected. Simultaneously with this, the 129th to 256th selection lines SL
While the high signals are sequentially output to each of 129 to SL256 in a stepwise manner, the initialization data is continuously propagated to the pixels of the lower region 202 to which they are connected. That is, while the brightness data continuously flows to the first data line DL100, the initialization data continuously flows to the second data line DL101. While the initialization data continuously flows to the first data line DL100, the second data line DL10
The luminance data continuously flows to 1.

According to the above configuration, the afterimage phenomenon can be reduced with a relatively simple configuration as in the first embodiment. In particular, the area required for arranging the data lines can be reduced in the region where the pixel circuits are arranged.

(Seventh Embodiment) In the present embodiment,
This is different from the sixth embodiment in that two sub lines in each row are arranged on a substantially straight line. Hereinafter, differences from the sixth embodiment will be mainly described.

FIG. 14 shows a circuit configuration for 6 pixels of the display device according to the present embodiment. The first data line DL10 and the second data line DL11 in the present embodiment are arranged on the respective extension lines and at positions not adjacent to each other. The second data line DL11 extends to the lower region 202 without passing through the upper region 200. That is, the wiring extends from the data control circuit 104 so as to bypass the selection control circuit 102, extends to the side symmetrical with the data control circuit 104, and is wired so as to enter the area of the pixel circuit from below. The area occupied by the data lines in the region of the pixel circuit is sufficient for each column, so that the aperture ratio can be improved as compared with the other embodiments.

The present invention has been described above based on the embodiments. This embodiment is merely an example, and it will be understood by those skilled in the art that various modifications can be made to the combination of each constituent element and each processing process, and such modifications are also within the scope of the present invention. .

In the sixth and seventh embodiments, the upper region 20
For the 0 pixel, the first, second and third select lines SL1, SL
2 and SL3 are output in this order, and the selection lines SL12 of the 129th, 130th, and 131th pixels are output to the pixels in the lower region 202.
High is output in the order of 9, SL130, and SL131. That is, the pixels in the upper region 200 and the lower region 202 are both selected in ascending order. In the modification, the pixels in the upper region 200 are selected in ascending order while the lower region 2 is selected.
The 02 pixels may be selected in descending order. While selecting the pixels of the upper region 200 in descending order, the lower region 20
The two pixels may be selected in ascending order. Also in these cases, the internal configuration of the selection control circuit 102 can be simplified.

In each embodiment, two or more switch elements for setting data in the drive element may be arranged in series. At that time, the characteristics of these transistors such as the current amplification factor may be different. For example, if the current amplification factor of the transistor close to the driving element is set to be low, the effect of reducing the leakage current is great. Further, the characteristics of these switch element and drive element may be changed. For example, when the current amplification factor of the drive element is reduced, the range of setting data corresponding to the same brightness range is widened, which facilitates brightness control.

According to the present invention, the display quality of a display device can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of two pixels of a display device according to a first embodiment.

FIG. 2 is a diagram illustrating an internal configuration of a selection control circuit.

FIG. 3 is a diagram illustrating an internal configuration of a data control circuit.

FIG. 4 is a diagram showing a circuit configuration of eight pixels of a display device.

FIG. 5 is a time chart showing the relationship between the states of signals flowing through a select line and a data line.

FIG. 6 is a time chart showing a relationship between states of signals flowing through a selection line and a data line in the display device of the second embodiment.

FIG. 7 is a diagram showing a circuit configuration of 6 pixels of a display device according to a third embodiment.

FIG. 8 is a time chart showing a relationship between states of signals flowing through a selection line and a data line.

FIG. 9 is a diagram showing a circuit configuration of two pixels of a display device according to a fourth embodiment.

FIG. 10 is a time chart showing a relationship between states of signals flowing through a selection line and a data line.

FIG. 11 is a diagram illustrating an internal configuration of a data control circuit according to a fifth embodiment.

FIG. 12 is a diagram showing a circuit configuration of 7 pixels of a display device according to a sixth embodiment.

FIG. 13 is a time chart showing a relationship between states of signals flowing through a selection line and a data line in the sixth embodiment.

FIG. 14 is a diagram showing a circuit configuration of 6 pixels of a display device in a seventh embodiment.

FIG. 15 is a diagram showing a circuit configuration for one pixel of a display device in the related art.

[Explanation of symbols]

10, 20 OLED, Vdd power supply line, DL
100, DL101 basic data line, DL10, DL1
1, DL20, DL21, DL30, DL31 data line, SL10, SL20, SL30 select line, Tr
10, Tr11, Tr12, Tr13, Tr100, T
r101, Tr102, Tr103 transistors, P
ix10, Pix11, Pix12, Pix20, Pi
x21, Pix22, Pix30, Pix31, Pix
40, Pix41 pixels, 100 display control circuit, 1
02 selection control circuit, 104 data control circuit.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 642 G09G 3/20 642A

Claims (10)

[Claims] 1. A plurality of pixel circuits, first and second sub-lines obtained by dividing a data line for transmitting luminance data to be written in the pixel circuit, and a plurality of pixel circuits which should be originally connected to the same data line. Among the pixel circuits connected to the first sub line, while writing the luminance data to the pixel circuit connected to the first sub line, the second sub line is connected to the pixel circuit connected to the second sub line. And a display control circuit for writing initialization data via the display device. 2. The display control circuit includes a data control circuit for propagating, as the initialization data, data corresponding to zero in the case of luminance data to the first and second sub-lines. The display device according to claim 1. 3. The display control circuit according to claim 1, wherein the display control circuit includes a selection control circuit that sets a write timing of initialization data for a pixel circuit based on a write timing of luminance data for the pixel circuit. Display device. 4. The display device according to claim 3, wherein the selection control circuit sets a write timing of the initialization data so as to adjust brightness according to a light emission time. 5. The pixel circuit further includes a plurality of select lines that propagate a select signal that determines the write timing of the brightness data, and the pixel circuit includes the plurality of select lines and the first or second sub-line. The display control circuit is arranged in an intersecting portion, and the display control circuit propagates a selection signal for the pixel circuit connected to the first sub-line to an odd-numbered selection line of the plurality of selection lines and an even-numbered selection line. ,
The display device according to claim 1, further comprising a selection control circuit that propagates a selection signal for the pixel circuit connected to the second sub-line. 6. The brightness data should be written next while writing the brightness data to the plurality of pixel circuits arranged in a matrix and the pixel circuits included in any of the rows via the data line. A display control circuit for writing initialization data to a pixel circuit included in a row through a data line different from the data line. 7. A plurality of pixel circuits each of which emits light in any one of a plurality of colors, and a period from writing of luminance data to writing of initialization data to the pixel circuits is changed according to the emission color. And a display control circuit for individually setting the display device. 8. In the first half of the period in which a plurality of pixel circuits and a selection signal that determines the writing timing of the luminance data to the pixel circuits are activated, the first half is set to zero if the luminance data is initialization data. A display device, comprising: a display control circuit that outputs corresponding data and outputs luminance data to be actually set in the second half. 9. Luminance data is written to a plurality of pixel circuits arranged in a matrix and pixel circuits included in an upper region of the matrix of pixel circuits via a first data line. In between, a display control circuit that writes initialization data to a pixel circuit included in a lower region of the matrix of pixel circuits via a second data line different from the first data line, A display device having. 10. The display device according to claim 9, wherein the first data line and the second data line are arranged at positions on extension lines of each other and not adjacent to each other.