WO2015029336A1

WO2015029336A1 - Display device and display method

Info

Publication number: WO2015029336A1
Application number: PCT/JP2014/004051
Authority: WO
Inventors: 小倉　潤
Original assignee: 凸版印刷株式会社
Priority date: 2013-08-26
Filing date: 2014-08-01
Publication date: 2015-03-05
Also published as: JP2015043030A; TW201513080A

Abstract

Provided are a display device and display method that can suppress changes in image quality caused by changing of organic EL device and transistor element characteristics because of increases in the temperature of a display panel caused by the generation of heat by pixel circuits providing drive current to light-emitting elements. The display device is provided with: a plurality of pixel circuits that include transistors for supplying drive current to light-emitting elements; a plurality of dummy pixel circuits that have constitutions identical with the pixel circuits and do not carry out operations providing drive current to light-emitting elements; a selection driver that selects any one of a plurality of scanning lines as a target of selection; and a control unit that controls the driving of the selection driver. Gradient display operations, non-gradient display operations, and detection operations for detecting the characteristics of transistors are repeated in this order, and gradient display voltage is corrected using the results of detection obtained by the detection operations. Detection operations for detecting the characteristics of the transistors are carried out through data lines for the dummy pixel circuits and the temperature characteristics of the pixel circuits are corrected.

Description

Display device and display method

The technology of the present disclosure relates to a display device including a light emitting element to which a driving current is supplied through a transistor, and a display method.

2. Description of the Related Art Display devices that sequentially drive a plurality of electroluminescent elements (EL elements) arranged in a matrix by scanning line scanning are known (see, for example, Patent Documents 1 and 2). In the display device described in Patent Document 1, supply of drive current to a plurality of organic EL elements connected to one scanning line is controlled by a current control transistor and a sampling transistor, which are two transistors for each organic EL element. Is done. Each time the sampling transistor is switched to a conductive state, a voltage is applied between the gate and the source of the current control transistor at a level corresponding to the display data. As a result, a drain current based on the gate-source voltage of the current control transistor is supplied as a drive current to the organic EL element, and the gradation of light emission luminance is controlled for each organic EL element.

JP-A-8-330600 JP 2010-128397 A

However, a light emitting element such as an organic EL display device has a problem in that characteristic deterioration of the organic EL element is accelerated by an increase in display panel temperature accompanied by environmental temperature and heat generation due to its own light emission. In addition, when active matrix driving is performed, there is a problem in that deterioration of transistor characteristics due to temperature rise is also accelerated.
The technology of the present disclosure provides a display device and a display method capable of suppressing a change in image quality due to a change in characteristics of a light emitting element and a transistor element due to a panel temperature rise in a pixel circuit that supplies a driving current to the light emitting element. For the purpose.

One aspect of the present invention for solving the above problems is a plurality of pixel circuits including a transistor that supplies a driving current to the light-emitting element, and a plurality of pixel circuits that have the same configuration as the pixel circuit and do not perform a driving current supply operation to the light-emitting element. A dummy pixel circuit, a plurality of scanning circuits connected to each of the plurality of pixel circuits and the plurality of dummy pixels, and a plurality of data connected to each of the plurality of pixel circuits and the plurality of dummy pixels. A selection driver that selects one of the plurality of scanning lines as a selection target, and a control unit that controls driving of the selection driver. The control unit applies each scanning line to the pixel circuit. A grayscale display operation that applies a grayscale display voltage to the pixel circuit connected to each selection target through the data line to place the light emitting element in a grayscale display state, and each scanning line is selected in turn. A non-grayscale display operation in which a non-grayscale display voltage is applied to a pixel circuit connected to each selection target through a data line to place the light emitting element in a non-grayscale display state, and a plurality of scans in the non-grayscale display state A gray scale is displayed using the detection result obtained by the detection operation by repeating a detection operation in which a part of the line is selected and the pixel circuit connected to the selection target detects the characteristics of the transistor through the data line in this order. The voltage is corrected, the dummy pixel circuit is made to select a part of the plurality of scanning lines, and the dummy pixel circuit connected to the selection target performs a detection operation for detecting the characteristics of the transistor through the data line. A display device that corrects temperature characteristics.

Another aspect of the present invention for solving the above problems is to sequentially select any one of a plurality of scanning lines connected to a pixel circuit including a transistor that supplies a driving current to a light emitting element as a selection target, and select A gradation display operation in which a gradation display voltage is applied to a pixel circuit connected to a target through a data line to bring the light emitting element into a gradation display state, and a non-scale is applied to the pixel circuit connected to a target through a data line. A non-grayscale display operation in which a light-emitting element is applied to a non-grayscale display state by applying a grayscale display voltage, and a pixel circuit connected to a selection target by selecting a part of a plurality of scanning lines in the non-grayscale display state On the other hand, the detection operation of detecting the characteristics of the transistor through the data line is repeated in this order, and the gradation display voltage is corrected using the detection result obtained by the detection operation.

According to the display device of the present disclosure, it is possible to suppress a change in image quality due to a change in element characteristics in the pixel circuit that supplies the driving current to the light emitting element, and to display the panel temperature in the pixel circuit that supplies the driving current to the light emitting element. A change in image quality due to a change in the characteristics of the light emitting element and the transistor element due to the rise can be suppressed.

FIG. 1 is a block diagram showing the overall configuration of a display device according to an embodiment of the present invention. FIG. 2 is a block diagram functionally showing the configuration of the control unit in one embodiment of the present invention. FIG. 3 is a circuit diagram showing the configuration of the pixel circuit and the configuration of the data driver in one embodiment of the present invention. FIG. 4 is a diagram showing the relationship between the display voltage applied to the pixel circuit and the drain current in the current control transistor in one embodiment of the present invention. FIG. 5 is a diagram showing the temperature dependence (high temperature and room temperature) of the relationship between the display voltage applied to the pixel circuit and the drain current in the current control transistor in one embodiment of the present invention. FIG. 6 is a timing chart showing the transition of the level of each control signal together with the state of each switch in the threshold detection operation according to the embodiment of the present invention. FIG. 7 is a diagram showing the relationship between the potential of the data line and the relaxation time in one embodiment of the present invention. FIG. 8 is a diagram showing the temperature dependence of the threshold voltage measurement of the dummy pixel circuit in one embodiment of the present invention. FIG. 9 is a diagram showing the temperature dependence of the measurement result at t0 in FIG. 8 (linear correlation with temperature) in one embodiment of the present invention. FIG. 10 is a diagram showing a flow of data calculation correction output in one embodiment of the present invention (temperature control is multiplication correction, and threshold voltage correction is addition correction). FIG. 11 is a timing chart showing the transition of the level of each control signal along with the state of each switch during the display operation period in one embodiment of the present invention. FIG. 12 is a diagram schematically illustrating the timing of various operations performed in the first frame according to the embodiment of the present invention for each of the pixels from the first row to the 540th row. FIG. 13 is a diagram schematically illustrating the timing of various operations performed in the second frame in one embodiment of the present invention for each of the pixels from the first row to the 540th row. FIG. 14 is a diagram schematically illustrating the timing of various operations performed in the 540th frame for each of the pixels from the first row to the 540th row in the embodiment of the present invention. FIG. 15 is a diagram schematically illustrating the timing of various operations performed in the dummy row before the first frame in each of the pixels of the 540th row from the pixels in the dummy row in the embodiment of the present invention. FIG. 16 is a diagram schematically illustrating the timing of various operations performed in the dummy row after the 540th frame for each of the pixels from the first row to the dummy row in the embodiment of the present invention. FIG. 17 shows the timing of various operations performed in the dummy row after the 540th frame in the configuration in which the dummy row is provided before the first frame and after the 540th frame in one embodiment of the present invention. ) To a dummy row (second row) of pixels. FIG. 18 is a timing chart showing changes in the levels of various control signals for each scanning line and power supply line during a period in which one frame is displayed in one embodiment of the present invention. FIG. 19 is a timing chart showing the transition of the levels of various control signals for each scanning line and power supply line during a period in which one frame is displayed in one embodiment of the present invention. FIG. 20 is a diagram showing an example of luminance control means when the display panel temperature becomes high in one embodiment of the present invention (for example, the luminance is lowered at 50 ° C. or more, and deterioration of the organic EL and TFT is caused). Suppress).

(Embodiment)
The display device according to this embodiment will be described with reference to FIGS.

The display device of the present embodiment uses an active matrix driving method to cause an organic EL element as a light emitting element to emit light. The display operation of one frame in the display device includes a gradation display operation in which an image based on display data is displayed and a non-gradation display operation in which a black image is displayed. At this time, in the period in which the non-gradation display operation is performed, a voltage related to the threshold voltage of the current control transistor included in the pixel circuit is detected for each of the plurality of pixels connected to the specific scanning line. The display voltage applied to the pixel circuit based on the display data is corrected using the detection result relating to the threshold voltage and its temperature dependency. That is, a period during which one frame is displayed includes a display operation in which a grayscale display operation and a non-grayscale display operation are alternately repeated, and a threshold detection operation for detecting a voltage related to the threshold voltage. It is. Below, these display operations and threshold value detection operations will be mainly described.

[Configuration of display device]
The overall configuration of the display device will be described with reference to FIG. FIG. 1 is a block diagram illustrating an overall configuration of a display device according to the present embodiment.
As shown in FIG. 1, the display panel 10 has a plurality of pixels Px arranged in a matrix of m rows × n columns. m is an integer of 1 or more, and n is an integer of 1 or more. In each of the plurality of pixels Px, one organic EL element and one pixel circuit for supplying a driving current to the organic EL element are arranged.

Each of the plurality of pixels Px is arranged near a point (intersection) where the m scanning lines Ls extending along the row direction and the n data lines Ld extending along the column direction intersect in plan view. Yes. Each of the n pixels Px arranged in the row direction is connected to a common scanning line Ls and a common power supply line La. Each of the m pixels Px arranged in the column direction is connected to a common data line Ld.

Each of the m scanning lines Ls is connected to the selection driver circuit 20, each of the m power lines La is connected to the power driver 30, and each of the n data lines Ld is connected to the data driver circuit 40. Yes. Each of the selection driver circuit 20, the power supply driver 30, and the data driver circuit 40 is driven by the control unit 50. The control unit 50 is configured mainly with a microcomputer having a central processing unit and a storage unit, and generates display data using image data input to the control unit 50.

The selection driver circuit 20 is composed of, for example, a shift register and a buffer. The selection driver circuit 20 applies either the high level selection voltage VgH or the low level non-selection voltage VgL to each scanning line Ls in accordance with a control signal from the control unit 50. The selection driver circuit 20 sets the scanning line Ls to which the selection voltage VgH is applied as a selection target, and sequentially switches the selection target candidates from the first scanning line Ls to the m-th scanning line Ls as the final row. .

The power supply driver 30 is composed of, for example, a shift register and a buffer. The power supply driver 30 applies either the high level drive voltage ELVDD or the low level write voltage WDVSS to each power supply line La in accordance with a control signal from the control unit 50. The power supply driver 30 switches the target row to which the drive voltage ELVDD is applied from the first power supply line La to the mth power supply line La, which is the final row, in accordance with the selection of the scanning line Ls.

In the gradation display operation, the data driver circuit 40 generates a display voltage Vd based on gradation display display data for each data line Ld as a gradation display voltage in accordance with a control signal input from the control unit 50. . The data driver circuit 40 applies the display voltage Vd for gradation display all at once to each of the n data lines Ld in accordance with a control signal input from the control unit 50.

In the non-gradation display operation, the data driver circuit 40 generates the display voltage Vd as the non-gradation display voltage for each data line Ld according to the control signal input from the control unit 50. The data driver circuit 40 applies the display voltage Vd for non-gradation display simultaneously to each of the n data lines Ld according to a control signal input from the control unit 50.

In the threshold detection operation, the data driver circuit 40 applies a common detection voltage Vm to each of the n data lines Ld in response to a control signal input from the control unit 50. The data driver circuit 40 outputs the detection result of the voltage of each of the n data lines Ld to the control unit 50 in order from the first data line Ld according to the control signal input from the control unit 50.

[Configuration of Control Unit 50]
The configuration of the control unit 50 will be described with reference to FIG. FIG. 2 is a block diagram functionally showing the configuration of the control unit 50 in the present embodiment.
As shown in FIG. 2, the adjustment unit 51 handles the image data input to the adjustment unit 51 as gradation data for each pixel Px. The adjustment unit 51 uses a lookup table for performing various adjustments on the gradation data for each pixel Px and the image data input to the adjustment unit 51, and performs gamma correction on the gradation data for each pixel Px. Various adjustments such as initial luminance adjustment and chromaticity adjustment are performed.

The data storage unit 52 includes m rows × n columns of storage areas associated with each of the plurality of pixels Px. The data storage unit 52 inputs detection data Dout, which is data related to the threshold voltage Vth for each pixel Px, from the data driver circuit 40. The data storage unit 52 stores the detection data Dout for each pixel Px input to the data storage unit 52 in a storage area associated with the pixel Px. Each time the detection data Dout for each pixel Px is input, the data storage unit 52 updates the detection data Dout associated with the pixel Px.

The correction unit 53 reads the detection data Dout for each pixel Px stored in the data storage unit 52 and the gradation data for each pixel Px input from the adjustment unit 51. The correction unit 53 performs an addition / subtraction operation on the gradation data for each pixel Px based on the detection data Dout for each pixel Px to generate an output as display data Din for each pixel Px, and uses the display data Din as a data driver circuit. Output to 40.

The clock generator 54 generates a data shift clock signal Clkd, a display shift clock signal Clks, and a detection shift clock signal Clkr. The clock generation unit 54 outputs the data shift clock signal Clkd to the data driver circuit 40, and outputs the display shift clock signal Clks and the detection shift clock signal Clkr to the selection driver circuit 20 at different timings.

The data shift clock signal Clkd determines the timing at which the display data Din for each pixel Px is input from the correction unit 53 to the data driver circuit 40. Each time the data shift clock signal Clkd rises, the data driver circuit 40 displays the display data Din corresponding to the pixel Px in the first column, the display data Din corresponding to the pixel Px in the second column,. Display data Din for each pixel Px is input in the order of display data Din corresponding to. The data driver circuit 40 associates the display data Din for each pixel Px with the data line Ld to which the pixel Px is connected in the clock cycle of the data shift clock signal Clkd.

The display shift clock signal Clks determines a cycle in which candidates for selection are switched in the gradation display operation. In addition, the display shift clock signal Clks determines a cycle in which candidates for selection are switched in the non-gradation display operation. Each time the display shift clock signal Clks rises, the selection driver circuit 20 sets the scanning line Ls to 1 in the order of the first scanning line Ls, the second scanning line Ls,..., The mth scanning line Ls. Select books one by one. The display clock cycle, which is the clock cycle of the display shift clock signal Clks, is sufficiently longer than the clock cycle of the data shift clock signal Clkd. For example, the display clock cycle is n times the clock cycle of the data shift clock signal Clkd.

The detection shift clock signal Clkr determines a cycle in which a candidate to be selected is switched in the threshold detection operation. Each time the detection shift clock signal Clkr rises, the selection driver circuit 20 applies the selection voltage VgH in order of the first scanning line Ls, the second scanning line Ls,. The candidate to be switched is switched one by one. The detection clock cycle that is the clock cycle of the detection shift clock signal Clkr is sufficiently shorter than the display clock cycle.

For example, the detection clock cycle is the same as the clock cycle of the data shift clock signal Clkd. Then, the selection driver circuit 20 scans the candidate to which the selection voltage VgH is applied in the display clock cycle in the gradation display operation, and displays the candidate to which the selection voltage VgH is applied in the display clock cycle even in the non-gradation display operation. Scan with a period. On the other hand, in the threshold detection operation, the candidate to which the selection voltage VgH is applied is scanned with a detection clock cycle shorter than the display clock cycle.

The detection shift clock signal Clkr includes a shift standby portion in which the low level is maintained only during the threshold detection period while the high level and the low level are repeated in the detection clock cycle. The timing at which the shift standby portion is output is shifted every time the detection shift clock signal Clkr is output, that is, every time a threshold detection operation is performed.

For example, in this threshold value detection operation, the high level and the low level are repeated q times in the detection clock cycle (1 ≦ q ≦ m) in the detection shift clock signal Clkr, and then the shift standby part Is output. On the other hand, in the next threshold detection operation, the high level and the low level are repeated q + 1 times (1 ≦ q ≦ m) in the detection shift clock signal Clkr, and then the shift standby portion is output. . As a result, in the current threshold detection operation, the first scanning line Ls to the qth scanning line Ls are sequentially switched in the detection clock cycle as candidates for selection. Then, after the threshold detection period elapses, the switching from the q + 1th scanning line Ls to the mth scanning line Ls is sequentially switched in the detection clock cycle as candidates for selection. In the next threshold value detection operation, the first scanning line Ls to the (q + 1) th scanning line Ls are switched as selection candidates at the detection clock cycle. Then, after the threshold detection period elapses, the scan from the (q + 2) th scanning line Ls to the mth scanning line Ls is again scanned with a detection clock cycle as a candidate for selection.

The pulse generator 55 generates a start pulse signal SP1, a latch pulse signal LP, a start pulse signal SP2, and a mask pulse signal MP. The pulse generator 55 outputs the start pulse signal SP1 and the latch pulse signal LP to the data driver circuit 40. The pulse generator 55 outputs the start pulse signal SP2 and the mask pulse signal MP to the selection driver circuit 20 and the clock generator 54, respectively.

The start pulse signal SP1 is a control signal for controlling the timing at which the display data Din for one row is input from the correction unit 53 to the data driver circuit 40. Each time the start pulse signal SP1 is input, the data driver circuit 40 displays the display data for each pixel Px from the display data Din corresponding to the pixel Px in the first column to the display data Din corresponding to the pixel Px in the nth column. Enter Din for one line.

The latch pulse signal LP is a control signal for controlling the timing at which the display data Din for one row is held in the data driver circuit 40. Each time the latch pulse signal LP is input, the data driver circuit 40 displays one row of display data from the display data Din corresponding to the pixel Px in the first column to the display data Din corresponding to the pixel Px in the nth column. Hold Din.

The start pulse signal SP2 is a control signal for controlling the timing for starting the selection of candidate candidates. Each time the start pulse signal SP2 is input, the selection driver circuit 20 sequentially switches from the first scanning line Ls to the m-th scanning line Ls as a selection target candidate.

The start pulse signal SP2 is a control signal for switching a shift clock signal used for switching a candidate to be selected between a display clock cycle and a detection clock cycle. The clock generation unit 54 switches the shift clock signal used for switching the selection target candidate from the display clock cycle to the detection clock cycle each time the start pulse signal SP2 is input for the number of times to be switched.

In this embodiment, the number of times of switching is set to 3 times, and the clock generator 54 changes the clock cycle of the shift clock signal from the display clock cycle to the detection clock cycle every time the start pulse signal SP2 is input 3 times. Change to Thereby, in the gradation display operation, the m scanning lines Ls are sequentially switched in the display clock cycle as candidates for selection. In the non-gradation display operation, first, m scanning lines Ls are sequentially switched in the display clock cycle as candidates for selection, and then, in the threshold detection operation, m scanning lines Ls are selected. Candidates are sequentially switched in the detection clock cycle.

The mask pulse signal MP is a control signal for controlling the output of the shift signal generated by the selection driver circuit 20. When the mask pulse signal MP is at the high level, the selection driver circuit 20 applies the selection voltage VgH to one of the scanning lines Ls based on the shift signal generated by the selection driver circuit 20. On the other hand, when the mask pulse signal MP is at the low level, the selection driver circuit 20 applies the non-selection voltage VgL to all the scanning lines Ls regardless of the shift signal generated by the selection driver circuit 20.

The mask pulse signal MP is normally set to a high level, and is switched from a high level to a low level each time the start pulse signal SP2 is output for the number of times of switching, and the high level is maintained for the threshold detection period. Including an unmasking part. The timing at which the mask release portion is output is synchronized with the output of the shift standby portion, and is shifted each time a threshold detection operation is performed.

For example, in this threshold value detection operation, a high level and a low level are repeated q times (1 ≦ q ≦ m) in the detection shift clock signal Clkr, and then a mask release portion is output. On the other hand, in the next threshold detection operation, the high level and the low level are repeated q + 1 times (1 ≦ q ≦ m) in the detection shift clock signal Clkr, and then the mask release portion is output. Thus, in the current threshold detection operation, first, the first scanning line Ls to the qth scanning line Ls are sequentially switched in the detection clock cycle as candidates for selection. During this period, application of the selection voltage VgH to the scanning line Ls is prohibited. Next, in the threshold detection period in which the selection of the candidate to be selected is stopped, the selection voltage VgH is applied to the q-th scanning line Ls that is the candidate at that time. On the other hand, in the next threshold value detection operation, first, the scanning line from the first scanning line Ls to the q + 1th scanning line Ls is scanned as a selection target candidate in a detection clock cycle. During this period, application of the selection voltage VgH to the scanning line Ls is prohibited. Next, in the threshold detection period in which the selection of the candidate to be selected is stopped, the selection voltage VgH is applied to the q + 1-th scanning line Ls that is the candidate at that time.

[Configuration of Selected Driver Circuit 20]
The configuration of the selection driver circuit 20 will be described with reference to FIG.
As shown in FIG. 2, the shift register circuit 21 receives a start pulse signal SP2, a display shift clock signal Clks, and a detection shift clock signal Clkr from the control unit 50. Each time the start pulse signal SP2 is input, the shift register circuit 21 generates an m-bit parallel signal including one selection target bit as a shift signal. Each time the shift register circuit 21 receives the display shift clock signal Clks, the shift register circuit 21 sequentially shifts one selection target bit in the shift signal line by line from the first line to the m-th line. Each time the shift register circuit 21 receives the shift clock signal Clkr for detection, it also shifts one selection target bit in the shift signal one row at a time from the first row to the m-th row.

The shift register circuit 21 outputs a shift signal generated by the shift register circuit 21 when the mask pulse signal MP input to the shift register circuit 21 is at a high level. On the other hand, when the mask pulse signal MP input to the shift register circuit 21 is at a low level, the shift register circuit 21 does not include a selection target bit regardless of the shift signal generated by the shift register circuit 21. Output a signal. When the shift clock signal is the display shift clock signal Clks, the shift register circuit 21 outputs a shift signal including a selection target bit based on the input of the high level mask pulse signal MP. On the other hand, when the shift clock signal is the detection shift clock signal Clkr, the shift register circuit 21 includes the selection target bit based on the input of the low-level mask pulse signal MP outside the threshold detection period. No shift signal is output. Control of such shift signal output is performed, for example, by providing m logical product circuits corresponding to each bit of the shift signal at the output end of the shift register circuit 21, and each of the m logical product circuits has a mask pulse signal MP. This is realized by inputting.

The level shifter circuit 22 is a voltage adjustment circuit from the low withstand voltage circuit to the high withstand voltage circuit, and receives the shift signal from the shift register circuit 21 to adjust the voltage of the shift signal to the drive level of the buffer circuit 23. The buffer circuit 23 receives the shift signal with the adjusted voltage from the level shifter circuit 22 and adjusts the voltage of the shift signal to the drive level of the pixel Px.

[Configuration of Data Driver Circuit 40]
The configuration of the data driver circuit 40 will be described with reference to FIG. FIG. 3 is a circuit diagram showing the configuration of the pixel circuit and the configuration of the data driver circuit 40 in the present embodiment.
As shown in FIG. 3, the shift register circuit 41, the data register circuit 42, and the data latch circuit 43 are configured as low withstand voltage circuits. These circuits include a logic power source voltage LVDD from a logic power source 60. And a low level logic reference voltage LVSS is applied. The DAC / ADC circuit 44 and the buffer circuit 45 are configured as high withstand voltage circuits, and a high level analog power supply voltage DVSS and a low level analog reference voltage VEE are applied to these circuits from the analog power supply 70. The analog power supply voltage DVSS is set to the same potential as the write voltage WDVSS and the reference voltage ELVSS.

The shift register circuit 41 receives the start pulse signal SP1 and the data shift clock signal Clkd from the control unit 50. Each time the start pulse signal SP1 is input, the shift register circuit 41 outputs a shift signal as an n-bit parallel signal including one selection target bit. Each time the data shift clock signal Clkd is input, the shift register circuit 41 sequentially shifts and outputs one selection target bit in the shift signal.

The data register circuit 42 includes n registers associated with each bit of the shift signal, and one register inputs, for example, 8-bit gradation data from the control unit 50. The data register circuit 42 inputs gradation data to one register selected by one selection target bit. In the data register circuit 42, all the registers are selected by shifting one selection target bit, and display data Din for one row is fetched from the control unit 50.

The data latch circuit 43 includes n data latches 43a associated with the registers of the data register circuit 42, and inputs a common latch pulse signal LP to each of the n data latches 43a from the control unit 50. .

Each input terminal of the n data latches 43a is connected to a corresponding register in the data register circuit 42 in the gradation display operation and the non-gradation display operation. Each of the n data latches 43a holds the gradation data stored in the corresponding register, and synchronizes the holding with the latch pulse signal LP. Each of the n data latches 43 a outputs the gradation data held in the data latch 43 a to the DAC / ADC circuit 44. Thus, the data latch circuit 43 holds the display data Din for one row fetched by the data register circuit 42 for each input of the latch pulse signal LP, and the held display data Din for one row is DAC / ADC. Output to the circuit 44.

Each input terminal of the n data latches 43a is connected to a corresponding detection ADC 44b in the display DAC / ADC 44 in the threshold detection operation. Each of the n data latches 43a holds the data output from the corresponding detection ADC 44b as detection data Dout, and synchronizes the holding with the latch pulse signal LP.

The input terminal of the data latch 43a in the p-th column (1 ≦ p ≦ n) is connected to the output terminal of the data latch 43a in the p + 1 column in the threshold detection operation. Each of the data latches 43a in the p-th column holds the data held in the data latches 43a in the (p + 1) th column as detection data Dout, and synchronizes the holding with the latch pulse signal LP.

The output terminal of the data latch 43a in the first column is connected to the control unit 50 and outputs the detection data Dout held in the data latch 43a in the first column to the control unit 50 in the threshold detection operation. As a result, the data latch 43a in the first column holds all the data held in the data latch 43a in the (p + 1) th column in order from the data latch 43a in the second column, and sequentially holds the held data to the control unit 50. Output.

The data latch circuit 43 is connected to n data latches 43a, n input switches SW1 connected to the input terminals of the n data latches 43a, and output terminals of the n data latches 43a. N output switches SW2 are provided. The data latch circuit 43 includes an output switch SW2 in the first column and a transfer switch SWtrs connected to the control unit 50.

The input switch SW1 is driven based on a control signal from the control unit 50, and the input end of the p-th column data latch 43a is connected to the p-th column register in the data register circuit 42 and the p-th column detection ADC 44b. , Connected to any one of the output ends of the data latches 43a in the (p + 1) th column.

When the input terminal of the data latch 43a and the data register circuit 42 are connected, the data latch 43a holds the display data Din stored in the data register circuit 42 at a timing synchronized with the latch pulse signal LP.

When the input terminal of the data latch 43a and the detection ADC 44b are connected, the data latch 43a holds the data output from the detection ADC 44b as detection data Dout at a timing synchronized with the latch pulse signal LP.

When the input terminal of the data latch 43a in the p-th column and the output terminal of the data latch 43a in the p + 1-th column are connected, the data latch 43a in the p-th column is synchronized with the latch pulse signal LP at the timing of the p + 1th column. The detection data Dout held by the data latch 43a is held. Note that the data latch 43a in the nth column, which is the last column, is connected to the logic power supply 60, and the logic reference voltage LVSS is applied to the data latch 43a in the nth column.

The output switch SW2 is driven based on a control signal from the control unit 50, and the output terminal of the data latch 43a in the (p + 1) th column is connected to the display DAC 44a of the DAC / ADC circuit 44 and the input of the data latch 43a in the pth column. Connect to one of the ends.

When the output terminal of the data latch 43a is connected to the display DAC 44a of the DAC / ADC circuit 44, the display data Din held in the data latch 43a is input to the display DAC 44a at a timing synchronized with the latch pulse signal LP. Is done.

When the output terminal of the data latch 43a in the (p + 1) th column and the input terminal of the data latch 43a in the pth column are connected, the detection data Dout held by the data latch 43a in the (p + 1) th column is synchronized with the latch pulse signal LP. At the timing, it is held in the data latch 43a in the p-th column.

The transfer switch SWtrs is driven based on a control signal from the control unit 50 and switches between connection and disconnection between the data latch 43a in the first column and the control unit 50. When the data latch 43a in the first column and the control unit 50 are connected, the detection data Dout held in the data latch 43a in the first column is output to the control unit 50.

The DAC / ADC circuit 44 includes n display DACs 44a that are linear voltage digital-analog conversion circuits and n detection ADCs 44b that are analog-digital conversion circuits. Each of the n display DACs 44a converts the display data Din held in the data latch 43a connected to the display DAC 44a into an analog signal voltage, and outputs the analog signal voltage to the buffer circuit 45 connected to the display DAC 44a. . Each of the n detection ADCs 44b converts an analog signal voltage output from the buffer circuit 45 connected to the detection ADC 44b into, for example, 8-bit detection data Dout, and a data latch connected to the detection ADC 44b. The detection data Dout is output to 43a.

In the display DAC 44a, the input / output characteristics of the analog signal voltage output with respect to the input digital data have linearity. The analog signal voltage to be converted is set within the range from the analog power supply voltage DVSS applied from the analog power supply 70 to the analog reference voltage VEE. Also in the detection ADC 44b, the input / output characteristics of the digital data output with respect to the input analog signal voltage have linearity. In the display DAC 44a and the detection ADC 44b, the bit length of the digital data at the time of voltage conversion is set to the same bit length, for example, 8 bits.

Between the output switch SW2 and the display DAC 44a, a level shifter 46a that is a voltage adjusting circuit from the low withstand voltage circuit to the high withstand voltage circuit is provided. Further, a level shifter 46b, which is a voltage adjustment circuit from the high withstand voltage circuit to the low withstand voltage circuit, is provided between the detection ADC 44b and the input switch SW1.

The buffer circuit 45 includes a buffer 45a for each data line Ld that applies the display voltage Vd to the data line Ld, a buffer 45b for each data line Ld that takes in the voltage of the data line Ld, and a connection between the data line Ld and the buffer 45a. And a display switch SWd for each data line Ld for switching between cutting and cutting. The buffer circuit 45 also includes a detection switch SWm for each data line Ld that switches connection and disconnection between the data line Ld and the buffer 45b, and a data line Ld that switches connection and disconnection between the data line Ld and the analog power supply 70. And a detection voltage switch SWs.

The buffer 45a amplifies the analog signal voltage input from the display DAC 44a to the drive level of the pixel circuit, and generates the display voltage Vd. The display switch SWd is driven based on a control signal from the control unit 50, connects the buffer 45a and the data line Ld, and applies the display voltage Vd from the buffer 45a to the data line Ld.

The buffer 45b captures the voltage of the data line Ld, amplifies the captured voltage to the drive level of the detection ADC 44b, and outputs the amplified voltage to the detection ADC 44b. The detection switch SWm is driven based on a control signal from the control unit 50, connects the buffer 45b and the data line Ld, and takes the voltage of the data line Ld into the buffer 45b.
The detection voltage switch SWs controls application of the detection voltage Vm from the analog power supply 70 to the data line Ld.

[Configuration of Pixel Circuit PCC]
The configuration of the pixel circuit PCC will be described with reference to FIG.
As shown in FIG. 3, the pixel Px includes an organic EL element OEL and a pixel circuit PCC that causes the organic EL element OEL to emit light. The pixel circuit PCC includes three transistors Tr1 to Tr3, which are thin film transistors, and a storage capacitor Cs. The transistors Tr1 to Tr3 may be amorphous thin film transistors or polysilicon thin film transistors. In this embodiment, the transistors Tr1 to Tr3 are n-channel amorphous thin film transistors.

In the sampling transistor Tr1, the source terminal is connected to the data line Ld, the drain terminal is connected to the anode of the organic EL element OEL, and the gate terminal is connected to the scanning line Ls. The sampling transistor Tr1 becomes conductive when the high-level selection voltage VgH is applied to the scanning line Ls, and becomes non-conductive when the low-level non-selection voltage VgL is applied to the scanning line Ls.

In the switching transistor Tr2, the source terminal is connected to the gate terminal of the current control transistor Tr3, the drain terminal is connected to the power supply line La, and the gate terminal is connected to the gate terminal of the sampling transistor Tr1. The switching transistor Tr2 becomes conductive when the high-level selection voltage VgH is applied to the scanning line Ls, and becomes non-conductive when the low-level non-selection voltage VgL is applied to the scanning line Ls.

In the current control transistor Tr3, the source terminal is connected to the anode of the organic EL element OEL, the drain terminal is connected to the drain terminal of the switching transistor Tr2, and the gate terminal is connected to the source terminal of the switching transistor Tr2. In the present embodiment, the threshold voltage Vth of the drain current Id in the current control transistor Tr3 is a detection target in the threshold detection operation.

The holding capacitor Cs is connected between the gate terminal and the source terminal of the current control transistor Tr3. The holding capacitor Cs may be a parasitic capacitor formed between the gate terminal and the source terminal of the current control transistor Tr3, and other capacitor elements may be connected in parallel to the parasitic capacitor.

The reference voltage ELVSS is applied to the cathode terminal of the organic EL element OEL, and the reference voltage ELVSS is, for example, a ground potential that is higher than the analog reference voltage VEE. In the pixel Px, the organic EL element OEL includes a pixel capacitance Cd, and the data line Ld includes a parasitic capacitance Cp.

In the display operation, when the write voltage WDVSS is applied to the q-th power line La and a high-level selection signal is supplied to the q-th scanning line Ls, the q-th sampling transistor Tr1 and the q-th sampling transistor Tr1 are supplied. The switching transistor Tr2 becomes conductive. When the sampling transistor Tr1 in the q row and the switching transistor Tr2 in the q row are in a conductive state, the current control transistor Tr3 in the q row is driven in a saturation region. In this state, when the display voltage Vd is applied to each of the n data lines Ld, each gate − of the current control transistor Tr3 in the q-th row is set according to the difference between the write voltage WDVSS and the display voltage Vd. The inter-source voltage Vgs is held in the holding capacitor Cs as a write voltage.

When the non-selection voltage VgL is applied to the q-th scanning line Ls after the write voltage is held in the q-th holding capacitor Cs, the q-th sampling transistor Tr1 and the q-th switching transistor Tr2 Becomes non-conductive. If the driving voltage ELVDD is applied to the q-th power supply line La when the q-th sampling transistor Tr1 and the q-th switching transistor Tr2 are non-conductive, the q-th current control transistor Tr3 is Based on the gate-source voltage Vgs, the drain current Id is passed through the organic EL element OEL. At this time, the drain current Id in the current control transistor Tr3 in the q-th row changes in the saturation region according to the difference between the gate-source voltage Vgs and the threshold voltage Vth in the current control transistor Tr3. That is, the drain current Id corresponding to the difference between the write voltage held in the holding capacitor Cs and the threshold voltage Vth in the current control transistor Tr3 flows in the organic EL element OEL.

When the display voltage Vd based on the display data for gradation display is applied to the data line Ld, the drain current Id corresponding to the display voltage Vd flows to the organic EL element OEL, and the organic EL element OEL enters the gradation display state. Further, when the display voltage Vd based on the display data for non-gradation display is applied to the data line Ld, the flow of the drain current Id is suppressed by the organic EL element OEL, and the organic EL element OEL Key is displayed. Note that the threshold voltage Vth of the current control transistor Tr3 indicates the gate-source voltage Vgs in the current control transistor Tr3 when the drain current Id of the current control transistor Tr3 starts to flow.

[Operation of display device]
The threshold value detection operation and the display operation will be described with reference to FIGS.
First, the dependency of the display voltage Vd on the drain current Id of the current control transistor Tr3 will be described with reference to FIG. FIG. 4 is a diagram showing the relationship between the display voltage Vd applied to the pixel circuit PCC and the drain current Id in the current control transistor Tr3 in this embodiment. FIG. 4 illustrates two cases in which the threshold voltage Vth of the current control transistor Tr3 is different from each other.

A curve L1 indicated by a solid line in FIG. 4 shows the dependency of the display voltage Vd on the drain current Id of the current control transistor Tr3, and the threshold voltage Vth of the current control transistor Tr3 and the current amplification factor in the pixel circuit PCC. It shows when β is an initial value. Assuming that the initial value of the threshold voltage Vth is Vth ₀ , the drain current Id flowing through the pixel circuit PCC in the initial state is expressed by the following formula (1). In addition, _{V 0} is a write voltage WDVSS.
Id = β (V ₀ −Vd−Vth ₀ ) ² (1)

A curve L2 indicated by a broken line in FIG. 4 shows the dependency of the display voltage Vd on the drain current Id of the current control transistor Tr3, and shows when the drain current Id of the current control transistor Tr3 fluctuates from the initial state over time. . When the threshold voltage Vth is Vth ₁ (= Vth ₀ + ΔVth), the drain current Id flowing through the pixel circuit PCC in this state is expressed by the following equation (2).
Id = β (V ₀ −Vd−Vth ₁ ) ² (2)

As shown in FIG. 4 and the above formulas (1) and (2), the curve L2 shows a shape in which the curve L1 is translated by the shift amount ΔVth, and before and after the fluctuation of the threshold voltage Vth, these curves L1 And the shape of the curve L2 are almost the same. This is because the fluctuation caused by the bias load of the current amplification factor β is negligible compared to the fluctuation of the threshold voltage Vth, and the display voltage Vd is determined using the shift amount ΔVth in the current control transistor Tr3. This suggests that the drain current Id of the current control transistor Tr3 is corrected. In the present embodiment, the threshold voltage Vth of the current control transistor Tr3 is detected in the threshold voltage Vth detection operation, and the display voltage Vd applied to the pixel circuit PCC via the data line Ld is corrected.

FIG. 5 is a diagram showing the temperature dependence (high temperature and room temperature) of the relationship between the display voltage Vd applied to the pixel circuit PCC in this embodiment and the drain current Id in the current control transistor Tr3. A curve L3 indicated by a solid line in FIG. 5 indicates the dependency of the display voltage Vd on the drain current Id of the current control transistor Tr3 when the pixel circuit temperature is higher than the curve L1. In FIG. 5, it is assumed that the threshold voltage Vth (T) of the current control transistor Tr3 and the current amplification factor β (T) in the pixel circuit PCC are initial values at the temperature T. The drain current Id flowing through the pixel circuit PCC in the initial state of the threshold voltage Vth (T) is expressed by the following formula (3). V ₀ is the write voltage WDVSS.
Id = β (T) (V ₀ −Vd−Vth (T)) ² (3)

When the threshold voltage Vth when the drain current Id of the current control transistor Tr3 fluctuates from the initial state with time is Vth ₁ (T) in consideration of temperature dependence, the drain flowing through the pixel circuit PCC in this state The current Id is expressed by the following formula (4).
Id = β (T) (V ₀ −Vd−Vth ₁ (T)) ² (4)
Here again, the fact that the fluctuation due to the bias load of the current amplification factor β is negligible compared to the fluctuation of the threshold voltage Vth is utilized.

As shown in FIG. 5 and the above equation (3), the curve L3 is obtained by correcting the display voltage Vd according to the temperature change of the current amplification factor β with respect to the curve L1, so that the drain current Id of the current control transistor Tr3 is It is suggested that the correction is made according to the temperature change.
Since the temperature change of the current amplification factor β is almost linear, it can be expressed by Expression (5).
β (T) = β0 + K _β (T−T0) (5)
T0 is a reference temperature, T is a pixel circuit temperature in the display panel 10, and β0 is a current amplification factor at the reference temperature. K _β is a constant that characterizes the temperature change. Equation (5) can be further described as Equation (6) below.
β (T) = β0 · Δβ, where Δβ = 1 + K _β (T−T0) / β0 (6)
The voltage correction of the temperature correction parameter using this Δβ is V ₀ -Vd (V ₀ -Vd) / (Δβ) ^0.5 (7)
As a result, the temperature dependence of the current amplification factor β can be corrected.
In the present embodiment, a threshold of a dummy pixel (a pixel that is disposed in a frame region around the display panel 10 and has the same structure as the pixel Px and does not perform a drive current supply operation to the light emitting element (OEL)). In the value detection operation, such a threshold voltage Vth of the current control transistor Tr3 is detected, and using the multiplication correction parameter calculated from the temperature dependence data of the threshold voltage Vth, the pixel circuit PCC is connected via the data line Ld. The temperature dependence of the current amplification factor β of the pixel circuit PCC in the display panel 10 is corrected by multiplying the display voltage Vd applied to the pixel circuit PCd.

[Threshold detection operation]
With reference to FIG. 6, the transition of the driving state of each of the

driver circuits

20, 30, 40 during the threshold detection period in the threshold detection operation will be described. In the threshold detection operation, a voltage holding operation, a voltage saturation operation, a voltage measurement operation, and a voltage output operation are performed in this order. FIG. 6 is a timing chart showing a driving state of each

driver circuit

20, 30, 40 when each pixel Px in the q-th row is a detection target row for the threshold voltage Vth.

As shown in the lower side of FIG. 6, the write voltage WDVSS is continuously applied to the q-th power line La during the period in which the threshold detection operation is performed for each pixel Px in the q-th row. Further, the display switch SWd is kept off, and each pixel circuit PCC in the q-th row is disconnected from the shift register circuit 41 and the data register circuit 42 in the data driver circuit 40. Further, the output switch SW2 continues to be connected to another adjacent data latch 43a.

First, at timing t1, the input switch SW1 is connected to the detection ADC 44b, and the transfer switch SWtrs is kept off. In this state, when the selection voltage VgH is applied to the scanning line Ls in the q-th row, each switching transistor Tr2 in the q-th row and each sampling transistor Tr1 in the q-th row become conductive, and the q-th row Each current control transistor Tr3 is driven in the saturation region. Further, when the detection voltage switch SWs is turned on, the detection voltage Vm is applied from the analog power supply 70 to the data lines Ld all at once.

At this time, the detection voltage Vm is set so that a voltage larger than the threshold voltage Vth assumed between the gate and the source of the current control transistor Tr3 is applied. That is, the detection voltage Vm is set between the gate and source of the current control transistor Tr3 so that the difference between the write voltage WDVSS and the detection voltage Vm is larger than the assumed threshold voltage Vth. Note that the potential of each data line Ld to which the detection voltage Vm is applied is lower than the potential of the power supply line La to which the write voltage WDVSS is applied and lower than the cathode terminal of the organic EL element OEL.

When the detection voltage Vm is applied to each data line Ld, the current for each pixel Px corresponding to the difference between the detection voltage Vm and the write voltage WDVSS is changed between each current control transistor Tr3 in the qth row and each qth row. It flows to the analog power supply 70 via each sampling transistor Tr1. Accordingly, each holding capacitor Cs in the q-th row holds the gate-source voltage Vgs of the current control transistor Tr3 to which the holding capacitor Cs is connected, and thus the voltage holding operation ends. Note that the organic EL element OEL does not emit light because the anode potential of the organic EL element OEL is equal to or lower than the cathode side potential.

At timing t2, application of the selection voltage VgH to the scanning line Ls in the q-th row is maintained, and only the detection voltage switch SWs is switched off while the detection switch SWm is maintained off. As a result, in each data line Ld, the part closer to the data driver circuit 40 than the part connected to the sampling transistor Tr1 is switched to the high impedance state.

At this time, the gate-source voltage Vgs of each current control transistor Tr3 in the q-th row is held in each holding capacitor Cs in the q-th row. Therefore, the drain current in each current control transistor Tr3 in the q row is adjusted so that the potential of the source terminal in each current control transistor Tr3 in the q row approaches the potential of the drain terminal in each current control transistor Tr3 in the q row. Id continues to flow. Then, as the relaxation time t, which is the time elapsed from the timing t2, progresses, the charge accumulated in each storage capacitor Cs in the qth row is discharged, and the voltage between both terminals of each storage capacitor Cs is q rows. The gate-source voltage Vgs in each eye current control transistor Tr3 drops to the threshold voltage Vth at which the drain current Id does not flow. Then, a voltage corresponding to the threshold voltage Vth of each current control transistor Tr3 in the q-th row is held in each holding capacitor Cs in the q-th row, and the voltage saturation operation ends. Note that the detection voltage switch SWs for applying the detection voltage Vm to each data line Ld is kept off after the timing t2.

At timing t3, the application of the selection voltage VgH to the q-th scanning line Ls is maintained, and only the detection switch SWm is turned on. Thus, each data line Ld and each detection ADC 44b are connected, and the potential of each data line Ld in the high impedance state is taken into each detection ADC 44b.

At this time, each holding capacitor Cs in the q-th row holds a voltage corresponding to the threshold voltage Vth of each current control transistor Tr3 in the q-th row. Therefore, the gate-source voltage Vgs in each current control transistor Tr3 in the q-th row, that is, the current control transistor Tr3 in the q-th row is determined from the potential difference between the potential taken in each detection ADC 44b and the write voltage WDVSS. A voltage corresponding to the threshold voltage Vth is detected. The detected potential of each data line Ld is converted into detection data Dout which is digital data by each detection ADC 44b, and is output to each data latch 43a via the level shifter 46b. Each data latch 43a holds the output detection data Dout, thereby ending the voltage measurement operation.

At timing t4, the non-selection voltage VgL is applied to the q-th scanning line Ls, and each switching transistor Tr2 in the q-th row and each sampling transistor Tr1 in the q-th row are switched to a non-conductive state. In this state, each detection switch SWm is turned off, and the transfer switch SWtrs is turned on. Further, the input switch SW1 is connected to the adjacent data latch 43a, and the data latches 43a are connected in series.

At this time, the latch pulse signal LP is output from the control unit 50 to the data driver circuit 40, and the detection data Dout held in each data latch 43a is sequentially transmitted to the control unit 50 in synchronization with the timing of the latch pulse signal LP. Transferred. As a result, data regarding the threshold voltage Vth of each of the n current control transistors Tr3 arranged in the q-th row is sequentially transferred to the control unit 50. In FIG. 6, the number of times the latch pulse signal LP is repeated is omitted for convenience of explanation.

At timing t5, application of the non-selection voltage VgL to the q-th scanning line Ls is maintained, and the transfer switch SWtrs is turned off. The input switch SW1 connects the input terminal of the data latch 43a to the data register circuit. Connect to the register at 42. As a result, the voltage output operation ends, and the threshold value detection operation ends for the n current control transistors Tr3 arranged in the q-th row.
With reference to FIG. 7, the transition of the data line potential VLd which is the potential of the data line Ld in the period from the timing t2 to the timing t3 will be described. FIG. 7 is a diagram showing the relationship between the data line potential VLd and the relaxation time t in the present embodiment.

As shown in FIG. 7, when the relaxation time t, which is the time elapsed from the timing t2, progresses, the data line potential VLd is detected according to the discharge of the accumulated charge in the storage capacitor Cs connected to the data line Ld. The voltage Vm approaches the write voltage WDVSS. When the relaxation time t advances to the saturation time ts, the data line potential VLd is saturated at the saturation voltage VLds, and the drain current Id does not flow. At this time, the difference between the write voltage WDVSS and the saturation voltage VLds is set as the threshold voltage Vth. The saturation time ts is, for example, 3 nsec to 10 nsec, and the period from timing t2 to timing t3 is set to be equal to or longer than the saturation time ts.

FIG. 8 shows the temperature dependence of the data line potential VLd in the measurement sequence described in FIG. As shown in FIG. 8, when the temperature increases, the data line potential VLd after the relaxation time t, which is the time elapsed from the timing t2, approaches WDVSS in a shorter time. FIG. 9 is a diagram showing the temperature dependence of the measurement result of the data line potential VLd at t0 in FIG. 8 in the present embodiment. When the relaxation time t is set to t0, the temperature dependence of the data voltage VLd at this time becomes linear as shown in FIG. Since the temperature change of the current amplification factor β can be expressed linearly as expressed by the equation (5) and the threshold voltage Vth measurement value can be expressed linearly, when the reference temperature is expressed as T0, β (T) / β _{(T0) = 1 + K β} '(Vth (T) -Vth (T0)) , and the temperature dependency of the current amplification factor beta from the threshold voltage Vth measurement results can be calculated. Here, K _β ′ is a constant. That is, the pixel circuit temperature in the display panel 10 can be measured by measuring the threshold voltage Vth, and the temperature dependence of the current amplification factor β of the pixel circuit PCC can be corrected based on the data.

FIG. 10 shows the flow of the threshold voltage Vth correction for each pixel Px and the temperature fluctuation correction for the current amplification factor β of the pixel circuit PCC. A multiplication correction value of the current amplification factor β is calculated from the measured value of the threshold voltage Vth measured using the dummy pixel circuit. The correction value is multiplied by the image data to correct the temperature dependence of the current amplification factor β. Thereafter, the threshold voltage Vth measured in each pixel Px is added. Since this threshold voltage Vth has already been measured including temperature dependence, threshold shift and correction of temperature change of the current amplification factor β are performed.

[Display operation]
With reference to FIG. 11, the transition of the driving state of each of the

driver circuits

20, 30, 40 in the gradation display operation will be described. FIG. 11 is a timing chart showing the transition of the level of each control signal along with the state of each switch during the display operation period in the present embodiment. In the gradation display operation, the writing operation and the light emitting operation are performed in this order. Note that the transition of the driving state of each of the

driver circuits

20, 30, and 40 in the non-gradation display operation is the same as that in the gradation display operation in the period from the start to the threshold detection operation.

As shown in the lower side of FIG. 11, each detection switch SWm, each detection voltage switch SWs, and the transfer switch SWtrs are kept off during the period in which the gradation display operation is performed. Each output switch SW2 is maintained in a state of connecting the data latch 43a and the display DAC 44a, and each of the input switches SW1 is maintained in a state of connecting the data latch 43a and the data register circuit 42. The

First, at timing td1, each display switch SWd is turned on, so that the shift register circuit 41, the data register circuit 42, the data latch 43a, the display DAC 44a, the buffer 45a, and the data line Ld are connected in series. The Next, when the start pulse signal SP1 is input to the data driver circuit 40, the shift signal is input from the shift register circuit 41 to the data register circuit 42, whereby the display data Din in the first row is transferred from the control unit 50 to the data register circuit 42. The data is taken into the register circuit 42.

At timing td2, the selection voltage VgH is applied to the scanning line Ls of the first row, and the writing voltage WDVSS is applied to the power supply line La of the first row, so that each sampling transistor Tr1 in the first row and the first row Each switching transistor Tr2 becomes conductive. In addition, each current control transistor Tr3 in the first row can be driven in the saturation region.

At this time, the latch pulse signal LP is output to the data driver circuit 40, whereby the display data Din of the first row is simultaneously held in the data latches 43a. The display data Din in the first row held in the n data latches 43a is converted into an analog signal voltage by the n display DACs 44a via the n level shifters 46a, and used as the display voltage Vd for each column. Output to each data line Ld. The gate-source voltage Vgs of each current control transistor Tr3 in the first row becomes a value corresponding to the difference between the write voltage WDVSS and the display voltage Vd, and is held in the storage capacitor Cs as the write voltage. Thus, the writing operation for each pixel Px in the first row is completed. It should be noted that the display voltage Vd applied to each data line Ld is such that the difference between the detection data Dout associated with each pixel Px in the first row and the reference threshold voltage Vth is an adjusted gradation. This is a voltage value obtained by adding or subtracting data.

At this time, the start pulse signal SP1 is output to the data driver circuit 40 again, whereby the shift signal is output from the shift register circuit 41 to the data register circuit 42. As a result, the display data Din on the second line is taken into the data register circuit 42 from the control unit 50.

At timing td3, the non-selection voltage VgL is applied to the scanning line Ls of the first row, and the driving voltage ELVDD is applied to the power supply line La of the first row, so that each sampling transistor Tr1 in the first row and the first row Each of the switching transistors Tr2 becomes non-conductive. Each current control transistor Tr3 in the first row has a difference between the write voltage held in each holding capacitor Cs in the first row and the threshold voltage Vth in the current control transistor Tr3 to which it is connected. The corresponding drain current Id is supplied to the corresponding organic EL element OEL. At this time, in the display voltage Vd applied to each data line Ld, the fluctuation amount of the threshold voltage Vth is corrected. Therefore, the drain current Id supplied to the organic EL element OEL is also the threshold voltage. The variation of Vth is corrected. As a result, a light emission operation is performed on each pixel Px in the first row.

At this time, the selection voltage VgH is applied to the scanning line Ls of the second row, and the write voltage WDVSS is applied to the power supply line La of the second row. The switching transistors Tr2 in the eye are brought into conduction. Each current control transistor Tr3 in the second row is in a state where it can be driven in the saturation region. Further, the latch pulse signal LP is output again to the data driver circuit 40, whereby the display data Din of the second row is held in each data latch 43a. The display data Din in the second row held in each data latch 43a is converted into an analog signal voltage by each display DAC 44a via each level shifter 46a, and output to each data line Ld as a display voltage Vd for each column. Is done. The gate-source voltage Vgs of each current control transistor Tr3 in the second row becomes a value corresponding to the difference between the write voltage WDVSS and the display voltage Vd, and is held as the write voltage in each storage capacitor Cs in the second row. Is done. Thus, the writing operation for each pixel Px in the second row is completed.

The writing operation and the light emitting operation are performed in this order for each row, and such gradation display operation is performed in order from the first row to the nth row in the display clock cycle. As a result, an image is displayed as one frame. When non-gradation display for displaying a black image is performed as the display operation, the voltage applied by the power supply driver 30 is set to the WDVSS state.

[Detection operation timing]
With reference to FIG. 12 to FIG. 14, the timing of the threshold detection operation performed in the non-gradation display operation will be described. In the following, a case where dummy pixels are arranged on the data line Ld, the pixels Px are arranged in 540 rows × 960 columns, and the frame rate is 60 fps will be described as an example. FIG. 12 shows the timing of the threshold detection operation in the non-gradation display operation in the first frame, and FIG. 13 shows the timing of the threshold detection operation in the non-gradation display operation in the second frame. FIG. 14 shows the timing of the threshold detection operation in the non-gradation display operation in the 540th frame.

As shown in FIG. 12, first, at the timing Tf1a, the writing operation in the gradation display operation is started at each pixel Px in the first row. When the writing operation in the gradation display operation is completed at each pixel Px in the first row, the light emission operation in the gradation display operation is started at each pixel Px in the first row, and the writing operation in the gradation display operation is performed. It starts at each pixel Px in the second row. Thus, the writing operation in the gradation display operation is started in the display clock cycle in order from the first row to the 540th row, and the light emission operation in the gradation display operation is started in order from the row in which the writing operation in the gradation display operation is completed. Is done.

At timing Tf1b, the writing operation in the gradation display operation is completed up to the 540th row, which is the last row, and the writing operation in the non-gradation display operation is started at each pixel Px in the first row. When the writing operation in the non-grayscale display operation ends at each pixel Px in the first row, the non-light emission operation in the non-grayscale display operation starts at each pixel Px in the first row and the non-grayscale display operation Is started at each pixel Px in the second row. Thus, the writing operation in the non-grayscale display operation is started in the display clock cycle in order from the first row to the 540th row, and the non-grayscale display operation is sequentially performed from the row in which the writing operation in the non-grayscale display operation is completed. The light emission operation is started.

At the timing Tf1c, the start of the non-light emission operation in the non-gradation display operation is completed until the last row 540, and the candidates to which the selection voltage VgH is applied are sequentially detected in the detection clock cycle from the first row to the 540th row. Scanned. In this case, first, the first row is set as a candidate to which the selection voltage VgH is applied, that is, the detection target row from which the threshold voltage Vth is detected, and the threshold detection operation for each pixel Px in the first row. Is performed during the threshold detection period.

Thus, the detection data Dout regarding each current control transistor Tr3 in the first row is stored in the data storage unit 52 of the control unit 50. When the threshold detection operation for each pixel Px in the first row is completed, the shift of the selection target bit in the detection clock cycle is repeated in order from the second row to the 540th row, while all the scanning lines are A non-selection voltage VgL is applied to Ls. As a result, all the pixels Px stand by in a non-gradation display state.

At timing Tf2a, the shift of the selection target bit in the detection clock cycle proceeds to the last row 540 by the input of the detection shift clock signal Clkr, and the gradation is again applied to each pixel Px in the first row. The writing operation in the display operation is started.

As shown in FIG. 13, at the timing Tf2a, the writing operation in the gradation display operation is started again from the first row to the 540th row, and the gradation display is performed in order from the row where the writing operation in the gradation display operation is completed. The light emission operation in the operation is started.

At the timing Tf2b, the writing operation in the gradation display operation is advanced in the display clock cycle up to the 540th row, which is the last row, and the light emission operation in the gradation display operation is sequentially performed from the row where the writing operation in the gradation display operation is completed. Be started. Next, the writing operation in the non-grayscale display operation proceeds again in the display clock cycle in order from the first row to the 540th row, and in the non-grayscale display operation in order from the row where the writing operation in the non-grayscale display operation is completed. Non-light emitting operation is started.

At timing Tf2c, the start of the non-light emission operation in the non-grayscale display operation is completed up to the 540th row, which is the last row, and the candidates to which the selection voltage VgH is applied are sequentially detected from the first row to the 540th row. Is scanned. At this time, the second row is set as the detection target row from which the threshold voltage Vth is detected. First, the selection target bit is shifted to the second row in the detection clock cycle. When the candidate to which the selection voltage VgH is applied is the first row, the non-selection voltage VgL is applied to the scanning line Ls. When the candidate to which the selection voltage VgH is applied is the second row, the threshold detection operation for each pixel Px in the second row is performed during the threshold detection period.

Thus, the detection data Dout regarding each current control transistor Tr3 in the second row is stored in the data storage unit 52 of the control unit 50. When the threshold detection operation for each pixel Px in the second row is completed, the shift of the selection target bit in the detection clock cycle is repeated in order from the third row to the 540th row, while all the scanning lines are A non-selection voltage VgL is applied to Ls. As a result, all the pixels Px stand by in a non-gradation display state.

At timing Tf3a, the shift of the selection target bit in the detection clock cycle proceeds to the last row 540 by the input of the detection shift clock signal Clkr, and the gradation is again applied to each pixel Px in the first row. The writing operation in the display operation is started.

As shown in FIG. 14, at the timing Tf540a, the writing operation in the gradation display operation is started again from the first row to the 540th row, and the gradation display is performed in order from the row where the writing operation in the gradation display operation is completed. The light emission operation in the operation is started.

At the timing Tf540b, the writing operation in the gradation display operation is advanced in the display clock cycle up to the 540th row, which is the final row, and the light emission operation in the gradation display operation is sequentially performed from the row where the writing operation in the gradation display operation is completed. Be started. Next, the writing operation in the non-grayscale display operation proceeds again in the display clock cycle in order from the first row to the 540th row, and in the non-grayscale display operation in order from the row where the writing operation in the non-grayscale display operation is completed. Non-light emitting operation is started.

At timing Tf540c, the start of the non-light emission operation in the non-grayscale display operation ends to the 540th row, which is the last row, and the candidates to which the selection voltage VgH is applied are sequentially detected from the 1st row to the 540th row. Is scanned. At this time, when the detection target row from which the threshold voltage Vth is detected is set as the detection target row, and the candidates to which the selection voltage VgH is applied are from the first row to the 539th row, with respect to the scanning line Ls. The non-selection voltage VgL is applied. When the candidate to which the selection voltage VgH is applied is the 540th row, the threshold detection operation for each pixel Px in the 540th row is performed during the threshold detection period. As a result, the detection data Dout regarding each current control transistor Tr3 in the 540th row is stored in the data storage unit 52 of the control unit 50.

At timing Tf540e, the threshold detection operation for each pixel Px in the 540th row is completed, and the writing operation in the gradation display operation is started again for each pixel Px in the first row.

As described above, in the period in which one frame is displayed, the threshold detection operation is performed on the pixels Px in a specific row after the non-light emission operation in the non-gradation display operation is started up to the 540th row. . The detection target row of the threshold voltage Vth is shifted by one row in order along the scanning direction from the pixel Px in the first row for each frame. That is, when the threshold detection operation is performed on the pixel Px in the q-th row (1 ≦ q ≦ 539) in the k-th frame (k is an integer equal to or greater than 1), the pixel Px in the q + 1-th row is performed in the k + 1-th frame. A threshold value detection operation is performed for. When the detection target line reaches the last line, the detection target line returns to the first line.

At this time, the detection data Dout obtained when the detection target row is the q-th row is stored in a storage area associated with each pixel Px in the q-row by the data storage unit 52 in the control unit 50. Has been updated. Therefore, in the (k + 1) th frame, when the control unit 50 generates the display data Din in the display operation, the latest detection data Dout is used as the detection data Dout in the q-th row. Then, the control unit 50 uses the previous detection data Dout used in the kth frame for the detection data Dout other than the q-th row. Thus, the detection data Dout of each row is updated every time the frame display is repeated 540 times.
When dummy pixels are provided other than the data line Ld for actual display, temperature change measurement data can also be acquired by the sequence shown in FIGS. At this time, black display data is applied to the dummy data (data input to the dummy pixel circuit) so that no bias load is generated in the pixel circuit PCC. Here, the dummy pixel circuit means a TFT pixel circuit portion that does not include the organic EL element OEL among the dummy pixels.

15 to 17 show an embodiment in which a scanning line for dummy pixels (hereinafter referred to as a dummy row) is provided separately from the display pixel Px for measuring the threshold voltage Vth. 15 shows a case where a dummy row is provided before the first row of the scanning line Ls for the display pixel Px, FIG. 16 shows a case where a dummy row is provided after the last row of the scanning line Ls, and FIG. The timing of the threshold voltage detection operation when dummy rows are provided both before the main and after the last row is shown. Since the threshold voltage Vth is measured as a value representative of the display panel temperature, the average value of the measured values of each dummy pixel is used as a correction data calculation parameter.

Referring to FIGS. 18 and 19, the transition of each control signal during a period in which one frame is displayed will be described in detail. 18 and 19 are timing charts showing the transition of the level of various control signals for each scanning line Ls and power supply line La during the period in which one frame is displayed in the present embodiment. Hereinafter, a case where the detection target row in the k-th frame is each pixel Px in the q-th row will be described.

In the selection driver circuit 20, first, a shift signal is generated at a display clock cycle in accordance with the input of the start pulse signal SP2, and the selection voltage VgH is sequentially applied to each scanning line Ls at a timing based on the shift signal. At this time, the selection voltage VgH is applied in order from the first scanning line Ls to the 540th scanning line Ls in the display clock cycle. In addition, the write voltage WDVSS is applied to each power supply line La in order from the power supply line La of the first row to the power supply line La of the 540th row in the display clock cycle. Then, when the selection voltage VgH is applied to the q-th scanning line Ls and the write voltage WDVSS is applied to the q-th power line La, each pixel circuit PCC in the q-th row has a gradation display. A display voltage Vd based on the display data Din is applied via each data line Ld, and a voltage Vd based on black display data having no bias load is applied to the dummy pixel circuit. Further, the non-selection voltage VgL is applied to the scanning line Ls in order from the row to which the selection voltage VgH is applied, and the driving voltage ELVDD is applied to the power supply line La in order from the row to which the write voltage WDVSS is applied. Then, when the non-selection voltage VgL is applied to the q-th scanning line Ls and the driving voltage ELVDD is applied to the q-th power supply line La, each pixel circuit PCC in the q-th row is used for gradation display. The drain current Id based on the display data Din is supplied to the organic EL element OEL.

When the writing operation is completed up to the 540th row, which is the last row, the selection voltage is again displayed in the display clock cycle in order from the first scanning line Ls to the 540th scanning line Ls again in response to the input of the start pulse signal SP2. VgH is applied to each scanning line Ls. Further, the write voltage WDVSS is also applied to each power supply line La in order from the first power supply line La to the 540th power supply line La in the display clock cycle. Then, when the selection voltage VgH is applied to the q-th scanning line Ls and the write voltage WDVSS is applied to the q-th power line La, each pixel circuit PCC in the q-th row displays a non-gradation display. A display voltage Vd based on the display data Din is applied via each data line Ld. Further, the non-selection voltage VgL is applied to the scanning line Ls in order from the row to which the selection voltage VgH is applied, and the driving voltage ELVDD is applied to the power supply line La in order from the row to which the write voltage WDVSS is applied. When the non-selection voltage VgL is applied to the q-th scanning line Ls and the driving voltage ELVDD is applied to the q-th power line La, the non-grayscale display is performed in each pixel circuit PCC in the q-th row. The supply of the drain current Id to the organic EL element OEL is suppressed based on the display data Din for use.

When the start of the non-gradation display operation is advanced to the 540th row which is the last row, the write voltage WDVSS is applied to each power supply line La. Further, the input of the start pulse signal SP2 is the number of times of switching, and the shift clock signal used for scanning the scanning line Ls is switched from the display clock cycle to the detection clock cycle. Then, in the shift register circuit 21 of the selection driver circuit 20, a shift signal is generated at the detection clock cycle, and the selection target bits in the shift signal are shifted to the q−1th row. During this period, the mask pulse signal MP is maintained at a low level, and the shift register circuit 21 of the selection driver circuit 20 continues to output a shift signal that does not include the selection target bit regardless of the generated shift signal.

At the timing when the selection target bit is shifted to the q-th row, the mask pulse signal MP is switched to the high level, and the selection voltage VgH is applied to the scanning line Ls of the q-th row. Then, detection of the threshold voltage Vth is started for each pixel Px in the q-th row. When the detection data Dout for each pixel Px in the q-th row is output from the data driver circuit 40 and the threshold detection period elapses after the mask pulse signal MP is switched to the high level, the mask pulse signal MP is again set to the low level. Can be switched to. Then, in the shift register circuit 21 of the selection driver circuit 20, a shift signal is generated at the detection clock cycle, and the selection target bits in the shift signal are shifted to the 540th row. During this period, since the mask pulse signal MP is maintained at a low level, the shift register circuit 21 of the selection driver circuit 20 continues to output a shift signal that does not include the selection target bit regardless of the generated shift signal. .

When the selection target bits in the shift signal are shifted to the 540th row, the mask pulse signal MP is switched to the high level again in response to the input of the start pulse signal SP2. Then, the selection voltage VgH is applied to each scanning line Ls in the display clock cycle in order from the first scanning line Ls to the 540th scanning line Ls. The writing operation in the tone display operation is started.

FIG. 19 shows a control sequence when a dummy row is arranged after the last row. In this case, since it is not necessary to perform a dummy row other than the threshold detection operation, the VgH setting of the scanning line Ls may be performed only when the threshold detection operation is performed, and the power supply line La may also remain at WDVSS. According to this embodiment, the effects listed below can be obtained.

(1) Through the threshold detection operation, the threshold voltage Vth of the current control transistor Tr3 and its temperature dependence in the pixel circuit PCC and the dummy pixel circuit are measured. Then, the image data is corrected using the detection data Dout based on the measured threshold voltage Vth, and display data Din is generated. A display voltage Vd based on the display data Din is applied to the pixel circuit PCC. Therefore, even if the threshold voltage Vth of the current control transistor Tr3 fluctuates, the image data is corrected in accordance with the threshold voltage Vth after the fluctuation, so that it is possible to suppress deterioration in the displayed image quality. .

(2) Since the threshold value detection operation is performed during a period in which one frame is displayed, compared to the case where the threshold value detection operation is performed only when the display device is started up or returned from the hibernation state, The update period of the detection data Dout is shortened. That is, the time difference between when the detection data Dout is acquired and when the display data Din, which is corrected data, is output is shortened. Therefore, even when an image with a high contrast is displayed, even when the variation of the threshold voltage Vth of the current control transistor Tr3 changes in a short period (for example, an environmental temperature change in a mobile display), it is displayed. Degradation of image quality is suppressed.

(3) In one threshold detection operation, detection of data related to the threshold voltage Vth is performed only for n pixels Px connected to one scanning line Ls. Therefore, the time required for one threshold detection operation is compared with the case where the detection of the data related to the threshold voltage Vth is performed once for all the pixels Px or the pixels Px in a plurality of rows. Becomes shorter. Therefore, even if the threshold detection operation is incorporated in a period during which one frame is displayed, it is possible to suppress the threshold detection operation from affecting the image display performance as the display device.

(4) In particular, the threshold detection operation is performed during the period in which the non-gradation display operation inserted to make the moving image display clear is performed, and thus the threshold detection operation has an effect on the image display performance. The impact is effectively suppressed.

(5) In the threshold value detection operation, detection target row candidates are sequentially switched from the first row to the last row. That is, in the threshold detection operation, the selection target candidates are switched similarly to the gradation display operation and the non-gradation display operation. Therefore, the selection driver circuit 20 also functions as a configuration in which the detection target row is changed every time one frame is displayed.

(6) Further, in the threshold value detection operation, the detection cycle of the detection target row candidate is a detection clock cycle shorter than the display clock cycle. Therefore, the time required for the threshold detection operation is shortened as compared with the case where the detection target line candidate switching period is the display clock period.

(7) The detection target row of the threshold voltage Vth is shifted one row at a time in the scanning direction from the pixel Px of the first row every time one frame is displayed. Therefore, the correction of the display data Din based on the threshold voltage Vth is finer in the scanning direction than in the configuration in which the detection target row of the threshold voltage Vth is intermittently set along the scanning direction. .

(Modification)
The above embodiment can be implemented with the following modifications.
The detection target line may be shifted by two or more lines along the scanning direction every time one frame is displayed. In this case, when the shift amount of the detection target row every time one frame is displayed is set as Sf, the data storage unit 52 includes a storage area of m / Sf rows × n columns along the column direction. Each of the Sf pixels Px arranged in parallel is associated with one storage area.

Sf pixels Px arranged in the column direction may be set as one group, and only the first row of each group may be set as a detection target row. That is, the configuration may be such that the detection target rows are repeatedly shifted for each frame in the order of the first row, the eleventh row, the twenty-first row,..., The 511th row, the 521st row, and the 531st row. Further, not only the first row of each group but also a specific row in each group is set as a detection target row, and the detection data Dout of each row in the group is always represented by the detection data Dout of the specific row. There may be.

The detection data Dout obtained in the period in which the current frame is displayed may be handled as the detection data Dout for all rows in the period in which the next frame is displayed. In this case, the data storage unit 52 includes a storage area of 1 row × n columns, and each of the m pixels Px arranged in the column direction is associated with one storage area. For example, when the operating temperature of the current control transistor Tr3 dominates the fluctuation amount of the threshold voltage Vth, the fluctuation amount of the threshold voltage Vth becomes close in all the current control transistors Tr3. In this regard, according to the above-described configuration, the detection data Dout for one row is also used as the detection data Dout for the other row, so the effect according to the above (7) becomes remarkable.

· The detection target line may be set to the same line for each frame. The detection target line may be set irregularly for each frame. When the detection target row is set irregularly for each frame, for example, the control unit 50 uses a random function that generates a random number for each frame between 1 and m. The timing at which the shift standby portion is output by the detection shift clock signal Clkr and the timing at which the mask release portion is output by the mask pulse signal MP are synchronized, and only the time corresponding to the generated random number. It is sufficient if these are delayed from the start pulse signal SP2.

· Two or more detection target rows may be set for each frame. At this time, the detection shift clock signal Clkr outputs two shift standby portions at different timings, and the mask pulse signal MP outputs two mask release portions at different timings. The timing at which each of the two shift standby portions is output is synchronized with the timing at which each of the two mask release portions is output.

-For example, when the display device is activated, when the display device is paused and then returned, the pixel circuits PCC in all rows or some rows are not included in a period other than one frame is displayed. On the other hand, a threshold detection operation may be performed.

The detection voltage Vm applied in one threshold detection operation may have a different configuration for each data line Ld. At this time, in the threshold detection operation, each of the plurality of data lines Ld may be connected to the analog power supply 70 through different wirings. Alternatively, the detection voltage Vm may be supplied as digital data from the data driver circuit 40 to the data line Ld.

The data line Ld to which the detection voltage Vm is applied in one threshold detection operation may be a part of all the data lines Ld. At this time, in one threshold value detection operation, only a part of the data lines Ld to which the detection voltage Vm is applied is connected to the analog power supply 70 via the detection voltage switch SWs.

In the above-described embodiment, the threshold voltage Vth is detected as a characteristic of the current control transistor Tr3, and the display voltage Vd is corrected based on the detected threshold voltage Vth. Not limited to this, the current amplification factor β may be detected as a characteristic of the current control transistor Tr3, and the display voltage Vd may be corrected based on the detected current amplification factor β. Further, both the threshold voltage Vth and the current amplification factor β may be detected as the characteristics of the current control transistor Tr3. In short, the detection target in the threshold detection operation may be any parameter that affects the drive current supplied to the organic EL element OEL among the element characteristics of the current control transistor Tr3.
In the correction of the display voltage Vd, in addition to the element characteristics of the current control transistor Tr3, the light emission characteristics of the organic EL element OEL such as light emission luminance may be used.

The configuration of the pixel circuit PCC is not limited to the above configuration. As long as the driving current is supplied to the organic EL element OEL through the current control transistor Tr3, the type of elements provided in the pixel circuit PCC and the circuit configuration are arbitrary. The light emitting element is not limited to an organic EL element, and may be an inorganic EL element, an LED, or the like, and may be any element that emits light by supplying a driving current through the current control transistor Tr3.

[High temperature side brightness control method]
In order to prevent the transistor and the light emitting element from deteriorating due to heat generation of the display panel 10 due to the drive current, it is possible to control the current according to the temperature in the present invention. FIG. 20 shows two types (a) and (b) of sequences for decreasing the drive current when the temperature exceeds the threshold temperature (Tc = 50 ° C.). Each can be dealt with by changing the voltage correction V ₀ -Vd of the temperature correction parameter as follows using Δβ of the equation (6).
(V ₀ -Vd) / (Δβ) ^0.5 , T <Tc
(V ₀ −Vd) (1−α (T−Tc)) / (Δβ) ^0.5 , T ≧ Tc (8)
(V ₀ -Vd) / (Δβ) ^0.5 , T <Tc
α (V ₀ −Vd) / (Δβ) ^0.5 , T ≧ Tc (9)
α is a constant smaller than 1 and is one of the brightness control parameters. Thus, if the fact that the threshold voltage Vth measurement result is linear with respect to temperature is used, it can be used as display panel temperature control.

According to the embodiment and the modification disclosed above, in each display pixel circuit PCC, the transistor characteristics are detected by the threshold detection operation, and the gradation display voltage supplied to the pixel circuit PCC is the threshold detection. Correction is made based on the result. Therefore, when the characteristics of the transistor fluctuate, the gradation display voltage is corrected in accordance with the fluctuation of the transistor characteristics. As a result, it is possible to prevent the image quality from being changed due to the change in the transistor characteristics, and hence the image quality from being deteriorated due to the change in the transistor characteristics, and the temperature characteristics of the transistor in the pixel circuit PCC for temperature control. Since measurement is performed, a data voltage correction operation as temperature control can be performed from the measured value.

In addition, since gradation display operation, non-gradation display operation, and threshold detection operation are repeated in this order, the timing of gradation display operation and threshold detection, such as in the case of a display incorporated in a moving body having a large environmental temperature change The time difference from the operation timing is shortened. Therefore, effective temperature control is possible when the temperature characteristics of the transistor change greatly in a short period.

According to the above configuration, the arrangement of the scanning lines Ls for the dummy pixels may be added as the scanning lines for measurement above and below the scanning lines Ls for the display pixels Px, for example, Except that no display data is applied to the data line Ld, the same driving as the display pixel Px may be performed. Furthermore, the EL element OEL may or may not be formed on the dummy pixel.

In addition, when the variation in the characteristics of the transistor depends on the manufacturing process of the transistor and the operating temperature of the transistor, the degree of the variation may be close between a plurality of different pixel circuits PCC. For this reason, when the gradation display voltage of one pixel circuit PCC is corrected, the detection result in another pixel circuit PCC may be used. In this respect, with the above-described configuration, since the range of the detection target is widened, when the gradation display voltage is corrected for one pixel circuit PCC, the threshold value detection used for the correction is detected. More candidate results. As a result, it becomes possible to share the detection result between the pixel circuits PCC in which the variation in the characteristics of the transistors is assumed to be close to each other, so that it is possible to improve the accuracy of the gradation display voltage correction. Since the change in the temperature characteristic of the transistor depends on the environmental temperature, a value obtained by averaging the measurement results of all the dummy pixels can be detected as a representative value, not the measurement result for one pixel circuit PCC. In addition, a plurality of measurement data for each area can be used as detection values.
In another aspect of the display device according to the present disclosure, the control unit 50 sets the number of selection targets in one threshold detection operation to one.

In another aspect of the display device of the present disclosure, the selection driver circuit 20 sequentially switches the selection target candidates among the plurality of scanning lines Ls. Then, the control unit 50 shortens the switching cycle in the threshold detection operation than the switching cycle in the gradation display operation and the switching cycle in the non-gradation display operation.

According to the above configuration, when one scanning line Ls is selected as a selection target, the selection target candidates are sequentially switched among the plurality of scanning lines Ls. At this time, since the switching cycle in the threshold detection operation is shorter than the switching cycle in other operations, the time required until a specific selection target is selected is compared with other operations. Become shorter. As a result, since the time required for one threshold detection operation is shortened, it is further suppressed that the non-display state becomes longer than necessary due to the time required for the threshold detection operation.

According to the present invention, it is possible to suppress a change in image quality due to a change in element characteristics in a pixel circuit that supplies a drive current to a light emitting element, and the present invention can be used for a display device, a display method, and the like.

β current amplification factor t relaxation time Ce pixel capacitance Cp parasitic capacitance Cs holding capacitance Id drain current L1, L2, L3 curve La power supply line Ld data line LP latch pulse signal Ls scanning line MP mask pulse signal Px pixel t1, t2, t3 t4, t5, td1, td2, td3, td4 timing ts saturation time Vd display voltage Vm detection voltage Din display data OEL organic EL element PCC pixel circuit SP1, SP2 start pulse signal SW1 input switch SW2 output switch SWd display switch SWm Detection switch SWs Detection voltage switch Tr1 Sampling transistor Tr2 Switching transistor Tr3 Current control transistor VEE Analog reference voltage VgH Selection voltage VgL Non-selection voltage gs gate-source voltage VLd data line potential Vth threshold voltage ΔVth shift amount Clkd data shift clock signal Clks display shift clock signal Clkr detection shift clock signal Dout detection data DVSS analog power supply voltage LVDD logic power supply voltage LVSS logic reference voltage VLds Saturation voltage ELVDD Drive voltage ELVSS Reference voltage SWtrs Transfer switch WDVSS Write voltage 10 Display panel 20 Select driver circuit 21 Shift register circuit 22 Level shifter circuit 23 Buffer circuit 30 Power supply driver 40 Data driver circuit 41 Shift register circuit 42 Data register circuit 43 Data latch Circuit 43a Data latch 44 DAC / ADC circuit 45 Buffer circuit 6 level shifter 50 control unit 51 adjusting unit 52 data storage unit 53 correction unit 54 clock generating unit 55 pulse generator 60 logic power 70 Analog Power

Claims

A plurality of pixel circuits including a transistor for supplying a driving current to the light emitting element;
A plurality of dummy pixel circuits having the same configuration as the pixel circuit and performing no drive current supply operation to the light emitting element;
A plurality of scanning lines that are connected to each of the plurality of pixel circuits and the plurality of dummy pixels;
A plurality of data lines that are connected to each of the plurality of pixel circuits and the plurality of dummy pixels;
A selection driver for selecting any one of the plurality of scanning lines as a selection target;
A control unit for controlling the driving of the selection driver,
The controller is
For the pixel circuit,
A gray scale display operation for sequentially selecting each scanning line and applying a gray scale display voltage to the pixel circuit connected to each selection target through a data line to bring the light emitting element into a gray scale display state;
A non-grayscale display operation in which each scanning line is sequentially selected and a non-grayscale display voltage is applied to the pixel circuit connected to each selection target through a data line so that the light emitting element is in a non-grayscale display state;
A detection operation of selecting a part of the plurality of scanning lines in the non-grayscale display state and detecting the characteristics of the transistor through the data line for the pixel circuit connected to the selection target is repeated in this order. ,
Using the detection result obtained by the detection operation to correct the gradation display voltage,
For the dummy pixel circuit,
Each scanning line is sequentially selected, and a non-gradation display voltage is applied to the dummy pixel circuit connected to each selection target through a data line,
A display device that corrects temperature characteristics of the pixel circuit by performing a detection operation for detecting characteristics of the transistor through a data line for the dummy pixel circuit connected to the selection target.
Among the plurality of scanning lines, the scanning line connected to the pixel circuit and the scanning line connected to the dummy pixel circuit are different,
The controller is
The display device according to claim 1, wherein the selection target in the detection operation is changed for each detection operation.
Among the plurality of data lines, the data line connected to the pixel circuit and the data line connected to the dummy pixel circuit are different,
The controller is
The display device according to claim 1, wherein the selection target in the detection operation is changed for each detection operation.
The controller is
The display device according to claim 1, wherein the selection target in the detection operation is changed for each detection operation.
The controller is
The display device according to claim 1, wherein the number of selection targets in one detection operation is set to one.
The controller is
The display device according to claim 3, wherein the selection target in the detection operation is displaced by one for each detection operation.
The controller is
The display device according to claim 3, wherein a plurality of the selection targets in the detection operation are displaced at equal intervals for each detection operation.
The controller is
Dividing the plurality of scanning lines into a plurality of scanning line groups composed of a plurality of scanning lines adjacent to each other;
A storage unit that stores data relating to the detection result in association with the scanning line group including the selection target;
Displacing the selection target in the detection operation by the scanning line group for each detection operation;
The display device according to claim 5, wherein the gradation display voltage to the pixel circuit connected to the scanning line group is corrected using the data associated with the scanning line group.
The selected driver is
Sequentially switching the candidates for selection among the plurality of scanning lines;
The controller is
7. The display according to claim 1, wherein the switching cycle in the detection operation is shorter than the switching cycle in the gradation display operation and the switching cycle in the non-gradation display operation. apparatus.
Sequentially selecting one of a plurality of scanning lines connected to a pixel circuit including a transistor that supplies a driving current to the light emitting element as a selection target;
A gradation display operation in which a gradation display voltage is applied to the pixel circuit connected to a selection target through a data line to place the light emitting element in a gradation display state;
A non-grayscale display operation in which a non-grayscale display voltage is applied to the pixel circuit connected to a selection target through a data line to bring the light-emitting element into a non-grayscale display state;
A detection operation of selecting a part of the plurality of scanning lines in the non-grayscale display state and detecting the characteristics of the transistor through the data line for the pixel circuit connected to the selection target is repeated in this order. ,
A display method in which the gradation display voltage is corrected using a detection result obtained by the detection operation.
Any of one or more scanning lines in which a pixel circuit including a transistor that supplies a driving current to the light emitting element and a dummy pixel circuit that has the same configuration as the pixel circuit and that does not perform the driving current supply operation to the light emitting element are connected. Select one or the other as a selection target,
A gradation display operation in which a gradation display voltage is applied to the pixel circuit connected to a selection target through a data line to place the light emitting element in a gradation display state;
A non-grayscale display operation in which a non-grayscale display voltage is applied to the pixel circuit or the dummy pixel circuit connected to each selection target through a data line to bring the light-emitting element into a non-grayscale display state;
A detection operation for selecting a part or all of the scanning lines in the non-grayscale display state and detecting the characteristics of the transistors through the data lines for the dummy pixel circuit connected to the selection target; Repeat to
A display method for controlling a change in temperature characteristics of a pixel circuit by correcting the gradation display voltage using a detection result obtained by the detection operation.