WO2019187101A1 - Display device and manufacturing method therefor - Google Patents

Display device and manufacturing method therefor Download PDF

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Publication number
WO2019187101A1
WO2019187101A1 PCT/JP2018/013868 JP2018013868W WO2019187101A1 WO 2019187101 A1 WO2019187101 A1 WO 2019187101A1 JP 2018013868 W JP2018013868 W JP 2018013868W WO 2019187101 A1 WO2019187101 A1 WO 2019187101A1
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WO
WIPO (PCT)
Prior art keywords
light emitting
emitting element
display device
line
control
Prior art date
Application number
PCT/JP2018/013868
Other languages
French (fr)
Japanese (ja)
Inventor
宣彦 鈴木
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Priority to PCT/JP2018/013868 priority Critical patent/WO2019187101A1/en
Publication of WO2019187101A1 publication Critical patent/WO2019187101A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/02—Details
    • H05B33/06—Electrode terminals
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/10—Apparatus or processes specially adapted to the manufacture of electroluminescent light sources
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/12—Light sources with substantially two-dimensional radiating surfaces

Definitions

  • the present invention relates to a display device and a manufacturing method thereof.
  • a display device in which a light emitting element such as an organic EL element constitutes a pixel includes a control circuit that performs electrical control on the pixel in order to display an image.
  • Examples of the control circuit include a scanning line driving circuit, and these control circuits are required to operate precisely. Therefore, it has been necessary to inspect whether the control circuit is defective.
  • an inspection probe is penetrated from the sealing resin to a target internal node and directly contacted to measure an electrical signal (Patent Document 1).
  • the display device emits light from the display area, the frame area provided around the display area, and the first light emitting element provided in the display area.
  • a plurality of pixel circuits including the first light emitting elements provided at intersections of the lines and the plurality of control lines, and corresponding control lines are activated at a timing when the data signal is supplied to the data lines.
  • the wiring intersects at the end face, and the other of the anode and the cathode of the second light emitting element is electrically connected to the second lead wiring extending to the end face of the display device, and the second lead wiring intersects at the end face. It is characterized by being made.
  • the second light emitting element may be provided in a gate driver monolithic circuit (GDM) region provided in the frame region adjacent to the outside in the left-right direction of the display region.
  • GDM gate driver monolithic circuit
  • the gate driver monolithic circuit is referred to as a GDM region.
  • the GDM region is a region where a plurality of transistors constituting a scanning line driving circuit and an emission driver are provided.
  • the semiconductor device further includes a planarization film provided on the data line and the control line, and the first light emitting element is formed on the planarization film, and includes a first electrode, a second electrode, and the first electrode.
  • a functional layer provided between one electrode and the second electrode, and a trench penetrating the planarizing film is formed in the planarizing film, the same layer as the second electrode and the first electrode.
  • the metal layer formed of the same material may cover the inner surface of the trench and contact each other inside the trench, and the second light emitting element may be provided inside the trench. preferable.
  • the light emitting layer of the first light emitting element and the light emitting layer of the second light emitting element have the same shape and size, and the opening of the edge cover of the light emitting layer of the first light emitting element is the second light emitting element. It is preferable that the light emitting layer is formed larger than the opening of the edge cover of the light emitting layer.
  • the “same shape and size” means the same when the light emitting material of the light emitting layer is deposited on the display region and the frame region using a mask having the same shape and the same size mask pattern. This means that a light emitting layer having the same shape and size is formed in the display area and the frame area. Accordingly, the light emitting layer of the first light emitting device and the light emitting layer of the second light emitting device do not necessarily have the same shape and the same size.
  • a plurality of types of light emitting elements that emit different colors are used for the plurality of second light emitting elements respectively provided on the plurality of control lines.
  • a plurality of the nodes are provided, and a plurality of types of light emitting elements that emit different colors are used for the plurality of second light emitting elements respectively provided at the plurality of nodes.
  • control line is a scanning line and an emission line
  • control circuit is a scanning line drive circuit and an emission driver
  • the plurality of second light emitting elements respectively provided on the scanning line and the emission line include It is preferable that a plurality of types of light emitting elements that emit different colors are used.
  • control line is a scanning line and the control circuit is a scanning line driving circuit. Furthermore, it is preferable that the control line is an emission line and the control circuit is an emission driver.
  • the second light emitting element is provided outside the side of the display area intersecting with the data line.
  • the second light emitting element provided for each data line, the second light emitting element provided in the frame region for each data line, and a data line driving circuit for supplying the data signal to the data line.
  • the light emitting element controls light emission by inputting an electric signal flowing through the data line or an electric signal flowing through a node provided in the data line driving circuit to a control terminal of a transistor connected to each data line. Even if it is what is done.
  • the data line driving circuit includes a demultiplexer.
  • first routing wiring extends through the end face and is connected to the first constant voltage source
  • second routing wiring extends through the end face to obtain a second constant voltage. Even those connected to a source are preferred.
  • the cut surface of the first lead wire and the cut surface of the second lead wire at the end face are formed by a semiconductor layer formed as a conductor.
  • first light emitting element and the second light emitting element are preferably organic EL elements.
  • a method for manufacturing a display device causes a display region, a frame region provided around the display region, and a first light emitting element provided in the display region to emit light.
  • a method of manufacturing a display device for displaying an image wherein a plurality of data lines to which a data signal for displaying the image is supplied and a plurality of control lines arranged to intersect the plurality of data lines Corresponding to the plurality of pixel circuits including the first light emitting elements provided at the intersections of the plurality of data lines and the plurality of control lines, and the timing at which the data signal is supplied to the data lines.
  • the second light emitting element controls light emission when an electric signal flowing through the control line or an electric signal flowing through a node provided in the control circuit is input to a control terminal of the first transistor.
  • a first conduction terminal of the transistor is connected to one of an anode and a cathode of the second light emitting element, and the second conduction terminal of the first transistor is connected to the first constant voltage via the end face of the display device.
  • An electrical signal that flows through the control line or an electrical signal that flows through a node provided in the control circuit is input to the second light emitting element.
  • first routing wiring and the second routing wiring are cut at the end face after detecting and evaluating light emission from the second light emitting element.
  • the second light emitting element and the first light emitting element are formed simultaneously.
  • the present invention it is not necessary to directly contact a probe with a control line to be inspected or a node provided in a control circuit, and an inspection apparatus that enables non-contact inspection of a node is realized. Can do. As a result, it is possible to eliminate the occurrence of damage to the metal wiring constituting the control line or node and the sealing resin covering the surface of the metal wiring, and to prevent the occurrence of secondary defects in the inspection process using the contact probe. can do. In addition, it is possible to easily cope with inspection of a display device built on a flexible substrate as the thickness is reduced.
  • the second light emitting element can emit light stably by the first constant voltage source and the second constant voltage source connected to the lead line, and a highly reliable inspection can be realized. it can.
  • both thinning and narrowing of the display device can be realized.
  • FIG. 1 shows a circuit configuration of a test circuit 10 according to a first embodiment.
  • 2 is a timing chart of the inspection circuit 10 according to the first embodiment.
  • An example of a cross-sectional structure of the display device 2 is shown from the periphery of the GDM region to the cut end 2a.
  • FIG. 6 shows an enlarged view of the structure of a trench 33 surrounded by a two-dot chain line in FIG. 5.
  • FIG. 1 shows a schematic diagram of a demultiplexer DM.
  • A shows a cross-sectional example around the first light-emitting element 6, and
  • the top view (a) of the 1st light emitting element 6 and the top view (b) of the 2nd light emitting element 9 are shown.
  • inspection circuit 10 in the example 1 of a detection are shown.
  • inspection circuit 10 in the example 2 of a detection are shown.
  • inspection circuit 10 in the example 3 of a detection are shown.
  • inspection circuit 10 in the example 4 of a detection are shown.
  • the first light emitting element 6 is a pixel at each intersection of a plurality of data lines Da arranged along the vertical direction and a plurality of control lines 8 arranged to intersect the data lines Da.
  • 1 shows a schematic diagram of a display device 2 including a display region 3 in which a pixel 4 is configured together with a circuit 5.
  • the display device 2 is provided with a control circuit 1 connected to the control line 8 in a frame area 7 provided around the display area 3.
  • the display area 3 is an area where image content is displayed.
  • the frame area 7 provided outside the periphery of the display area 3 is not an area in which image content is displayed, but an area that can be covered with a frame when the display device 2 is commercialized.
  • control circuit 1 may be either a scanning line driving circuit or an emission driver.
  • the control line 8 functions as a scanning line when the control circuit 1 is a scanning line driving circuit, and functions as an emission line when the control circuit 1 is an emission driver.
  • control circuit 1 When the control circuit 1 is a scanning line drive circuit or an emission driver, a control function for activating the corresponding control line 8 at a timing when a data signal is supplied to the data line Da is provided.
  • a plurality of control lines 8 are arranged from the control circuit 1 toward the display area 3.
  • the control lines are distinguished from the control lines 8 (n ⁇ 1), 8 (n), and 8 (n + 1) from the lower side of the display device 2.
  • the control lines 8 may be collectively referred to. Note that n represents an integer.
  • FIG. 1 An example of a circuit configuration when the control circuit 1 is a scanning line driving circuit is shown in FIG.
  • the scanning line driving circuit shown in FIG. 2 sends a signal to the node n connected to the control terminal of the transistor TC and one end of the capacitor Cbst via the transistor TA turned on by the signal from the control line 8 (n ⁇ 1). Is retained.
  • the transistor TC is turned on by the signal held at the node n, and the control line 8 (n) is activated by receiving the input of the clock signal CKA at the first conduction terminal of the transistor TC.
  • the transistor TD holds the potential of the control line 8 (n). Thereafter, the transistor TD is turned on by the clock signal CKB in an inverted relationship with the clock signal CKA, and discharges the charge of the control line 8 (n) to the low-potential power supply VSS.
  • the transistor TB is turned on by a signal from the control line 8 (n + 1) after a lapse of a predetermined period after the control line 8 (n) becomes active, and charges corresponding to the signal held at the node n are supplied to a low potential power source. Discharge to VSS.
  • the control line 8 is introduced into the display area 3 via the frame area 7.
  • the frame area 7 is provided with a second light-emitting element 9 that is connected so as to be able to emit light when an electric signal flowing through a control line 8 or a node provided in the control circuit 1 is input to constitute an inspection circuit 10. It becomes.
  • the first light emitting element 6 and the second light emitting element 9 are organic EL elements.
  • a trench 33 is formed so as to surround the display area 3.
  • the trench 33 has a function of blocking moisture, oxygen, and the like from entering the planarizing film 24 made of an organic resin, and preventing deterioration of the first light emitting element 6 constituting the display region 3. It is a groove structure provided. Therefore, by providing the second light emitting element 9 also inside the trench 33 as shown in FIG. 1, it is possible to prevent the deterioration similarly to the first light emitting element 6, and the second light emitting element 9 can be inspected by light emission. It can be done reliably.
  • the light emitted from the second light emitting element 9 can be received by the light receiving device 11 provided outside the display device 2.
  • the light receiving device 11 can show the intensity of light received by a light receiving element (not shown) provided therein in a graph with respect to time, and is provided in a node provided in the control line 8 or the control circuit 1.
  • the relationship with the electrical signal flowing through the A photodiode can be used as the light receiving element of the light receiving device 11.
  • FIG. 3 shows a circuit configuration of the inspection circuit 10 according to the first embodiment when the control circuit 1 is a scanning line driving circuit or an emission driver.
  • a PMOS transistor T1 is provided as a first transistor for turning on / off the light emission drive of the second light emitting element 9.
  • the control terminal g1 of the transistor T1 is connected to the control line 8.
  • the second conduction terminal s1 of the transistor T1 is electrically connected to the first lead wiring H1 that is wired to the divided end portion 2a of the display device 2 (the end face of the display device 2).
  • the first routing wiring H1 is further extended via the divided end portion 2a of the display device 2, and is a drive power supply ELVDD (high power supply voltage source) that is a first constant voltage source that drives the pixels 4 in the display region 3. Is connected.
  • ELVDD high power supply voltage source
  • the anode 9a of the second light emitting element 9 is connected to the first conduction terminal d1 of the transistor T1.
  • the cathode 9c of the second light emitting element 9 is electrically connected to the second lead wiring H2 that is wired to the divided end portion 2a of the display device 2.
  • the second routing wiring H2 is further extended via the split end portion 2a of the display device 2 and connected to a cathode power supply ELVSS (low power supply voltage source) which is a second constant voltage source.
  • ELVSS low power supply voltage source
  • the current output from the control circuit 1 can be passed through the second light emitting element 9 to emit light.
  • the drive power supply ELVDD and the cathode power supply ELVSS are respectively connected to the anode side and the cathode side of the first light emitting element 6 (not shown), and drive the first light emitting element 6 to emit light when the display device 2 is driven.
  • a high power supply voltage source and a low power supply voltage source as independent power supply sources different from the drive power supply ELVDD and the cathode power supply ELVSS are connected to the second light emitting element 9 respectively, A configuration in which the second light emitting element 9 is driven to emit light may be used.
  • the second light emitting element 9 is provided in the GDM area provided in the frame area 7 in the vicinity of the outside in the left-right direction of the display area 3.
  • the second light emitting element 9 is formed inside the trench 33 formed by the dot-patterned shaded area so as to surround the display area 3 in the GDM area.
  • FIG. 4 shows a timing chart of the inspection circuit 10 in the first embodiment.
  • the voltage of the drive power supply ELVDD was maintained at + 4.6V
  • the voltage of the cathode power supply ELVSS was maintained at ⁇ 3.0V.
  • the transistor T1 is turned on by applying a voltage that changes from ⁇ 8.0 V to +5.0 V as shown in FIG. In this case, it is possible to determine that the control circuit 1 is operating normally by detecting the light emitted from the second light emitting element 9 with the light receiving device 11 at the timing when the voltage is applied to the control line 8. .
  • the current from the drive power supply ELVDD to the second light emitting element 9 can be cut off by turning off the transistor T1.
  • the light receiving device 11 may visually recognize the light emitted from the second light emitting element 9 using human eyes.
  • the circuit configuration can be simplified as compared with the case where an independent power supply source is provided.
  • current supply from the drive power supply ELVDD is continuously performed at least during the inspection period t1, and the transistor T1 is turned on by the voltage output from the control circuit 1, whereby the current from the drive power supply ELVDD is turned on. Can be caused to flow through the second light emitting element 9 to emit light.
  • FIG. 5 shows an example of a structure constituting a top emission type light emitting element.
  • a base material 12, a resin layer 13, and a barrier layer 14 (base coat layer) are formed in order from the lower side.
  • a data line Da and a control line 8 are provided thereon, and a planarizing film 24 is provided thereon.
  • a transistor T1 is formed below the planarizing film 24. Further, the first light emitting element 6 and the second light emitting element 9 are provided on the planarizing film 24. Note that inorganic insulating films 21, 22, and 23 are formed on the layer provided with the transistor T1.
  • an anode electrode 25 as a first electrode and a cathode electrode 28 as a second electrode are provided to drive the first light emitting element, and the anode electrode 25 and the cathode electrode are provided.
  • 28 is provided with a light emitting layer 27 as a functional layer.
  • An inorganic sealing film 29 that covers the cathode electrode 28 is provided on the cathode electrode 28. Further, the sealing layer 17 and the functional film 19 are provided on the inorganic sealing film 29.
  • FIG. 6 shows an enlarged view of the structure inside the ellipse consisting of the two-dot chain line in FIG.
  • the trench 33 is formed in a groove shape penetrating the planarizing film 24 from the sealing layer 17 side.
  • the inner surface of the trench 33 is covered with a cathode layer 28 and a metal layer 25a formed of the same material as the anode electrode 25, and the metal layer 25a and the cathode electrode 28 are in contact with each other inside the trench 33. .
  • the trench 33 blocks moisture, oxygen, and the like from entering the planarizing film 24 made of an organic resin, and prevents the first light emitting element 6 constituting the display region 3 from deteriorating. Therefore, by providing the second light emitting element 9 also inside the trench 33, it is possible to prevent the deterioration as in the case of the first light emitting element 6, and the inspection by the light emission of the second light emitting element 9 can be more reliably performed. .
  • FIG. 5 shows an example of the first routing wiring H1 that is electrically connected to the second conduction terminal s1 of the transistor T1 and is wired to the dividing end 2a of the display device 2.
  • the first routing wiring H1 is composed of H1a, H1b, H1c, and H1m.
  • the first routing wiring H1 extends from the first routing wiring H1a formed in the source layer to the first routing wiring H1b formed in the gate layer and extends beyond the GDM region.
  • the first routing wiring H1b is connected again to the first routing wiring H1c formed in the source layer.
  • the first routing wiring H1c is connected to the first routing wiring H1m made of a semiconductor made into a conductor in the vicinity of the split end portion 2a of the display device 2, and reaches the split end portion 2a.
  • the first routing wirings H1a, H1b, and H1c are made of a metal layer.
  • the second routing wiring that is conducted to the cathode 9c of the second light emitting element 9 also reaches the divided end portion 2a.
  • the first routing wiring H1 and the second routing wiring H2 are detected by the light emission from the second light emitting element 9 and finished the inspection process, and then cut at the dividing end portion 2a to drive the power supply ELVDD and the cathode.
  • the state disconnected from the power source ELVSS is shown.
  • the cut surfaces of the routing wirings H1 and H2 are formed of a conductor semiconductor layer, the metal layer is corroded on the cut surface, and the reliability of the display region 3 can be prevented from being lowered.
  • the second light emitting element 9 is provided outside the side of the display area 3 intersecting with the data line Da as shown in FIG.
  • the second light emitting element 9 is provided in the frame area 7 for each data line Da.
  • the data line Da is connected to a data line driving circuit 100 that supplies a data signal.
  • the second light emitting element 9 provided for each data line Da includes a transistor T1 in which an electric signal flowing through the data line Da or an electric signal flowing through a node provided in the data line driving circuit 100 is connected to each data line Da. The light emission is controlled by being input to the control terminal.
  • the data line driving circuit 100 includes a demultiplexer DM.
  • FIG. 7 shows an outline of the structure of the demultiplexer DM.
  • the demultiplexer DM is a device that exhibits a function of receiving one signal as an input, dividing it into a plurality of signals, and outputting it.
  • the structure shown in FIG. 7 will be described as an example.
  • the arrow direction pointing downward is the display area 3.
  • the data line Da1 is branched and connected to the conduction terminals of the two transistors arranged in the region indicated by Dm1.
  • the two transistors in Dm1 are on / off controlled by signals input from the switch signal lines ASW1 and ASW2.
  • the data signal input from the data line Da1 to Dm1 can be distributed to the data line Da11 or the data line Da12 and output.
  • the data signals are distributed to the data lines Da21 and Da22 and the data lines Da31 and Da32 by signals input from the switch signal lines ASW1 and ASW2 common to the data line Da1. Can do.
  • the inspection circuit 10 including the second light emitting element 9 and the transistor T1 can be connected to the data lines Da11, Da12, Da21, Da22, Da31, and Da32. Further, the inspection circuit 10 may be connected to a node provided in the data line driving circuit 100, for example, the demultiplexer DM.
  • the inspection circuit 10 has the same structure as that in the first embodiment (see the parenthesis in FIG. 3). See the sign). That is, as shown in FIG. 3, the data line Da is connected to the control terminal g1 of the transistor T1, and the second conduction terminal s1 of the transistor T1 is wired to the dividing end 2a of the display device 2. It is electrically connected to the wiring H1. Further, the first routing wiring H1 is further extended through the divided end portion 2a of the display device 2, and is connected to a driving power source ELVDD that is a first constant voltage source for driving the pixels 4 in the display region 3.
  • ELVDD driving power source
  • the anode 9a of the second light emitting element 9 is connected to the first conduction terminal d1 of the transistor T1, and the cathode 9c of the second light emitting element 9 is wired to the dividing end 2a of the display device 2.
  • the structure that is electrically connected to the two routing wirings H2 is the same as that in the first embodiment.
  • the second lead wiring H2 is further extended via the divided end portion 2a of the display device 2, and is connected to the cathode power source ELVSS which is the second constant voltage source.
  • the first routing wiring H1 and the second routing wiring H2 in the second embodiment are also cut by the dividing end portion 2a after detecting the light emission from the second light emitting element 9 and finishing the inspection process, and the driving power supply ELVDD. And the cathode power supply ELVSS.
  • the cut surfaces of the routing wirings H1 and H2 are formed of a conductor semiconductor layer, the metal layer is corroded on the cut surface, and the reliability of the display region 3 can be prevented from being lowered.
  • the second light emitting element 9 can be formed and arranged in the frame region 7 so as to be clearly distinguished from the first light emitting element formed in the display region 3. Further, when forming the display region 3 constituted by the pixels 4 including the first light emitting elements, the light emitting elements included in the dummy pixels formed slightly outside the outer edge of the display region 3 are used as the second light emitting elements. You can also That is, the first light emitting element and the second light emitting element are formed simultaneously.
  • FIG. 8A shows an example of a cross section around the sub-pixel SPA showing one emission color of the first light emitting element 6, and FIG. 8B shows one emission color as the second light emitting element 9.
  • An example of a cross section around the subpixel SPB shown is shown.
  • the light emitting elements shown in FIGS. 8A and 8B are top emission types that emit light upward, and in order from the bottom, a base material 12, a resin layer 13, a barrier layer 14 (base coat layer), and a TFT layer. 15, a light emitting element layer 16, a sealing layer 17, an adhesive layer 18 and a functional film 19.
  • the TFT layer 15 is formed on the semiconductor film 20, the inorganic insulating film 21 formed above the semiconductor film 20, the gate electrode G formed above the inorganic insulating film 21, and the layer above the gate electrode G.
  • the inorganic insulating film 22 is formed; the capacitive electrode C formed above the inorganic insulating film 22; the inorganic insulating film 23 formed above the capacitive electrode C; and the upper layer than the inorganic insulating film 23.
  • a thin film transistor Tr (light emission control transistor) is configured to include the semiconductor film 20, the inorganic insulating film 21 (gate insulating film), and the gate electrode G.
  • the source electrode S is connected to the source region of the semiconductor film 20, and the drain electrode D is connected to the drain region of the semiconductor film 20.
  • the semiconductor film 20 is made of, for example, low-temperature polysilicon (LTPS) or an oxide semiconductor.
  • LTPS low-temperature polysilicon
  • FIG. 8 the TFT having the semiconductor film 20 as a channel is shown in a top gate structure.
  • the light emitting element layer 16 is an organic light emitting diode layer in the present embodiment, and the anode electrode 25 formed above the planarizing film 24 and the subpixel SPA in the active region (the region overlapping the light emitting element layer 16) or It includes an edge cover 26 that is a planarizing film that defines SPB, a light emitting layer 27 formed above the anode electrode 25, and a cathode electrode 28 formed above the light emitting layer 27.
  • An organic light emitting diode (OLED) is configured to include the anode electrode 25, the light emitting layer 27, and the cathode electrode 28.
  • the edge cover 26 surrounds the end of the anode electrode 25.
  • the light emitting layer 27 is formed in a region surrounded by the edge cover 26 by an evaporation method or an ink jet method.
  • the anode electrode 25 is composed of, for example, a laminate of ITO (Indium Tin Oxide) and an alloy containing Ag, and has light reflectivity.
  • the cathode electrode 28 can be made of a light-transmitting conductive material such as ITO or IZO (Indium Zinc Oxide).
  • the cathode electrode 28 is translucent and the anode electrode 25 is light reflective, the light emitted from the light emitting layer 27 is directed upward and becomes top emission.
  • the sealing layer 17 is translucent, and includes an inorganic sealing film 29 that covers the cathode electrode 28, an organic sealing film 30 that is formed above the inorganic sealing film 29, and an organic that covers the organic sealing film 30. And a sealing film 31.
  • the sealing layer 17 covers the light emitting element layer 16 and prevents penetration of foreign substances such as water and oxygen into the light emitting element layer 16.
  • the functional film 19 has, for example, an optical compensation function, a touch sensor function, a protection function, and the like.
  • FIG. 9 is a plan view showing a structural example of the sub-pixels SPA and SPB.
  • the sub-pixel SPA includes at least an edge cover 26 having an opening HA and a light emitting layer 27 disposed above the edge cover 26. Yes.
  • the edge cover 26 surrounds the entire periphery of the opening HA.
  • the light emitting layer 27 is formed so as to completely fill at least the opening HA.
  • the area of the light emitting layer 27 is larger than the area of the opening HA.
  • a range of the light emitting layer 27 that overlaps the opening HA contributes to light emission of the first light emitting element 6.
  • the sub-pixel SPB has an edge cover 26 having an opening HB, an upper layer than the edge cover 26, and a light-emitting layer 27 of the sub-pixel SPA. At least a light emitting layer 27 having the same shape and the same size is provided.
  • the edge cover 26 surrounds the entire periphery of the opening HB.
  • the light emitting layer 27 is formed so as to completely fill at least the opening HB.
  • the area of the light emitting layer 27 is larger than the area of the opening HB.
  • a range of the light emitting layer 27 that overlaps the opening HB contributes to light emission of the second light emitting element 9.
  • the opening HA of the edge cover 26 of the light emitting layer 27 of the first light emitting element 6 is larger than the opening HB of the edge cover 26 of the light emitting layer 27 of the second light emitting element 9.
  • the opening HB of the edge cover 26 of the light emitting layer 27 of the second light emitting element 9 is thus obtained.
  • the light emitting layer 27 can be formed so as to cover the opening HB of the edge cover 26, and light can be reliably emitted in a desired light emitting region.
  • the second light-emitting element 9 is formed in the central portion side instead of the end of the vapor deposition mask, or the second light-emitting element 6 is used by using a vapor deposition mask different from the first light-emitting element 6.
  • the light emitting area of the first light emitting element 6 and the light emitting area of the second light emitting element 9 may be the same size.
  • the above-mentioned “same shape and size” means that the light emitting material of the light emitting layer 27 is deposited on the display region 3 and the outer edge region of the display region 3 using a mask having the same shape and the same size mask pattern. In this case, it means that the light emitting layer 27 having the same shape and the same size is formed as a result in the display area 3 and the outer edge area of the display area 3 (hereinafter referred to as a dummy area). Therefore, when using the vapor deposition technique, even if a mask having the same size mask pattern is used, the light emitting layer 27 of the subpixel SPA and the light emitting layer 27 of the subpixel SPB are not necessarily completely the same shape and the same. The case where the size is not formed is also included.
  • the dummy area 7a is formed using one mask when the display area 3 is formed. However, the dummy area 7a is formed slightly outside the area where the image content is displayed, as shown by a one-dot chain line in FIG. Therefore, it belongs to the frame area 7 in the present invention.
  • the pixels formed in the dummy area 7a are referred to as dummy pixels.
  • the light emitting elements constituting the dummy pixels can be formed at the same time as the first light emitting element 6, and can be the second light emitting element 9.
  • the opening HA opening the inner side of the anode electrode 25 formed in the display area 3 is larger than the opening HB opening the inner side of the anode electrode 25 formed in the dummy area 7a.
  • the light emitting layer 27 formed in the display region 3 has the same shape and the same size as the light emitting layer 27 formed in the dummy region 7a.
  • the light emitting layer 27 is formed so as to completely cover the opening HB in the dummy region 7a even if the accuracy of the vapor deposition pattern when the light emitting material is deposited on the dummy region 7a is low. . Therefore, the normally functioning sub-pixel SPB can be formed in the dummy region 7a.
  • the contact hole of the thin film transistor Tr is formed at a position that does not overlap with the opening HA.
  • the contact hole of the capacitor electrode C is also formed at a position that does not overlap with the opening HA.
  • the contact hole of the thin film transistor Tr is formed in a portion of the light emitting layer 27 that does not overlap the opening HB (a portion that overlaps the opening HA in the display region 3). be able to.
  • the contact hole of the capacitor electrode C can also be formed in a portion of the light emitting layer 27 that does not overlap the opening HB.
  • the second light emitting elements 9 and the inspection circuit 10 are formed. No special space is required, and the display device 2 can be easily narrowed. Further, the region 32 can be used as another circuit arrangement space.
  • the plurality of second light emitting elements 9 respectively provided on the plurality of control lines 8 (n ⁇ 1), the control lines 8 (n), the control lines 8 (n + 1),. You may form in a light emitting element of a kind.
  • Detection Example 1 the potential of the internal node n in FIG. 2 is measured as an output of the control circuit 1 or an internal node of the control circuit 1, and based on a signal input to the second light emitting element 9 from the control line 8 If the waveform is different from the expected light emission waveform, it is possible to detect an abnormality in the control line 8. For example, a method of detecting whether or not the second light emitting element 9 emits light twice by inputting a signal to the control line 8 twice and correctly emitting light twice can be adopted. As shown in FIG. 10, unlike the expected light emission waveform, when there is no signal change for the first time, an abnormality of the control line 8 or an internal node of the control circuit 1 can be detected.
  • control line 8 (n ) there is a method of detecting an abnormality of the control line 8 or an internal node of the control circuit 1 based on the presence or absence of light emission by causing the upper and lower stages, that is, three second light emitting elements to emit light simultaneously.
  • the control line 8 (n + 1) When signals are simultaneously input to the control line 8 (n ⁇ 1), the control line 8 (n), and the control line 8 (n + 1) shown in FIG. 1, the control line 8 (n + 1) and the control line 8 (n ⁇
  • the control line 8 (n ) Abnormality can be detected.
  • Detection Example 2 When a defective element such as an abnormal resistance or an abnormal TFT exists on the control circuit 1 side of the portion connected to the control line 8 of the inspection circuit 10, the expected light emission waveform shown in the upper part of FIG. On the other hand, a defect can be detected by outputting a rounded waveform in the light emission signal as shown in the lower part of FIG.
  • the expected intensity shown in the upper part of FIG. 13 is obtained by measuring the light emission intensity from the second light emitting element 9 provided at a position farther from the control circuit 1 than the open part. With respect to the emitted light waveform, as shown in the lower part of FIG. 13, the measured waveform is indefinite or a waveform that does not match the expected light emission waveform is detected.
  • the 2nd light emitting element 9 may be provided in all the control lines 8, and some control among the some control lines 8 is possible. Each line 8 may be provided.
  • the second light emitting element 9 may be provided for every two or every three control lines 8.
  • detection example 1 to detection example 4 the example of detecting a failure of a node in the control line or the control circuit has been described. However, detection of a failure of a node in the data line or the data line driving circuit is also detected in the detection example 1. This can be performed in the same manner as in Detection Example 4.
  • This manufacturing method can detect defects in the scanning line drive circuit or the emission driver after the material vapor deposition process for forming the light emitting element and before the thin film sealing (TFE) process. It is possible to sort out driver defects at an earlier stage.
  • TFE thin film sealing
  • identification of a defective stage of wiring in the control circuit 1 connected to the control line 8 based on the detection example 1 identification of a defective element in the control circuit 1 based on the detection example 2, control based on the detection example 3
  • a display device manufacturing method in which at least one of specifying a short circuit between wires in the circuit 1 and specifying a wire open in the control circuit based on the detection example 4 is performed is preferable.
  • the display device 2 can be manufactured while clarifying the failure factors shown in the detection examples 1 to 4 at an earlier stage than before.
  • the display according to the present embodiment is not particularly limited as long as the display panel includes a display element.
  • the display element is a display element whose luminance and transmittance are controlled by current.
  • an organic EL (Electro Luminescence) having an OLED (Organic Light Emitting Diode) is used.
  • OLED Organic Light Emitting Diode
  • a display, or an EL display QLED (Quantum ⁇ dot ⁇ ⁇ Light Emitting Diode) such as an inorganic EL display provided with an inorganic light emitting diode, or the like.

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Abstract

This display device is provided with: a display region formed of first light emitting elements constituting pixels together with a pixel circuit and being arranged in a matrix; and a control circuit having a function of controlling electricity to the display region, wherein a second light emitting element connected so as to be able to emit light upon receiving an electric signal flowing through a control line connected to the control circuit or an electric signal flowing through a node provided in the control circuit, is provided in a frame region.

Description

表示デバイス及びその製造方法Display device and manufacturing method thereof
　本発明は、表示デバイス及びその製造方法に関する。 The present invention relates to a display device and a manufacturing method thereof.
　有機ＥＬ素子等の発光素子が画素を構成する表示デバイスは、画像を表示するために画素への電気制御を行う制御回路を備える。制御回路には、例えば走査線駆動回路が挙げられ、これらの制御回路には精密な動作が求められる。そこで、制御回路に不具合が生じていないかを検査する必要があった。従来の検査手段としては、検査プローブを、封止樹脂の上から対象となる内部ノードへ貫通させて直接接触させて、電気信号を測定するものであった（特許文献１）。 A display device in which a light emitting element such as an organic EL element constitutes a pixel includes a control circuit that performs electrical control on the pixel in order to display an image. Examples of the control circuit include a scanning line driving circuit, and these control circuits are required to operate precisely. Therefore, it has been necessary to inspect whether the control circuit is defective. As a conventional inspection means, an inspection probe is penetrated from the sealing resin to a target internal node and directly contacted to measure an electrical signal (Patent Document 1).
特開平０９－０６１４５８号公報Japanese Patent Laid-Open No. 09-061458
　しかし、近年は表示デバイスの薄型化が著しく、また柔軟性を有する基板上に構築される表示デバイスも開発されているため、検査時における表示装置の平坦化が乏しくなってきていることから、正確に検査プローブを対象となるノードへ接触させることが困難となってきていた。 In recent years, however, display devices have become extremely thin, and display devices constructed on flexible substrates have also been developed. It has become difficult to bring the inspection probe into contact with the target node.
　さらに、高精細な画像による臨場感の高い視聴を可能とするため、表示デバイスの狭額縁化に対する要望も強い。 Furthermore, there is a strong demand for narrower display devices to enable high-definition viewing with a high sense of presence.
　そこで、上記課題を解決する手段として本発明に係る表示デバイスは、表示領域と、表示領域の周囲に設けられた額縁領域と、表示領域に設けられた第１発光素子を発光させることにより、画像を表示する表示デバイスであって、前記画像を表示するデータ信号が供給される複数のデータ線と、前記複数のデータ線と交差するように配設された複数の制御線と、前記複数のデータ線及び前記複数の制御線の各交点に設けられた前記第１発光素子を備えた複数の画素回路と、前記データ線に前記データ信号が供給されるタイミングで、対応する制御線をアクティブにする制御回路と、前記制御線毎に前記額縁領域に設けられた第２発光素子と、前記第２発光素子の発光駆動をオン/オフする第１トランジスタと、を備え、前記第２発光素子は、前記制御線を流れる電気信号又は前記制御回路内に設けられたノードを流れる電気信号が前記第１トランジスタの制御端子に入力されることにより発光が制御され、前記第１トランジスタの第１導通端子は、前記第２発光素子の陽極又は陰極の一方に接続され、前記第１トランジスタの第２導通端子は、前記表示デバイスの端面まで延伸する第１引き回し配線と電気的に導通し、前記第１引き回し配線は前記端面において交差し、前記第２発光素子の陽極又は陰極の他方は、前記表示デバイスの前記端面まで延伸する第２引き回し配線と電気的に導通し、第２引き回し配線は前記端面において交差されてなることを特徴とする。 Accordingly, as a means for solving the above problems, the display device according to the present invention emits light from the display area, the frame area provided around the display area, and the first light emitting element provided in the display area. A plurality of data lines to which a data signal for displaying the image is supplied, a plurality of control lines arranged to intersect the plurality of data lines, and the plurality of data And a plurality of pixel circuits including the first light emitting elements provided at intersections of the lines and the plurality of control lines, and corresponding control lines are activated at a timing when the data signal is supplied to the data lines. A control circuit; a second light emitting element provided in the frame region for each control line; and a first transistor for turning on / off light emission of the second light emitting element, wherein the second light emitting element includes: Light emission is controlled by inputting an electric signal flowing through the control line or an electric signal flowing through a node provided in the control circuit to the control terminal of the first transistor, and the first conduction terminal of the first transistor is The second conductive terminal of the first transistor is connected to one of the anode and the cathode of the second light emitting element, and is electrically connected to a first lead wiring extending to an end face of the display device, and the first lead is connected. The wiring intersects at the end face, and the other of the anode and the cathode of the second light emitting element is electrically connected to the second lead wiring extending to the end face of the display device, and the second lead wiring intersects at the end face. It is characterized by being made.
　また、前記第２発光素子が、前記額縁領域において前記表示領域の左右方向外側に近接して設けられたゲートドライバモノリシック回路（ＧＤＭ：Ｇａｔｅ　Ｄｒｉｖｅｒ　Ｍｏｎｏｌｉｔｈｉｃ　Ｃｉｒｃｕｉｔ）領域に設けられてなるものであっても好ましい。以下、前記ゲートドライバモノリシック回路をＧＤＭ領域という。ＧＤＭ領域は、走査線駆動回路やエミッションドライバを構成する複数のトランジスタが設けられている領域である。 Further, the second light emitting element may be provided in a gate driver monolithic circuit (GDM) region provided in the frame region adjacent to the outside in the left-right direction of the display region. preferable. Hereinafter, the gate driver monolithic circuit is referred to as a GDM region. The GDM region is a region where a plurality of transistors constituting a scanning line driving circuit and an emission driver are provided.
　さらに、前記データ線及び前記制御線上に設けられた平坦化膜を更に備え、前記第１発光素子は、前記平坦化膜上に形成されるとともに、第１電極と、第２電極と、前記第１電極及び前記第２電極の間に設けられた機能層とを備え、前記平坦化膜には、当該平坦化膜を貫通するトレンチが形成され、前記第２電極及び前記第１電極と同層で同一材料によって形成された金属層は、前記トレンチの内面を覆い、且つ前記トレンチの内部で互いに接触し、前記第２発光素子は、前記トレンチよりも内側に設けられてなるものであっても好ましい。 Furthermore, the semiconductor device further includes a planarization film provided on the data line and the control line, and the first light emitting element is formed on the planarization film, and includes a first electrode, a second electrode, and the first electrode. A functional layer provided between one electrode and the second electrode, and a trench penetrating the planarizing film is formed in the planarizing film, the same layer as the second electrode and the first electrode The metal layer formed of the same material may cover the inner surface of the trench and contact each other inside the trench, and the second light emitting element may be provided inside the trench. preferable.
　さらにまた、前記第１発光素子の発光層と前記第２発光素子の発光層は、同一の形状及び大きさであって、前記第１発光素子の発光層のエッジカバーの開口は、前記第２発光素子の発光層のエッジカバーの開口よりも大きく形成されても好ましい。 Furthermore, the light emitting layer of the first light emitting element and the light emitting layer of the second light emitting element have the same shape and size, and the opening of the edge cover of the light emitting layer of the first light emitting element is the second light emitting element. It is preferable that the light emitting layer is formed larger than the opening of the edge cover of the light emitting layer.
　なお、「同一の形状及び大きさ」とは、発光層の発光材料を同一の形状かつ同一の大きさのマスクパターンを有するマスクを用いて表示領域及び額縁領域にそれぞれ蒸着した場合に、同一の形状かつ同一の大きさの発光層が表示領域及び額縁領域に結果的に形成されることを意味する。従って、前記第１発光素子の発光層と第２発光素子の発光層とは、必ずしも完全に同一の形状かつ同一の大きさである必要はない。 The “same shape and size” means the same when the light emitting material of the light emitting layer is deposited on the display region and the frame region using a mask having the same shape and the same size mask pattern. This means that a light emitting layer having the same shape and size is formed in the display area and the frame area. Accordingly, the light emitting layer of the first light emitting device and the light emitting layer of the second light emitting device do not necessarily have the same shape and the same size.
　また、前記複数の制御線にそれぞれ設けられた複数の前記第２発光素子には、互いに異なる色を発光する複数種類の発光素子が用いられていても好ましい。 Further, it is preferable that a plurality of types of light emitting elements that emit different colors are used for the plurality of second light emitting elements respectively provided on the plurality of control lines.
　さらに、前記ノードは複数設けられ、複数の前記ノードにそれぞれ設けられた複数の前記第２発光素子には、互いに異なる色を発光する複数種類の発光素子が用いられていても好ましい。 Furthermore, it is preferable that a plurality of the nodes are provided, and a plurality of types of light emitting elements that emit different colors are used for the plurality of second light emitting elements respectively provided at the plurality of nodes.
　さらにまた、前記制御線が走査線及びエミッション線であり、前記制御回路が走査線駆動回路及びエミッションドライバであり、前記走査線と前記エミッション線にそれぞれ設けられた複数の前記第２発光素子には、互いに異なる色を発光する複数種類の発光素子が用いられていても好ましい。 Furthermore, the control line is a scanning line and an emission line, the control circuit is a scanning line drive circuit and an emission driver, and the plurality of second light emitting elements respectively provided on the scanning line and the emission line include It is preferable that a plurality of types of light emitting elements that emit different colors are used.
　また、前記制御線が走査線であり、前記制御回路が走査線駆動回路であっても好ましい。さらに、前記制御線がエミッション線であり、前記制御回路がエミッションドライバであっても好ましい。 It is also preferable that the control line is a scanning line and the control circuit is a scanning line driving circuit. Furthermore, it is preferable that the control line is an emission line and the control circuit is an emission driver.
　さらにまた、前記第２発光素子が、前記データ線と交差する前記表示領域の辺の外側に設けられてなるものであっても好ましい。 Furthermore, it is preferable that the second light emitting element is provided outside the side of the display area intersecting with the data line.
　また、前記データ線毎に前記額縁領域に設けられた前記第２発光素子と、前記データ線に前記データ信号を供給するデータ線駆動回路と、を備え前記データ線毎に設けられた前記第２発光素子は、前記データ線を流れる電気信号又は前記データ線駆動回路内に設けられたノードを流れる電気信号が、前記データ線毎に接続されるトランジスタの制御端子に入力されることにより発光が制御されるものであっても好ましい。さらに、前記データ線駆動回路は、デマルチプレクサを含むものであっても好ましい。 The second light emitting element provided for each data line, the second light emitting element provided in the frame region for each data line, and a data line driving circuit for supplying the data signal to the data line. The light emitting element controls light emission by inputting an electric signal flowing through the data line or an electric signal flowing through a node provided in the data line driving circuit to a control terminal of a transistor connected to each data line. Even if it is what is done. Furthermore, it is preferable that the data line driving circuit includes a demultiplexer.
　さらにまた、前記第１引き回し配線は、前記端面を経由して延伸して第１の定電圧源に接続され、前記第２引き回し配線は、前記端面を経由して延伸して第２の定電圧源に接続されてなるものであっても好ましい。 Furthermore, the first routing wiring extends through the end face and is connected to the first constant voltage source, and the second routing wiring extends through the end face to obtain a second constant voltage. Even those connected to a source are preferred.
　また、前記端面における前記第１引き回し線の切断面及び前記第２引き回し線の切断面は、導体化された半導体層によって形成されてなるものであっても好ましい。 Further, it is preferable that the cut surface of the first lead wire and the cut surface of the second lead wire at the end face are formed by a semiconductor layer formed as a conductor.
　さらに、前記第１発光素子及び前記第２発光素子は、有機ＥＬ素子であることが好ましい。 Furthermore, the first light emitting element and the second light emitting element are preferably organic EL elements.
　また、上記課題を解決する手段として本発明に係る表示デバイスの製造方法は、表示領域と、表示領域の周囲に設けられた額縁領域と、表示領域に設けられた第１発光素子を発光させることにより、画像を表示する表示デバイスの製造方法であって、前記画像を表示するデータ信号が供給される複数のデータ線と、前記複数のデータ線と交差するように配設された複数の制御線と、前記複数のデータ線及び前記複数の制御線の各交点に設けられた前記第１発光素子を備えた複数の画素回路と、前記データ線に前記データ信号が供給されるタイミングで、対応する制御線をアクティブにする制御回路と、前記制御線毎に前記額縁領域に設けられた第２発光素子と、前記第２発光素子の発光駆動をオン/オフする第１トランジスタと、を備え、前記第２発光素子は、前記制御線を流れる電気信号又は前記制御回路内に設けられたノードを流れる電気信号が前記第１トランジスタの制御端子に入力されることにより発光が制御され、前記第１トランジスタの第１導通端子は、前記第２発光素子の陽極又は陰極の一方に接続されてなり、前記第１トランジスタの第２導通端子を、前記表示デバイスの端面を経由して第１の定電圧源に接続された第１引き回し線と電気的に導通させ、前記第２発光素子の陽極又は陰極の他方を、前記表示デバイスの端面を経由して第２の定電圧源に接続された第２引き回し線と電気的に導通させ、前記第２発光素子に対して、前記制御線を流れる電気信号又は前記制御回路内に設けられたノードを流れる電気信号を入力し、当該第２発光素子からの発光を検出して評価することにより、前記制御回路を検査することを特徴とする。 In addition, as a means for solving the above problems, a method for manufacturing a display device according to the present invention causes a display region, a frame region provided around the display region, and a first light emitting element provided in the display region to emit light. A method of manufacturing a display device for displaying an image, wherein a plurality of data lines to which a data signal for displaying the image is supplied and a plurality of control lines arranged to intersect the plurality of data lines Corresponding to the plurality of pixel circuits including the first light emitting elements provided at the intersections of the plurality of data lines and the plurality of control lines, and the timing at which the data signal is supplied to the data lines. A control circuit for activating a control line, a second light emitting element provided in the frame region for each control line, and a first transistor for turning on / off the light emission driving of the second light emitting element. The second light emitting element controls light emission when an electric signal flowing through the control line or an electric signal flowing through a node provided in the control circuit is input to a control terminal of the first transistor. A first conduction terminal of the transistor is connected to one of an anode and a cathode of the second light emitting element, and the second conduction terminal of the first transistor is connected to the first constant voltage via the end face of the display device. A second lead connected to a second constant voltage source via the end face of the display device, the other of the anode and the cathode of the second light emitting element being electrically connected to a first lead line connected to the source; An electrical signal that flows through the control line or an electrical signal that flows through a node provided in the control circuit is input to the second light emitting element. Detect luminescence By evaluating Te, characterized by inspecting said control circuit.
　さらに、前記第２発光素子からの発光を検出して評価した後、前記第１引き回し配線及び前記第２引き回し配線を前記端面において切断することとしても好ましい。 Further, it is also preferable that the first routing wiring and the second routing wiring are cut at the end face after detecting and evaluating light emission from the second light emitting element.
　さらにまた、前記第２発光素子と前記第１発光素子とは、同時に形成されることとしても好ましい。 Furthermore, it is also preferable that the second light emitting element and the first light emitting element are formed simultaneously.
　本発明によれば、検査対象となる制御線又は制御回路内に設けられたノードに対して直接プローブを接触させる必要がなく、非接触でのノードの検査を可能とする検査装置を実現することができる。これにより、制御線又はノードを構成する金属配線及び当該金属配線の表面を被覆する封止樹脂へのダメージ発生も解消することができ、接触型プローブによる検査工程に伴う二次不良の発生も防止することができる。また、薄型化に伴って柔軟性を有する基板上に構築される表示デバイスへの検査にも容易に対応させることができる。 According to the present invention, it is not necessary to directly contact a probe with a control line to be inspected or a node provided in a control circuit, and an inspection apparatus that enables non-contact inspection of a node is realized. Can do. As a result, it is possible to eliminate the occurrence of damage to the metal wiring constituting the control line or node and the sealing resin covering the surface of the metal wiring, and to prevent the occurrence of secondary defects in the inspection process using the contact probe. can do. In addition, it is possible to easily cope with inspection of a display device built on a flexible substrate as the thickness is reduced.
　また、表示デバイスの額縁領域に第２発光素子を駆動させるための定電圧源を形成する必要がなく、狭額縁化を実現することができる。一方、製造工程中においては引き回し線に接続された第１の定電圧源及び第２の定電圧源によって第２発光素子を安定に発光させることができ、信頼性の高い検査を実現することができる。 Further, it is not necessary to form a constant voltage source for driving the second light emitting element in the frame area of the display device, and a narrow frame can be realized. On the other hand, during the manufacturing process, the second light emitting element can emit light stably by the first constant voltage source and the second constant voltage source connected to the lead line, and a highly reliable inspection can be realized. it can.
　さらに、本発明によれば、表示デバイスの薄型化及び狭額縁化の両方を実現することができる。 Furthermore, according to the present invention, both thinning and narrowing of the display device can be realized.
第１発光素子６が画素回路５と共に画素４を構成してマトリクス状に配置されてなる表示領域３と、表示領域３への電気制御機能を有する制御回路１とを備える表示デバイス２の概略図を示す。Schematic diagram of a display device 2 including a display area 3 in which first light emitting elements 6 constitute pixels 4 together with a pixel circuit 5 and are arranged in a matrix, and a control circuit 1 having an electric control function for the display area 3. Indicates. 制御回路１が走査線回路である場合の回路構成の概略を示す。An outline of a circuit configuration when the control circuit 1 is a scanning line circuit is shown. 実施形態１における検査回路１０の回路構成を示す。1 shows a circuit configuration of a test circuit 10 according to a first embodiment. 実施形態１における検査回路１０のタイミングチャートを示す。2 is a timing chart of the inspection circuit 10 according to the first embodiment. ＧＤＭ領域周辺から分断端部２ａにかけて、表示デバイス２の断面構造の例を示す。An example of a cross-sectional structure of the display device 2 is shown from the periphery of the GDM region to the cut end 2a. 図５中の二点鎖線で囲われたトレンチ３３の構造の拡大図を示す。FIG. 6 shows an enlarged view of the structure of a trench 33 surrounded by a two-dot chain line in FIG. 5. デマルチプレクサＤＭの概略図を示す。1 shows a schematic diagram of a demultiplexer DM. （ａ）は、第１発光素子６周辺の断面例を示し、（ｂ）は、第２発光素子９周辺の断面例を示す。(A) shows a cross-sectional example around the first light-emitting element 6, and (b) shows a cross-sectional example around the second light-emitting element 9. 第１発光素子６の平面図（ａ）及び第２発光素子９の平面図（ｂ）を示す。The top view (a) of the 1st light emitting element 6 and the top view (b) of the 2nd light emitting element 9 are shown. 検出例１における検査回路１０の第２発光素子９から得られる期待波形(上段)と測定波形（下段）を示す。The expected waveform (upper stage) and measurement waveform (lower stage) obtained from the 2nd light emitting element 9 of the test | inspection circuit 10 in the example 1 of a detection are shown. 検出例２における検査回路１０の第２発光素子９から得られる期待波形(上段)と測定波形（下段）を示す。The expected waveform (upper stage) and measurement waveform (lower stage) obtained from the 2nd light emitting element 9 of the test | inspection circuit 10 in the example 2 of a detection are shown. 検出例３における検査回路１０の第２発光素子９から得られる期待波形(上段１組)と測定波形（下段）を示す。The expected waveform (1 set of upper stage) and measurement waveform (lower stage) obtained from the 2nd light emitting element 9 of the test | inspection circuit 10 in the example 3 of a detection are shown. 検出例４における検査回路１０の第２発光素子９から得られる期待波形(上段)と測定波形（下段）を示す。The expected waveform (upper stage) and measurement waveform (lower stage) obtained from the 2nd light emitting element 9 of the test | inspection circuit 10 in the example 4 of a detection are shown.
　以下、本発明に係る実施の形態を、図を参照しながら詳しく説明する。なお、本明細書及び図面において、実質的に同一の機能構成を有する構成要素については、同一の符号を付することにより重複説明を省略する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, in this specification and drawing, about the component which has the substantially same function structure, duplication description is abbreviate | omitted by attaching | subjecting the same code | symbol.
　図１には、上下方向に沿って配設された複数のデータ線Ｄａと、データ線Ｄａと交差するように配設された複数の制御線８との各交点において第１発光素子６が画素回路５と共に画素４が構成されてなる表示領域３を備える表示デバイス２の概略図を示す。 In FIG. 1, the first light emitting element 6 is a pixel at each intersection of a plurality of data lines Da arranged along the vertical direction and a plurality of control lines 8 arranged to intersect the data lines Da. 1 shows a schematic diagram of a display device 2 including a display region 3 in which a pixel 4 is configured together with a circuit 5. FIG.
　また、表示デバイス２には、表示領域３の周囲に設けられた額縁領域７に、制御線８と接続する制御回路１が設けられてなる。表示領域３は、画像コンテンツが表示される領域である。表示領域３の周縁よりも外側に設けられた額縁領域７は、画像コンテンツが表示される領域ではなく、表示デバイス２が製品化された際に枠体によって被覆することができる領域である。 Further, the display device 2 is provided with a control circuit 1 connected to the control line 8 in a frame area 7 provided around the display area 3. The display area 3 is an area where image content is displayed. The frame area 7 provided outside the periphery of the display area 3 is not an area in which image content is displayed, but an area that can be covered with a frame when the display device 2 is commercialized.
　制御回路１は、具体的には、走査線駆動回路、若しくはエミッションドライバのいずれであってもよい。また制御線８は、制御回路１が走査線駆動回路の場合には走査線として機能し、エミッションドライバの場合にはエミッション線として機能する。 Specifically, the control circuit 1 may be either a scanning line driving circuit or an emission driver. The control line 8 functions as a scanning line when the control circuit 1 is a scanning line driving circuit, and functions as an emission line when the control circuit 1 is an emission driver.
　制御回路１が走査線駆動回路、若しくはエミッションドライバである場合は、データ線Ｄａにデータ信号が供給されるタイミングで、対応する制御線８をアクティブにする制御機能が設けられる。制御線８は、制御回路１から表示領域３に向かって複数配設されてなる。本実施の形態においては、図１に示すように、表示デバイス２の下方から、制御線を、・・・制御線８（ｎ－１）、８（ｎ）、８（ｎ＋１）と区別して示すことがあり、また、合わせて制御線８ということがある。なお、ｎは整数を示す。 When the control circuit 1 is a scanning line drive circuit or an emission driver, a control function for activating the corresponding control line 8 at a timing when a data signal is supplied to the data line Da is provided. A plurality of control lines 8 are arranged from the control circuit 1 toward the display area 3. In the present embodiment, as shown in FIG. 1, the control lines are distinguished from the control lines 8 (n−1), 8 (n), and 8 (n + 1) from the lower side of the display device 2. In some cases, the control lines 8 may be collectively referred to. Note that n represents an integer.
　制御回路１が走査線駆動回路である場合の回路構成の例を図２に示す。 An example of a circuit configuration when the control circuit 1 is a scanning line driving circuit is shown in FIG.
　図２に示される走査線駆動回路は、制御線８（ｎ－１）からの信号によってオンされたトランジスタＴＡを介して、トランジスタＴＣの制御端子及び容量Ｃｂｓｔの一端に接続されたノードｎに信号が保持される。このノードｎに保持された信号によってトランジスタＴＣがオンされ、当該トランジスタＴＣの第１導通端子にクロック信号ＣＫＡの入力を受けて制御線８（ｎ）がアクティブとなる。なお、トランジスタＴＤは制御線８（ｎ）の電位を保持する。その後、トランジスタＴＤは、クロック信号ＣＫＡとは反転関係にあるクロック信号ＣＫＢによってオンされ、制御線８（ｎ）の電荷を低電位の電源ＶＳＳへ放電する。また、トランジスタＴＢは制御線８（ｎ）がアクティブになった所定期間経過後に、制御線８（ｎ＋１）からの信号によってオンされ、ノードｎに保持された信号に対応する電荷を低電位の電源ＶＳＳへ放電する。 The scanning line driving circuit shown in FIG. 2 sends a signal to the node n connected to the control terminal of the transistor TC and one end of the capacitor Cbst via the transistor TA turned on by the signal from the control line 8 (n−1). Is retained. The transistor TC is turned on by the signal held at the node n, and the control line 8 (n) is activated by receiving the input of the clock signal CKA at the first conduction terminal of the transistor TC. Note that the transistor TD holds the potential of the control line 8 (n). Thereafter, the transistor TD is turned on by the clock signal CKB in an inverted relationship with the clock signal CKA, and discharges the charge of the control line 8 (n) to the low-potential power supply VSS. The transistor TB is turned on by a signal from the control line 8 (n + 1) after a lapse of a predetermined period after the control line 8 (n) becomes active, and charges corresponding to the signal held at the node n are supplied to a low potential power source. Discharge to VSS.
　制御線８は、額縁領域７を経由して表示領域３に導入されてなる。額縁領域７には、制御線８又は制御回路１内に設けられたノードを流れる電気信号が入力されると発光可能に接続されてなる第２発光素子９が設けられて検査回路１０が構成されてなる。本実施の形態において、第１発光素子６及び第２発光素子９は有機ＥＬ素子とする。 The control line 8 is introduced into the display area 3 via the frame area 7. The frame area 7 is provided with a second light-emitting element 9 that is connected so as to be able to emit light when an electric signal flowing through a control line 8 or a node provided in the control circuit 1 is input to constitute an inspection circuit 10. It becomes. In the present embodiment, the first light emitting element 6 and the second light emitting element 9 are organic EL elements.
　また、表示領域３を取り囲むようにトレンチ３３が形成されてなる。トレンチ３３は、後述するように有機樹脂によって構成されてなる平坦化膜２４を浸入しようとする水分や酸素等を遮断し、表示領域３を構成する第１発光素子６の劣化を防止する機能を備える溝構造である。従って、第２発光素子９も図１に示すようにトレンチ３３の内側に設けることによって、第１発光素子６と同様に劣化を防止することができ、第２発光素子９の発光による検査をより確実に行うことができる。 Further, a trench 33 is formed so as to surround the display area 3. As will be described later, the trench 33 has a function of blocking moisture, oxygen, and the like from entering the planarizing film 24 made of an organic resin, and preventing deterioration of the first light emitting element 6 constituting the display region 3. It is a groove structure provided. Therefore, by providing the second light emitting element 9 also inside the trench 33 as shown in FIG. 1, it is possible to prevent the deterioration similarly to the first light emitting element 6, and the second light emitting element 9 can be inspected by light emission. It can be done reliably.
　第２発光素子９からの発光は、表示デバイス２の外部に設けた受光装置１１によって受光することができる。受光装置１１は、その内部に設けられた受光素子（図示せず）によって受光した光の強度を、時間に対してグラフに示すことができ、制御線８又は制御回路１内に設けられたノードを流れる電気信号との関係を比較することができる。なお、受光装置１１の上記受光素子にはフォトダイオードを用いることができる。 The light emitted from the second light emitting element 9 can be received by the light receiving device 11 provided outside the display device 2. The light receiving device 11 can show the intensity of light received by a light receiving element (not shown) provided therein in a graph with respect to time, and is provided in a node provided in the control line 8 or the control circuit 1. The relationship with the electrical signal flowing through the A photodiode can be used as the light receiving element of the light receiving device 11.
　以下、表示デバイス２の各実施形態について説明する。 Hereinafter, each embodiment of the display device 2 will be described.
　〔実施形態１〕
　（構造について）
　図３には、制御回路１が走査線駆動回路又はエミッションドライバである場合の実施形態１における検査回路１０の回路構成を示す。第２発光素子９の発光駆動をオン/オフする第１トランジスタとして、ＰＭＯＳのトランジスタＴ１が設けられてなる。実施形態１によれば、制御線８には、トランジスタＴ１の制御端子ｇ１が接続される。また、トランジスタＴ１の第２導通端子ｓ１は、表示デバイス２の分断端部２ａ（表示デバイス２の端面）まで配線されてなる第１引き回し配線Ｈ１と電気的に導通されてなる。 Embodiment 1
(About structure)
FIG. 3 shows a circuit configuration of the inspection circuit 10 according to the first embodiment when the control circuit 1 is a scanning line driving circuit or an emission driver. As a first transistor for turning on / off the light emission drive of the second light emitting element 9, a PMOS transistor T1 is provided. According to the first embodiment, the control terminal g1 of the transistor T1 is connected to the control line 8. Further, the second conduction terminal s1 of the transistor T1 is electrically connected to the first lead wiring H1 that is wired to the divided end portion 2a of the display device 2 (the end face of the display device 2).
　第１引き回し配線Ｈ１は、表示デバイス２の分断端部２ａを経由してさらに延伸し、表示領域３の画素４を駆動する第１の定電圧源である駆動電源ＥＬＶＤＤ（高電源電圧源）が接続される。 The first routing wiring H1 is further extended via the divided end portion 2a of the display device 2, and is a drive power supply ELVDD (high power supply voltage source) that is a first constant voltage source that drives the pixels 4 in the display region 3. Is connected.
　また、トランジスタＴ１の第１導通端子ｄ１に第２発光素子９のアノード９ａが接続されてなる。第２発光素子９のカソード９ｃは、表示デバイス２の分断端部２ａまで配線されてなる第２引き回し配線Ｈ２と電気的に導通されてなる。 Further, the anode 9a of the second light emitting element 9 is connected to the first conduction terminal d1 of the transistor T1. The cathode 9c of the second light emitting element 9 is electrically connected to the second lead wiring H2 that is wired to the divided end portion 2a of the display device 2.
　第２引き回し配線Ｈ２は、表示デバイス２の分断端部２ａを経由してさらに延伸し、第２の定電圧源であるカソード電源ＥＬＶＳＳ（低電源電圧源）に接続されてなる。実施形態１によれば、トランジスタＴ１をオンさせた状態において、制御回路１から出力された電流を第２発光素子９に流して発光させることができる。なお、駆動電源ＥＬＶＤＤ及びカソード電源ＥＬＶＳＳは、第１発光素子６の陽極側及び陰極側にそれぞれ接続されて（図示せず）、表示デバイス２の駆動時に第１発光素子６を発光駆動させる。また、上記の説明以外に、駆動電源ＥＬＶＤＤ及びカソード電源ＥＬＶＳＳとは異なる、独立した電力供給源としての高電源電圧源及び低電源電圧源を第２発光素子９にそれぞれ接続して、検査時に当該第２発光素子９の発光駆動を行う構成でもよい。 The second routing wiring H2 is further extended via the split end portion 2a of the display device 2 and connected to a cathode power supply ELVSS (low power supply voltage source) which is a second constant voltage source. According to the first embodiment, in a state where the transistor T1 is turned on, the current output from the control circuit 1 can be passed through the second light emitting element 9 to emit light. The drive power supply ELVDD and the cathode power supply ELVSS are respectively connected to the anode side and the cathode side of the first light emitting element 6 (not shown), and drive the first light emitting element 6 to emit light when the display device 2 is driven. In addition to the above description, a high power supply voltage source and a low power supply voltage source as independent power supply sources different from the drive power supply ELVDD and the cathode power supply ELVSS are connected to the second light emitting element 9 respectively, A configuration in which the second light emitting element 9 is driven to emit light may be used.
　また図３に示すように、第２発光素子９は、額縁領域７において表示領域３の左右方向外側に近接して設けられたＧＤＭ領域に設けられてなる。 As shown in FIG. 3, the second light emitting element 9 is provided in the GDM area provided in the frame area 7 in the vicinity of the outside in the left-right direction of the display area 3.
　さらに、第２発光素子９は、ＧＤＭ領域内において、表示領域３を取り囲むようにドット柄の網掛け領域で示されてなるトレンチ３３よりも内側に形成されてなる。 Furthermore, the second light emitting element 9 is formed inside the trench 33 formed by the dot-patterned shaded area so as to surround the display area 3 in the GDM area.
　（機能について）
　図４には、実施形態１における検査回路１０のタイミングチャートを示す。非検査期間ｔ２及び検査期間ｔ１にわたって、駆動電源ＥＬＶＤＤの電圧を＋４．６Ｖに維持すると共に、カソード電源ＥＬＶＳＳの電圧を－３．０Ｖに維持した。そして、検査期間ｔ１において、制御線８に対しては図４に示すような－８．０Ｖから＋５．０Ｖに変化する電圧を所定のタイミングでかけてトランジスタＴ１をオンとした。この場合、制御線８に電圧がかけられたタイミングで第２発光素子９から放射された光を受光装置１１で検出することによって制御回路１が正常に動作していることを判断することができる。さらに、非検査期間ｔ２においてはトランジスタＴ１をオフとすることによって駆動電源ＥＬＶＤＤから第２発光素子９への電流を遮断することができる。なお、受光装置１１には人の目を用いて第２発光素子９からの発光を視認することとしてもよい。 (About functions)
FIG. 4 shows a timing chart of the inspection circuit 10 in the first embodiment. Over the non-inspection period t2 and the inspection period t1, the voltage of the drive power supply ELVDD was maintained at + 4.6V, and the voltage of the cathode power supply ELVSS was maintained at −3.0V. In the inspection period t1, the transistor T1 is turned on by applying a voltage that changes from −8.0 V to +5.0 V as shown in FIG. In this case, it is possible to determine that the control circuit 1 is operating normally by detecting the light emitted from the second light emitting element 9 with the light receiving device 11 at the timing when the voltage is applied to the control line 8. . Further, in the non-inspection period t2, the current from the drive power supply ELVDD to the second light emitting element 9 can be cut off by turning off the transistor T1. The light receiving device 11 may visually recognize the light emitted from the second light emitting element 9 using human eyes.
　実施形態１によれば、検査期間ｔ１において第２発光素子９を発光させることに伴う制御線８の電圧降下を生じさせることがないという利点がある。また、駆動電源ＥＬＶＤＤ及びカソード電源ＥＬＶＳＳを電力供給源とすることで、独立した電力供給源を設ける場合と比較して回路構成を簡単とすることができる。 According to the first embodiment, there is an advantage that the voltage drop of the control line 8 caused by causing the second light emitting element 9 to emit light in the inspection period t1 does not occur. Further, by using the drive power supply ELVDD and the cathode power supply ELVSS as power supply sources, the circuit configuration can be simplified as compared with the case where an independent power supply source is provided.
　実施形態１によれば、駆動電源ＥＬＶＤＤから少なくとも検査期間ｔ１中において電流供給を継続的に行っておき、制御回路１から出力された電圧によってトランジスタＴ１をオンさせることによって、駆動電源ＥＬＶＤＤからの電流を第２発光素子９に流して発光させることができる。 According to the first embodiment, current supply from the drive power supply ELVDD is continuously performed at least during the inspection period t1, and the transistor T1 is turned on by the voltage output from the control circuit 1, whereby the current from the drive power supply ELVDD is turned on. Can be caused to flow through the second light emitting element 9 to emit light.
　（トレンチ３３の構造について）
　ここで、トレンチ３３の構造を図５の表示デバイス２の一部における断面図を参照しながら説明する。 (Regarding the structure of the trench 33)
Here, the structure of the trench 33 will be described with reference to a cross-sectional view of a part of the display device 2 of FIG.
　図５は、トップエミッション型の発光素子を構成する構造の例が示されている。下側から順に、基材１２、樹脂層１３、バリア層１４（ベースコート層）が形成されてなる。この上にデータ線Ｄａ及び制御線８が設けられ、その上には平坦化膜２４が設けられてなる。平坦化膜２４の下側にはトランジスタＴ１が形成されてなる。また、平坦化膜２４上には第１発光素子６及び第２発光素子９が設けられてなる。なお、トランジスタＴ１が設けられてなる層には無機絶縁膜２１、２２、２３が形成されてなる。 FIG. 5 shows an example of a structure constituting a top emission type light emitting element. A base material 12, a resin layer 13, and a barrier layer 14 (base coat layer) are formed in order from the lower side. A data line Da and a control line 8 are provided thereon, and a planarizing film 24 is provided thereon. A transistor T1 is formed below the planarizing film 24. Further, the first light emitting element 6 and the second light emitting element 9 are provided on the planarizing film 24. Note that inorganic insulating films 21, 22, and 23 are formed on the layer provided with the transistor T1.
　平坦化膜２４上には、第１発光素子を駆動するために設けられた第１電極であるアノード電極２５、及び第２電極であるカソード電極２８が設けられてなり、アノード電極２５及びカソード電極２８の間には、機能層として発光層２７が設けられてなる。また、カソード電極２８上には、カソード電極２８を覆う無機封止膜２９が設けられてなる。さらに、無機封止膜２９上には、封止層１７及び機能フィルム１９が設けられてなる。 On the planarizing film 24, an anode electrode 25 as a first electrode and a cathode electrode 28 as a second electrode are provided to drive the first light emitting element, and the anode electrode 25 and the cathode electrode are provided. 28 is provided with a light emitting layer 27 as a functional layer. An inorganic sealing film 29 that covers the cathode electrode 28 is provided on the cathode electrode 28. Further, the sealing layer 17 and the functional film 19 are provided on the inorganic sealing film 29.
　図５中の二点鎖線からなる楕円内の構造の拡大図を図６に示す。トレンチ３３は、平坦化膜２４を封止層１７側から貫通する溝形状に形成されてなる。トレンチ３３の内面は、カソード電極２８と、アノード電極２５と同層で同一材料によって形成された金属層２５ａによって覆われ、且つ金属層２５ａとカソード電極２８はトレンチ３３の内部で互いに接触してなる。 FIG. 6 shows an enlarged view of the structure inside the ellipse consisting of the two-dot chain line in FIG. The trench 33 is formed in a groove shape penetrating the planarizing film 24 from the sealing layer 17 side. The inner surface of the trench 33 is covered with a cathode layer 28 and a metal layer 25a formed of the same material as the anode electrode 25, and the metal layer 25a and the cathode electrode 28 are in contact with each other inside the trench 33. .
　トレンチ３３は、有機樹脂によって構成されてなる平坦化膜２４を浸入しようとする水分や酸素等を遮断し、表示領域３を構成する第１発光素子６の劣化を防止する。従って、第２発光素子９もトレンチ３３の内側に設けることによって、第１発光素子６と同様に劣化を防止することができ、第２発光素子９の発光による検査をより確実に行うことができる。 The trench 33 blocks moisture, oxygen, and the like from entering the planarizing film 24 made of an organic resin, and prevents the first light emitting element 6 constituting the display region 3 from deteriorating. Therefore, by providing the second light emitting element 9 also inside the trench 33, it is possible to prevent the deterioration as in the case of the first light emitting element 6, and the inspection by the light emission of the second light emitting element 9 can be more reliably performed. .
　（分断端部２ａ付近の構造について）
　また、図５にはトランジスタＴ１の第２導通端子ｓ１と導通し、表示デバイス２の分断端部２ａまで配線されてなる第１引き回し配線Ｈ１の例を示す。 (About the structure in the vicinity of the split end 2a)
FIG. 5 shows an example of the first routing wiring H1 that is electrically connected to the second conduction terminal s1 of the transistor T1 and is wired to the dividing end 2a of the display device 2.
　図５の例によれば、第１引き回し配線Ｈ１はＨ１ａ、Ｈ１ｂ、Ｈ１ｃ、及びＨ１ｍによって構成されてなる。第１引き回し配線Ｈ１は、ソースレイヤに形成された第１引き回し配線Ｈ１ａからゲートレイヤに形成された第１引き回し配線Ｈ１ｂに繋ぎかえられてＧＤＭ領域を超えて延出する。さらに、第１引き回し配線Ｈ１ｂから再度ソースレイヤに形成された第１引き回し配線Ｈ１ｃに繋ぎかえられる。第１引き回し配線Ｈ１ｃは、表示デバイス２の分断端部２ａ付近で導体化された半導体からなる第１引き回し配線Ｈ１ｍに繋ぎかえられて分断端部２ａに到達する。なお、第１引き回し配線Ｈ１ａ、Ｈ１ｂ、及びＨ１ｃは金属層からなる。また、第２発光素子９のカソード９ｃに導通されてなる第２引き回し配線も同様に分断端部２ａに到達される。 According to the example of FIG. 5, the first routing wiring H1 is composed of H1a, H1b, H1c, and H1m. The first routing wiring H1 extends from the first routing wiring H1a formed in the source layer to the first routing wiring H1b formed in the gate layer and extends beyond the GDM region. Furthermore, the first routing wiring H1b is connected again to the first routing wiring H1c formed in the source layer. The first routing wiring H1c is connected to the first routing wiring H1m made of a semiconductor made into a conductor in the vicinity of the split end portion 2a of the display device 2, and reaches the split end portion 2a. The first routing wirings H1a, H1b, and H1c are made of a metal layer. Similarly, the second routing wiring that is conducted to the cathode 9c of the second light emitting element 9 also reaches the divided end portion 2a.
　図５は、第１引き回し配線Ｈ１及び第２引き回し配線Ｈ２は、第２発光素子９からの発光を検出して検査工程を終えた後、分断端部２ａで切断されて駆動電源ＥＬＶＤＤ及びカソード電源ＥＬＶＳＳから切断された状態を示す。 In FIG. 5, the first routing wiring H1 and the second routing wiring H2 are detected by the light emission from the second light emitting element 9 and finished the inspection process, and then cut at the dividing end portion 2a to drive the power supply ELVDD and the cathode. The state disconnected from the power source ELVSS is shown.
　引き回し配線Ｈ１，Ｈ２の切断面は、導体化された半導体層で形成されてなるため、切断面において金属層が腐食して、表示領域３の信頼性低下を防ぐことができる。 Since the cut surfaces of the routing wirings H1 and H2 are formed of a conductor semiconductor layer, the metal layer is corroded on the cut surface, and the reliability of the display region 3 can be prevented from being lowered.
　〔実施形態２〕
　他の実施形態として、第２発光素子９が、図１に示すように、データ線Ｄａと交差する表示領域３の辺の外側に設けられても好ましい。この場合、第２発光素子９はデータ線Ｄａ毎に額縁領域７に設けられる。またデータ線Ｄａには、データ信号を供給するデータ線駆動回路１００が接続されてなる。データ線Ｄａ毎に設けられた第２発光素子９は、データ線Ｄａを流れる電気信号又はデータ線駆動回路１００内に設けられたノードを流れる電気信号が、データ線Ｄａ毎に接続されるトランジスタＴ１の制御端子に入力されることにより発光が制御される。 [Embodiment 2]
As another embodiment, it is preferable that the second light emitting element 9 is provided outside the side of the display area 3 intersecting with the data line Da as shown in FIG. In this case, the second light emitting element 9 is provided in the frame area 7 for each data line Da. The data line Da is connected to a data line driving circuit 100 that supplies a data signal. The second light emitting element 9 provided for each data line Da includes a transistor T1 in which an electric signal flowing through the data line Da or an electric signal flowing through a node provided in the data line driving circuit 100 is connected to each data line Da. The light emission is controlled by being input to the control terminal.
　さらに、データ線駆動回路１００は、デマルチプレクサＤＭを含むものであっても好ましい。 Furthermore, it is preferable that the data line driving circuit 100 includes a demultiplexer DM.
　ここで、図７にデマルチプレクサＤＭの構造の概略を示す。デマルチプレクサＤＭは、１つの信号を入力として受け取り、複数の信号に分割して出力する機能を発揮する装置である。図７に示す構造を例にとって説明する。図７において、下方を向く矢印方向が表示領域３となる。データ線Ｄａ１は、Ｄｍ１で示された領域に配置された２つのトランジスタの導通端子にそれぞれ分岐して接続されてなる。Ｄｍ１内に２つのトランジスタは、スイッチ信号線ＡＳＷ１、及びＡＳＷ２から入力される信号によってオン/オフが制御される。そして、データ線Ｄａ１からＤｍ１内に入力されたデータ信号を、データ線Ｄａ１１若しくはデータ線Ｄａ１２に振り分けて出力することができる。また同様に、データ線Ｄａ２，Ｄａ３においても、データ線Ｄａ１と共通のスイッチ信号線ＡＳＷ１、及びＡＳＷ２から入力される信号によって、データ信号をデータ線Ｄａ２１，Ｄａ２２，及びデータ線Ｄａ３１，Ｄａ３２に振り分けることができる。図７に示す場合、第２発光素子９及びトランジスタＴ１からなる検査回路１０は、データ線Ｄａ１１，Ｄａ１２，Ｄａ２１，Ｄａ２２，Ｄａ３１，及びＤａ３２に、それぞれ接続することが可能である。また、データ線駆動回路１００、例えばデマルチプレクサＤＭ内に設けられたノードに、検査回路１０を接続してもよい。 Here, FIG. 7 shows an outline of the structure of the demultiplexer DM. The demultiplexer DM is a device that exhibits a function of receiving one signal as an input, dividing it into a plurality of signals, and outputting it. The structure shown in FIG. 7 will be described as an example. In FIG. 7, the arrow direction pointing downward is the display area 3. The data line Da1 is branched and connected to the conduction terminals of the two transistors arranged in the region indicated by Dm1. The two transistors in Dm1 are on / off controlled by signals input from the switch signal lines ASW1 and ASW2. Then, the data signal input from the data line Da1 to Dm1 can be distributed to the data line Da11 or the data line Da12 and output. Similarly, in the data lines Da2 and Da3, the data signals are distributed to the data lines Da21 and Da22 and the data lines Da31 and Da32 by signals input from the switch signal lines ASW1 and ASW2 common to the data line Da1. Can do. In the case shown in FIG. 7, the inspection circuit 10 including the second light emitting element 9 and the transistor T1 can be connected to the data lines Da11, Da12, Da21, Da22, Da31, and Da32. Further, the inspection circuit 10 may be connected to a node provided in the data line driving circuit 100, for example, the demultiplexer DM.
　実施形態２に示すように、第２発光素子９がデータ線Ｄａに接続されてなる場合であっても、検査回路１０は実施形態１の場合と同様の構造を備える（図３のかっこ書の符号を参照）。すなわち、図３に示すように、データ線ＤａはトランジスタＴ１の制御端子ｇ１に接続され、トランジスタＴ１の第２導通端子ｓ１は、表示デバイス２の分断端部２ａまで配線されてなる第１引き回し配線Ｈ１と電気的に導通されてなる。また第１引き回し配線Ｈ１は、表示デバイス２の分断端部２ａを経由してさらに延伸し、表示領域３の画素４を駆動する第１の定電圧源である駆動電源ＥＬＶＤＤが接続される。 As shown in the second embodiment, even when the second light emitting element 9 is connected to the data line Da, the inspection circuit 10 has the same structure as that in the first embodiment (see the parenthesis in FIG. 3). See the sign). That is, as shown in FIG. 3, the data line Da is connected to the control terminal g1 of the transistor T1, and the second conduction terminal s1 of the transistor T1 is wired to the dividing end 2a of the display device 2. It is electrically connected to the wiring H1. Further, the first routing wiring H1 is further extended through the divided end portion 2a of the display device 2, and is connected to a driving power source ELVDD that is a first constant voltage source for driving the pixels 4 in the display region 3.
　また、トランジスタＴ１の第１導通端子ｄ１に第２発光素子９のアノード９ａが接続されてなり、第２発光素子９のカソード９ｃは、表示デバイス２の分断端部２ａまで配線されてなる第２引き回し配線Ｈ２と電気的に導通されてなる構造も実施形態１の場合と同様である。また、第２引き回し配線Ｈ２は、表示デバイス２の分断端部２ａを経由してさらに延伸し、第２の定電圧源であるカソード電源ＥＬＶＳＳに接続されてなる。 Further, the anode 9a of the second light emitting element 9 is connected to the first conduction terminal d1 of the transistor T1, and the cathode 9c of the second light emitting element 9 is wired to the dividing end 2a of the display device 2. The structure that is electrically connected to the two routing wirings H2 is the same as that in the first embodiment. Further, the second lead wiring H2 is further extended via the divided end portion 2a of the display device 2, and is connected to the cathode power source ELVSS which is the second constant voltage source.
　そして、実施形態２における第１引き回し配線Ｈ１及び第２引き回し配線Ｈ２も、第２発光素子９からの発光を検出して検査工程を終えた後、分断端部２ａで切断されて駆動電源ＥＬＶＤＤ及びカソード電源ＥＬＶＳＳから切断される。 Then, the first routing wiring H1 and the second routing wiring H2 in the second embodiment are also cut by the dividing end portion 2a after detecting the light emission from the second light emitting element 9 and finishing the inspection process, and the driving power supply ELVDD. And the cathode power supply ELVSS.
　引き回し配線Ｈ１，Ｈ２の切断面は、導体化された半導体層で形成されてなるため、切断面において金属層が腐食して、表示領域３の信頼性低下を防ぐことができる。 Since the cut surfaces of the routing wirings H1 and H2 are formed of a conductor semiconductor layer, the metal layer is corroded on the cut surface, and the reliability of the display region 3 can be prevented from being lowered.
　＜第２発光素子９の構造について＞
　第２発光素子９は、額縁領域７において、表示領域３に形成される第１発光素子とは明確に区別して形成して配置することができる。また、第１発光素子を含む画素４によって構成される表示領域３を形成する際に、表示領域３の外縁のわずか外側に形成されるダミー画素に含まれる発光素子を、第２発光素子として用いることもできる。つまり、第１発光素子と第２発光素子とは、同時に形成されている。 <About Structure of Second Light-Emitting Element 9>
The second light emitting element 9 can be formed and arranged in the frame region 7 so as to be clearly distinguished from the first light emitting element formed in the display region 3. Further, when forming the display region 3 constituted by the pixels 4 including the first light emitting elements, the light emitting elements included in the dummy pixels formed slightly outside the outer edge of the display region 3 are used as the second light emitting elements. You can also That is, the first light emitting element and the second light emitting element are formed simultaneously.
　図８の（ａ）は、第１発光素子６の１つの発光色を示すサブ画素ＳＰＡの周辺の断面例を示し、図８の（ｂ）は、第２発光素子９として１つの発光色を示すサブ画素ＳＰＢの周辺の断面例を示す。図８（ａ）、（ｂ）に示される発光素子は上方に向けて発光するトップエミッション型であり、下側から順に、基材１２、樹脂層１３、バリア層１４（ベースコート層）、ＴＦＴ層１５、発光素子層１６、封止層１７、接着層１８及び機能フィルム１９を備える。 FIG. 8A shows an example of a cross section around the sub-pixel SPA showing one emission color of the first light emitting element 6, and FIG. 8B shows one emission color as the second light emitting element 9. An example of a cross section around the subpixel SPB shown is shown. The light emitting elements shown in FIGS. 8A and 8B are top emission types that emit light upward, and in order from the bottom, a base material 12, a resin layer 13, a barrier layer 14 (base coat layer), and a TFT layer. 15, a light emitting element layer 16, a sealing layer 17, an adhesive layer 18 and a functional film 19.
　ＴＦＴ層１５は、半導体膜２０と、半導体膜２０よりも上層に形成される無機絶縁膜２１と、無機絶縁膜２１よりも上層に形成されるゲート電極Ｇと、ゲート電極Ｇよりも上層に形成される無機絶縁膜２２と、無機絶縁膜２２よりも上層に形成される容量電極Ｃと、容量電極Ｃよりも上層に形成される無機絶縁膜２３と、無機絶縁膜２３よりも上層に形成される、ソース電極Ｓ及びドレイン電極Ｄと、ソース電極Ｓ及びドレイン電極Ｄよりも上層に形成される平坦化膜２４とを含む。 The TFT layer 15 is formed on the semiconductor film 20, the inorganic insulating film 21 formed above the semiconductor film 20, the gate electrode G formed above the inorganic insulating film 21, and the layer above the gate electrode G. The inorganic insulating film 22 is formed; the capacitive electrode C formed above the inorganic insulating film 22; the inorganic insulating film 23 formed above the capacitive electrode C; and the upper layer than the inorganic insulating film 23. A source electrode S and a drain electrode D, and a planarizing film 24 formed in an upper layer than the source electrode S and the drain electrode D.
　半導体膜２０、無機絶縁膜２１（ゲート絶縁膜）、ゲート電極Ｇを含むように薄膜トランジスタＴｒ（発光制御トランジスタ）が構成される。ソース電極Ｓは半導体膜２０のソース領域に接続され、ドレイン電極Ｄは半導体膜２０のドレイン領域に接続される。 A thin film transistor Tr (light emission control transistor) is configured to include the semiconductor film 20, the inorganic insulating film 21 (gate insulating film), and the gate electrode G. The source electrode S is connected to the source region of the semiconductor film 20, and the drain electrode D is connected to the drain region of the semiconductor film 20.
　半導体膜２０は、例えば低温ポリシリコン（ＬＴＰＳ）あるいは酸化物半導体で構成される。図８では、半導体膜２０をチャネルとするＴＦＴがトップゲート構造で示されている。 The semiconductor film 20 is made of, for example, low-temperature polysilicon (LTPS) or an oxide semiconductor. In FIG. 8, the TFT having the semiconductor film 20 as a channel is shown in a top gate structure.
　発光素子層１６は本実施の形態においては有機発光ダイオード層であり、平坦化膜２４よりも上層に形成されるアノード電極２５と、アクティブ領域（発光素子層１６と重なる領域）のサブ画素ＳＰＡまたはＳＰＢを規定する平坦化膜であるエッジカバー２６と、アノード電極２５よりも上層に形成される発光層２７と、発光層２７よりも上層に形成されるカソード電極２８とを含む。アノード電極２５、発光層２７、及びカソード電極２８を含むように、有機発光ダイオード（ＯＬＥＤ）が構成される。 The light emitting element layer 16 is an organic light emitting diode layer in the present embodiment, and the anode electrode 25 formed above the planarizing film 24 and the subpixel SPA in the active region (the region overlapping the light emitting element layer 16) or It includes an edge cover 26 that is a planarizing film that defines SPB, a light emitting layer 27 formed above the anode electrode 25, and a cathode electrode 28 formed above the light emitting layer 27. An organic light emitting diode (OLED) is configured to include the anode electrode 25, the light emitting layer 27, and the cathode electrode 28.
　エッジカバー２６は、アノード電極２５の端部を囲っている。発光層２７は、蒸着法あるいはインクジェット法によって、エッジカバー２６で囲まれた領域に形成される。 The edge cover 26 surrounds the end of the anode electrode 25. The light emitting layer 27 is formed in a region surrounded by the edge cover 26 by an evaporation method or an ink jet method.
　アノード電極２５は、例えばＩＴＯ（Ｉｎｄｉｕｍ　Ｔｉｎ　Ｏｘｉｄｅ）とＡｇを含む合金との積層によって構成され、光反射性を有する。カソード電極２８は、ＩＴＯ、ＩＺＯ（Ｉｎｄｉｕｍ　Ｚｉｎｃ　Ｏｘｉｄｅ）等の透光性の導電材で構成することができる。 The anode electrode 25 is composed of, for example, a laminate of ITO (Indium Tin Oxide) and an alloy containing Ag, and has light reflectivity. The cathode electrode 28 can be made of a light-transmitting conductive material such as ITO or IZO (Indium Zinc Oxide).
　カソード電極２８が透光性であり、アノード電極２５が光反射性であるため、発光層２７から放出された光は上方に向かい、トップエミッションとなる。 Since the cathode electrode 28 is translucent and the anode electrode 25 is light reflective, the light emitted from the light emitting layer 27 is directed upward and becomes top emission.
　封止層１７は透光性であり、カソード電極２８を覆う無機封止膜２９と、無機封止膜２９よりも上層に形成される有機封止膜３０と、有機封止膜３０を覆う有機封止膜３１とを含む。封止層１７は、発光素子層１６を覆い、水、酸素等の異物の発光素子層１６への浸透を防いでいる。機能フィルム１９は、例えば、光学補償機能、タッチセンサ機能、保護機能等を有する。 The sealing layer 17 is translucent, and includes an inorganic sealing film 29 that covers the cathode electrode 28, an organic sealing film 30 that is formed above the inorganic sealing film 29, and an organic that covers the organic sealing film 30. And a sealing film 31. The sealing layer 17 covers the light emitting element layer 16 and prevents penetration of foreign substances such as water and oxygen into the light emitting element layer 16. The functional film 19 has, for example, an optical compensation function, a touch sensor function, a protection function, and the like.
　（サブ画素ＳＰＡ及びＳＰＢの構造例）
　図９は、サブ画素ＳＰＡ及びＳＰＢの構造例を示す平面図である。図８の（ａ）及び図９の（ａ）に示すように、サブ画素ＳＰＡは、開口ＨＡを有するエッジカバー２６と、エッジカバー２６よりも上層に配置される発光層２７とを少なくとも備えている。サブ画素ＳＰＡにおいて、開口ＨＡの周囲のすべてをエッジカバー２６が囲っている。発光層２７は、少なくとも開口ＨＡを完全に充填するように形成されている。発光層２７の面積は、開口ＨＡの面積よりも大きい。発光層２７のうち開口ＨＡに重畳する範囲が、第１発光素子６の発光に寄与する。 (Structural example of subpixels SPA and SPB)
FIG. 9 is a plan view showing a structural example of the sub-pixels SPA and SPB. As shown in FIGS. 8A and 9A, the sub-pixel SPA includes at least an edge cover 26 having an opening HA and a light emitting layer 27 disposed above the edge cover 26. Yes. In the sub-pixel SPA, the edge cover 26 surrounds the entire periphery of the opening HA. The light emitting layer 27 is formed so as to completely fill at least the opening HA. The area of the light emitting layer 27 is larger than the area of the opening HA. A range of the light emitting layer 27 that overlaps the opening HA contributes to light emission of the first light emitting element 6.
　図８の（ｂ）及び図９の（ｂ）に示すように、サブ画素ＳＰＢは開口ＨＢを有するエッジカバー２６と、エッジカバー２６よりも上層に配置され、かつサブ画素ＳＰＡの発光層２７と同一の形状かつ同一の大きさの発光層２７とを少なくとも備えている。サブ画素ＳＰＢにおいて、開口ＨＢの周囲のすべてをエッジカバー２６が囲っている。発光層２７は、少なくとも開口ＨＢを完全に充填するように形成されている。発光層２７の面積は、開口ＨＢの面積よりも大きい。発光層２７のうち開口ＨＢに重畳する範囲が、第２発光素子９の発光に寄与する。また、このように、第１発光素子６の発光層２７のエッジカバー２６の開口ＨＡは、第２発光素子９の発光層２７のエッジカバー２６の開口ＨＢよりも大きい。これにより、蒸着マスクの端の方で蒸着される第２発光素子９の発光層２７に蒸着ずれが生じても、このように、第２発光素子９の発光層２７のエッジカバー２６の開口ＨＢを小さくすることで、当該エッジカバー２６の開口ＨＢを覆うように発光層２７を形成でき、所望の発光領域で確実に発光させることが可能となる。 As shown in FIG. 8B and FIG. 9B, the sub-pixel SPB has an edge cover 26 having an opening HB, an upper layer than the edge cover 26, and a light-emitting layer 27 of the sub-pixel SPA. At least a light emitting layer 27 having the same shape and the same size is provided. In the sub-pixel SPB, the edge cover 26 surrounds the entire periphery of the opening HB. The light emitting layer 27 is formed so as to completely fill at least the opening HB. The area of the light emitting layer 27 is larger than the area of the opening HB. A range of the light emitting layer 27 that overlaps the opening HB contributes to light emission of the second light emitting element 9. As described above, the opening HA of the edge cover 26 of the light emitting layer 27 of the first light emitting element 6 is larger than the opening HB of the edge cover 26 of the light emitting layer 27 of the second light emitting element 9. As a result, even if a vapor deposition shift occurs in the light emitting layer 27 of the second light emitting element 9 deposited near the end of the vapor deposition mask, the opening HB of the edge cover 26 of the light emitting layer 27 of the second light emitting element 9 is thus obtained. The light emitting layer 27 can be formed so as to cover the opening HB of the edge cover 26, and light can be reliably emitted in a desired light emitting region.
　なお、上記の説明以外に、例えば、蒸着マスクの端の方ではなく中央部側の部分で第２発光素子９を形成したり、第１発光素子６とは別の蒸着マスクを用いて第２発光素子９を形成したりした場合には、第１発光素子６の発光面積と第２発光素子９の発光面積とを同じ大きさとした構成でもよい。 In addition to the above description, for example, the second light-emitting element 9 is formed in the central portion side instead of the end of the vapor deposition mask, or the second light-emitting element 6 is used by using a vapor deposition mask different from the first light-emitting element 6. When the light emitting element 9 is formed, the light emitting area of the first light emitting element 6 and the light emitting area of the second light emitting element 9 may be the same size.
　上述した「同一の形状及び大きさ」とは、発光層２７の発光材料を同一の形状かつ同一の大きさのマスクパターンを有するマスクを用いて表示領域３及び表示領域３の外縁領域に蒸着した場合に、同一の形状かつ同一の大きさの発光層２７が表示領域３及び表示領域３の外縁領域（以下、ダミー領域という。）に結果的に形成されることを意味する。従って、蒸着技術を使用するにあたり、同一の大きさのマスクパターンを有するマスクを用いたとしてもサブ画素ＳＰＡの発光層２７とサブ画素ＳＰＢの発光層２７とは、必ずしも完全に同一の形状かつ同一の大きさには形成されない場合も含まれる。 The above-mentioned “same shape and size” means that the light emitting material of the light emitting layer 27 is deposited on the display region 3 and the outer edge region of the display region 3 using a mask having the same shape and the same size mask pattern. In this case, it means that the light emitting layer 27 having the same shape and the same size is formed as a result in the display area 3 and the outer edge area of the display area 3 (hereinafter referred to as a dummy area). Therefore, when using the vapor deposition technique, even if a mask having the same size mask pattern is used, the light emitting layer 27 of the subpixel SPA and the light emitting layer 27 of the subpixel SPB are not necessarily completely the same shape and the same. The case where the size is not formed is also included.
　なお、ダミー領域７ａは、表示領域３を形成する際に一つのマスクを用いて形成されるが、図１の一点鎖線に示すように画像コンテンツが表示される領域のわずかに外側に形成されるため、本発明において額縁領域７に属する。また、ダミー領域７ａに形成される画素をダミー画素という。ダミー画素を構成する発光素子は、第１発光素子６と同時に形成することができ、第２発光素子９とすることができる。 The dummy area 7a is formed using one mask when the display area 3 is formed. However, the dummy area 7a is formed slightly outside the area where the image content is displayed, as shown by a one-dot chain line in FIG. Therefore, it belongs to the frame area 7 in the present invention. The pixels formed in the dummy area 7a are referred to as dummy pixels. The light emitting elements constituting the dummy pixels can be formed at the same time as the first light emitting element 6, and can be the second light emitting element 9.
　図９に示すように、表示領域３に形成されるアノード電極２５の内方を開口する開口ＨＡは、ダミー領域７ａに形成されるアノード電極２５の内方を開口する開口ＨＢよりも大きい。さらに、表示領域３に形成される発光層２７は、ダミー領域７ａに形成される発光層２７と同一の形状かつ同一の大きさを有する。 As shown in FIG. 9, the opening HA opening the inner side of the anode electrode 25 formed in the display area 3 is larger than the opening HB opening the inner side of the anode electrode 25 formed in the dummy area 7a. Further, the light emitting layer 27 formed in the display region 3 has the same shape and the same size as the light emitting layer 27 formed in the dummy region 7a.
　開口ＨＢが開口ＨＡよりも小さいので、ダミー領域７ａに発光材料を蒸着させる際の蒸着パターンの精度が低かったとしても、発光層２７はダミー領域７ａにおいて開口ＨＢを完全に覆うように形成される。従って、正常に機能するサブ画素ＳＰＢを、ダミー領域７ａに形成することができる。 Since the opening HB is smaller than the opening HA, the light emitting layer 27 is formed so as to completely cover the opening HB in the dummy region 7a even if the accuracy of the vapor deposition pattern when the light emitting material is deposited on the dummy region 7a is low. . Therefore, the normally functioning sub-pixel SPB can be formed in the dummy region 7a.
　表示領域３では、発光層２７を充分に発光させるために、発光層２７のうち開口ＨＡに充填された箇所に重畳するように、コンタクトホールを設けることができない。そのため表示領域３では、図８の（ａ）に示すように、薄膜トランジスタＴｒのコンタクトホールは、開口ＨＡと重畳しない位置に形成されている。同様に、容量電極Ｃのコンタクトホールも、開口ＨＡと重畳しない位置に形成されている。 In the display area 3, in order to cause the light emitting layer 27 to emit light sufficiently, a contact hole cannot be provided so as to overlap with a portion of the light emitting layer 27 filled in the opening HA. Therefore, in the display region 3, as shown in FIG. 8A, the contact hole of the thin film transistor Tr is formed at a position that does not overlap with the opening HA. Similarly, the contact hole of the capacitor electrode C is also formed at a position that does not overlap with the opening HA.
　ダミー領域７ａでは、発光層２７のうち開口ＨＢに重畳しない箇所は、有効な発光層２７として機能しない。そのためダミー領域７ａでは、図８の（ｂ）に示すように、薄膜トランジスタＴｒのコンタクトホールを、発光層２７のうち開口ＨＢに重畳しない箇所（表示領域３では開口ＨＡに重畳する箇所）に形成することができる。同様に、容量電極Ｃのコンタクトホールも、発光層２７のうち開口ＨＢに重畳しない箇所に形成することができる。これにより、ダミー領域７ａでは、薄膜トランジスタＴｒ及び容量電極Ｃをいずれも開口ＨＢにより近づけて設けることができる。このように、ダミー画素を構成する発光素子を第２発光素子９に用いるとともに、ダミー領域７ａ内に検査回路１０を設置しているので、第２発光素子９及び検査回路１０を形成するために特別なスペースを必要とせず、表示デバイス２の狭額縁化を容易にはかることができる。また、領域３２を他の回路配置スペースとして活用することもできる。 In the dummy region 7a, a portion of the light emitting layer 27 that does not overlap the opening HB does not function as an effective light emitting layer 27. Therefore, in the dummy region 7a, as shown in FIG. 8B, the contact hole of the thin film transistor Tr is formed in a portion of the light emitting layer 27 that does not overlap the opening HB (a portion that overlaps the opening HA in the display region 3). be able to. Similarly, the contact hole of the capacitor electrode C can also be formed in a portion of the light emitting layer 27 that does not overlap the opening HB. Thereby, in the dummy region 7a, both the thin film transistor Tr and the capacitor electrode C can be provided closer to the opening HB. As described above, since the light emitting elements constituting the dummy pixels are used for the second light emitting elements 9 and the inspection circuit 10 is provided in the dummy region 7a, the second light emitting elements 9 and the inspection circuit 10 are formed. No special space is required, and the display device 2 can be easily narrowed. Further, the region 32 can be used as another circuit arrangement space.
　また、複数の制御線８（ｎ－１）、制御線８（ｎ）、制御線８（ｎ＋１）・・・にそれぞれ設けられた複数の第２発光素子９は、互いに異なる色を発光する複数種類の発光素子に形成されてもよい。 Further, the plurality of second light emitting elements 9 respectively provided on the plurality of control lines 8 (n−1), the control lines 8 (n), the control lines 8 (n + 1),. You may form in a light emitting element of a kind.
　＜制御線若しくは制御回路内のノードの不良検出例＞
　〔検出例１〕
　本発明によれば、制御回路１の出力、もしくは制御回路１の内部ノードとして、例えば図２の内部ノードｎの電位を測定し、制御線８から第２発光素子９に入力された信号に基づいて期待される発光波形とは異なる波形となった場合、制御線８の異常を検出することが可能である。例えば、制御線８に信号を２回入力させることによって第２発光素子９を２回発光させて、正しく２回発光するか否かを検出する方法をとることができる。図１０に示すように、期待される発光波形と異なり、１回目の信号変化がない場合等には制御線８若しく制御回路１の内部ノードの異常を検出することができる。 <Example of failure detection of a node in a control line or control circuit>
[Detection Example 1]
According to the present invention, for example, the potential of the internal node n in FIG. 2 is measured as an output of the control circuit 1 or an internal node of the control circuit 1, and based on a signal input to the second light emitting element 9 from the control line 8 If the waveform is different from the expected light emission waveform, it is possible to detect an abnormality in the control line 8. For example, a method of detecting whether or not the second light emitting element 9 emits light twice by inputting a signal to the control line 8 twice and correctly emitting light twice can be adopted. As shown in FIG. 10, unlike the expected light emission waveform, when there is no signal change for the first time, an abnormality of the control line 8 or an internal node of the control circuit 1 can be detected.
　また、他の例として、上下段、すなわち３つの第２発光素子を同時に発光させて、発光の有無に基づいて制御線８若しく制御回路１の内部ノードの異常を検出する方法がある。図１に示す制御線８（ｎ－１）、制御線８（ｎ）、制御線８（ｎ＋１）に対して同時に信号を入力した場合に、制御線８（ｎ＋１）、制御線８（ｎ－１）に係る第２発光素子９からは発光に伴う同一の発光波形が得られたのに対して、制御線８（ｎ）からは発光波形が得られない場合には、制御線８（ｎ）の異常を検出することができる。 As another example, there is a method of detecting an abnormality of the control line 8 or an internal node of the control circuit 1 based on the presence or absence of light emission by causing the upper and lower stages, that is, three second light emitting elements to emit light simultaneously. When signals are simultaneously input to the control line 8 (n−1), the control line 8 (n), and the control line 8 (n + 1) shown in FIG. 1, the control line 8 (n + 1) and the control line 8 (n− In the case where the same light emission waveform associated with light emission is obtained from the second light emitting element 9 according to 1), but the light emission waveform cannot be obtained from the control line 8 (n), the control line 8 (n ) Abnormality can be detected.
　〔検出例２〕
　検査回路１０の制御線８と接続されている部分よりも制御回路１側に、異常抵抗、若しくは異常ＴＦＴ等の不良素子が存在する場合には、図１１の上段に示す期待される発光波形に対して、図１１の下段に示すような発光信号に波形のなまりが出力されることによって不良を検出することができる。 [Detection Example 2]
When a defective element such as an abnormal resistance or an abnormal TFT exists on the control circuit 1 side of the portion connected to the control line 8 of the inspection circuit 10, the expected light emission waveform shown in the upper part of FIG. On the other hand, a defect can be detected by outputting a rounded waveform in the light emission signal as shown in the lower part of FIG.
　〔検出例３〕
　隣り合う制御線８（ｎ）と制御線８（ｎ－１）が、なんらかの原因でショートしている場合、例えば制御線８（ｎ）と制御線８（ｎ－１）に逆位相の信号を同時にかけた場合には、両方の制御線の信号が打ち消し合う（下段に示す破線）。この場合、図１２の上段に示す期待される発光波形に対して、図１２の下段に示すような発光が全く見られないといった異常波形となる。 [Detection Example 3]
When the adjacent control line 8 (n) and the control line 8 (n-1) are short-circuited for some reason, for example, a signal having an opposite phase is applied to the control line 8 (n) and the control line 8 (n-1). When applied simultaneously, the signals of both control lines cancel each other (dashed line shown in the lower stage). In this case, an abnormal waveform in which no light emission as shown in the lower part of FIG.
　〔検出例４〕
　対象の制御線８若しくはノードがオープンとなっている場合、オープン箇所よりも制御回路１から離れた位置に設けられた第２発光素子９からの発光強度を測定すると、図１３の上段に示す期待される発光波形に対して、図１３の下段に示すように測定波形は不定となる、若しくは期待される発光波形とは一致しない波形が検出される。 [Detection Example 4]
When the target control line 8 or node is open, the expected intensity shown in the upper part of FIG. 13 is obtained by measuring the light emission intensity from the second light emitting element 9 provided at a position farther from the control circuit 1 than the open part. With respect to the emitted light waveform, as shown in the lower part of FIG. 13, the measured waveform is indefinite or a waveform that does not match the expected light emission waveform is detected.
　なお、制御線８毎に第２発光素子９を備える意味であるが、すべての制御線８に第２発光素子９が備えられていてもよく、複数の制御線８のうち、一部の制御線８毎に備えられていてもよい。例えば、２本毎又は３本毎の制御線８毎に第２発光素子９が備えられていてもよい。 In addition, although it is the meaning provided with the 2nd light emitting element 9 for every control line 8, the 2nd light emitting element 9 may be provided in all the control lines 8, and some control among the some control lines 8 is possible. Each line 8 may be provided. For example, the second light emitting element 9 may be provided for every two or every three control lines 8.
　なお、上記の検出例１～検出例４の説明では、制御線若しくは制御回路内のノードの不良検出例について説明したが、データ線若しくはデータ線駆動回路内のノードの不良検出も、検出例１～検出例４と同様に行うことができる。 In the above description of detection example 1 to detection example 4, the example of detecting a failure of a node in the control line or the control circuit has been described. However, detection of a failure of a node in the data line or the data line driving circuit is also detected in the detection example 1. This can be performed in the same manner as in Detection Example 4.
　＜表示デバイス２の製造方法について＞
　第２発光素子９に対して、制御線８を流れる電気信号又は制御回路１内に設けられたノードｎ等を流れる電気信号を入力し、第２発光素子９からの発光を検出して評価することにより、制御回路１を検査する検査工程を有する表示デバイス２の製造方法を実現することができる。 <About the manufacturing method of the display device 2>
An electric signal flowing through the control line 8 or an electric signal flowing through the node n provided in the control circuit 1 is input to the second light emitting element 9, and light emission from the second light emitting element 9 is detected and evaluated. Thereby, the manufacturing method of the display device 2 which has the test process which test | inspects the control circuit 1 is realizable.
　この製造方法により、例えば発光素子を構成する材料蒸着工程後であって薄膜封止（ＴＦＥ）行程前に、走査線駆動回路、若しくはエミッションドライバの不良を検出する事ができる為、従来のパネル検査時より早い段階でドライバー不良の振り分けを可能とすることができる。 This manufacturing method can detect defects in the scanning line drive circuit or the emission driver after the material vapor deposition process for forming the light emitting element and before the thin film sealing (TFE) process. It is possible to sort out driver defects at an earlier stage.
　特に、前記検出例１に基づく制御線８に接続された制御回路１内の配線の不良段の特定、前記検出例２に基づく制御回路１内の不良素子の特定、前記検出例３に基づく制御回路１内の配線間ショートの特定、及び前記検出例４に基づく制御回路内の配線オープンの特定の少なくとも一つが行われる表示デバイスの製造方法が好ましい。これにより、検出例１～４に示された不良要因を従来よりも早い段階で明確にしつつ表示デバイス２を製造することができる。 In particular, identification of a defective stage of wiring in the control circuit 1 connected to the control line 8 based on the detection example 1, identification of a defective element in the control circuit 1 based on the detection example 2, control based on the detection example 3 A display device manufacturing method in which at least one of specifying a short circuit between wires in the circuit 1 and specifying a wire open in the control circuit based on the detection example 4 is performed is preferable. As a result, the display device 2 can be manufactured while clarifying the failure factors shown in the detection examples 1 to 4 at an earlier stage than before.
　さらに、第２発光素子９からの発光を検出して不良の有無を評価した後、分断端部２ａの端面を切断面として、第１引き回し配線、及び第２引き回し配線を切断することによって、第１の定電圧源であるＥＬＶＤＤや第２の定電圧源であるＥＬＶＳＳに接続された領域を除去することができる。これにより、額縁領域７の省スペース化を図ることができるので、表示デバイス２のさらなる狭額縁化を実現することができる。 Further, after detecting the light emission from the second light emitting element 9 and evaluating the presence or absence of defects, by cutting the first routing wiring and the second routing wiring with the end face of the divided end portion 2a as a cut surface, A region connected to ELVDD which is the first constant voltage source or ELVSS which is the second constant voltage source can be removed. Thereby, since space saving of the frame area | region 7 can be achieved, the further narrow frame of the display device 2 is realizable.
　本実施形態に係るディスプレイは、表示素子を備えた表示パネルであれば、特に限定されるものではない。上記表示素子は、電流によって輝度や透過率が制御される表示素子であり、電流制御の表示素子としては、ＯＬＥＤ（Organic Light Emitting Diode：有機発光ダイオード）を備えた有機ＥＬ（Electro Luminescence：エレクトロルミネッセンス）ディスプレイ、又は無機発光ダイオードを備えた無機ＥＬディスプレイ等のＥＬディスプレイＱＬＥＤ（Quantum dot Light Emitting Diode：量子ドット発光ダイオード）を備えたＱＬＥＤディスプレイ等がある。 The display according to the present embodiment is not particularly limited as long as the display panel includes a display element. The display element is a display element whose luminance and transmittance are controlled by current. As a current-controlled display element, an organic EL (Electro Luminescence) having an OLED (Organic Light Emitting Diode) is used. ) A display, or an EL display QLED (Quantum 無機 dot 発 光 Light Emitting Diode) such as an inorganic EL display provided with an inorganic light emitting diode, or the like.
　１　制御回路
　２　表示デバイス
　３　表示領域
　４　画素
　５　画素回路
　６　第１発光素子
　７　額縁領域
　８　制御線
　９　第２発光素子
　１１　受光装置
　３３　トレンチ
　Ｈ１　第１引き回し配線
　Ｈ２　第２引き回し配線
　Ｔ１　トランジスタ DESCRIPTION OF SYMBOLS 1 Control circuit 2 Display device 3 Display area 4 Pixel 5 Pixel circuit 6 1st light emitting element 7 Frame area 8 Control line 9 2nd light emitting element 11 Light receiving device 33 Trench H1 1st routing wiring H2 2nd routing wiring T1 transistor

Claims (18)

  1. 　表示領域と、表示領域の周囲に設けられた額縁領域と、表示領域に設けられた第１発光素子を発光させることにより、画像を表示する表示デバイスであって、
    　前記画像を表示するデータ信号が供給される複数のデータ線と、
    　前記複数のデータ線と交差するように配設された複数の制御線と、
    　前記複数のデータ線及び前記複数の制御線の各交点に設けられた前記第１発光素子を備えた複数の画素回路と、
    　前記データ線に前記データ信号が供給されるタイミングで、対応する制御線をアクティブにする制御回路と、
    　前記制御線毎に前記額縁領域に設けられた第２発光素子と、
    　前記第２発光素子の発光駆動をオン/オフする第１トランジスタと、を備え、
    　前記第２発光素子は、前記制御線を流れる電気信号又は前記制御回路内に設けられたノードを流れる電気信号が前記第１トランジスタの制御端子に入力されることにより発光が制御され、
    　前記第１トランジスタの第１導通端子は、前記第２発光素子の陽極又は陰極の一方に接続され、
    　前記第１トランジスタの第２導通端子は、前記表示デバイスの端面まで延伸する第１引き回し配線と電気的に導通し、前記第１引き回し配線は前記端面において交差し、
    　前記第２発光素子の陽極又は陰極の他方は、前記表示デバイスの前記端面まで延伸する第２引き回し配線と電気的に導通し、第２引き回し配線は前記端面において交差されてなる
    ことを特徴とする表示デバイス。     A display device that displays an image by causing a display area, a frame area provided around the display area, and a first light emitting element provided in the display area to emit light,
    A plurality of data lines to which a data signal for displaying the image is supplied;
    A plurality of control lines arranged to intersect the plurality of data lines;
    A plurality of pixel circuits including the first light emitting elements provided at intersections of the plurality of data lines and the plurality of control lines;
    A control circuit for activating a corresponding control line at a timing when the data signal is supplied to the data line;
    A second light emitting element provided in the frame region for each control line;
    A first transistor for turning on / off the light emission drive of the second light emitting element,
    The second light emitting element is controlled to emit light when an electric signal flowing through the control line or an electric signal flowing through a node provided in the control circuit is input to a control terminal of the first transistor,
    A first conduction terminal of the first transistor is connected to one of an anode and a cathode of the second light emitting element;
    A second conduction terminal of the first transistor is electrically connected to a first lead wiring extending to an end face of the display device, and the first lead wiring intersects at the end face;
    The other of the anode and the cathode of the second light emitting element is electrically connected to a second lead wiring extending to the end face of the display device, and the second lead wiring intersects with the end face. Display device.
  2. 　前記第２発光素子が、前記額縁領域において前記表示領域の左右方向外側に近接して設けられたＧＤＭ領域に設けられてなる
    ことを特徴とする請求項１に記載の表示デバイス。     2. The display device according to claim 1, wherein the second light emitting element is provided in a GDM region provided in the frame region adjacent to the outside in the left-right direction of the display region.
  3. 　前記データ線及び前記制御線上に設けられた平坦化膜を更に備え、
    　前記第１発光素子は、前記平坦化膜上に形成されるとともに、第１電極と、第２電極と、前記第１電極及び前記第２電極の間に設けられた機能層とを備え、
    　前記平坦化膜には、当該平坦化膜を貫通するトレンチが形成され、
    　前記第２電極及び前記第１電極と同層で同一材料によって形成された金属層は、前記トレンチの内面を覆い、且つ前記トレンチの内部で互いに接触し、
    　前記第２発光素子は、前記トレンチよりも内側に設けられてなる
    ことを特徴とする請求項２に記載の表示デバイス。     A flattening film provided on the data line and the control line;
    The first light emitting element is formed on the planarizing film, and includes a first electrode, a second electrode, and a functional layer provided between the first electrode and the second electrode,
    In the planarizing film, a trench penetrating the planarizing film is formed,
    The metal layer formed of the same material and in the same layer as the second electrode and the first electrode covers the inner surface of the trench and contacts each other inside the trench,
    The display device according to claim 2, wherein the second light emitting element is provided inside the trench.
  4. 　前記第１発光素子の発光層と前記第２発光素子の発光層は、同一の形状及び大きさであって、前記第１発光素子の発光層のエッジカバーの開口は、前記第２発光素子の発光層のエッジカバーの開口よりも大きい
    ことを特徴とする請求項１から３のいずれか１つに記載の表示デバイス。     The light emitting layer of the first light emitting element and the light emitting layer of the second light emitting element have the same shape and size, and the opening of the edge cover of the light emitting layer of the first light emitting element is the same as that of the second light emitting element. The display device according to claim 1, wherein the display device is larger than an opening of an edge cover of the light emitting layer.
  5. 　前記複数の制御線にそれぞれ設けられた複数の前記第２発光素子には、互いに異なる色を発光する複数種類の発光素子が用いられている
    ことを特徴とする請求項１から４のいずれか１つに記載の表示デバイス。     5. The light emitting device according to claim 1, wherein a plurality of types of light emitting devices that emit different colors are used for the plurality of second light emitting devices respectively provided on the plurality of control lines. The display device described in one.
  6. 　前記ノードは複数設けられ、複数の前記ノードにそれぞれ設けられた複数の前記第２発光素子には、互いに異なる色を発光する複数種類の発光素子が用いられている
    ことを特徴とする請求項１から５のいずれか１つに記載の表示デバイス。     The plurality of nodes are provided, and a plurality of types of light emitting elements that emit different colors are used for the plurality of second light emitting elements respectively provided in the plurality of nodes. The display device according to any one of 5 to 5.
  7. 　前記制御線が走査線及びエミッション線であり、前記制御回路が走査線駆動回路及びエミッションドライバであり、前記走査線と前記エミッション線にそれぞれ設けられた複数の前記第２発光素子には、互いに異なる色を発光する複数種類の発光素子が用いられている
    ことを特徴とする請求項１から６のいずれか１つに記載の表示デバイス。     The control line is a scanning line and an emission line, the control circuit is a scanning line driving circuit and an emission driver, and the plurality of second light emitting elements respectively provided on the scanning line and the emission line are different from each other. The display device according to claim 1, wherein a plurality of types of light emitting elements that emit colors are used.
  8. 　前記制御線が走査線であり、前記制御回路が走査線駆動回路である
    ことを特徴とする請求項１から７のいずれか１つに記載の表示デバイス。     The display device according to claim 1, wherein the control line is a scanning line, and the control circuit is a scanning line driving circuit.
  9. 　前記制御線がエミッション線であり、前記制御回路がエミッションドライバである
    ことを特徴とする請求項１から７のいずれか１つに記載の表示デバイス。     The display device according to claim 1, wherein the control line is an emission line, and the control circuit is an emission driver.
  10. 　前記第２発光素子が、前記データ線と交差する前記表示領域の辺の外側に設けられてなる
    ことを特徴とする請求項１から９のいずれか１つに記載の表示デバイス。     The display device according to claim 1, wherein the second light emitting element is provided outside a side of the display area that intersects the data line.
  11. 　前記データ線毎に前記額縁領域に設けられた前記第２発光素子と、
    　前記データ線に前記データ信号を供給するデータ線駆動回路と、を備え
    　前記データ線毎に設けられた前記第２発光素子は、前記データ線を流れる電気信号又は前記データ線駆動回路内に設けられたノードを流れる電気信号が、前記データ線毎に接続されるトランジスタの制御端子に入力されることにより発光が制御される
    ことを特徴とする請求項１０に記載の表示デバイス。     The second light emitting element provided in the frame region for each data line;
    A data line driving circuit for supplying the data signal to the data line, wherein the second light emitting element provided for each data line is provided in an electric signal flowing through the data line or in the data line driving circuit. 11. The display device according to claim 10, wherein light emission is controlled by inputting an electric signal flowing through the node to a control terminal of a transistor connected to each data line.
  12. 　前記データ線駆動回路は、デマルチプレクサを含む
    ことを特徴とする請求項１１に記載の表示デバイス。     The display device according to claim 11, wherein the data line driving circuit includes a demultiplexer.
  13. 　前記第１引き回し配線は、前記端面を経由して延伸して第１の定電圧源に接続され、
    　前記第２引き回し配線は、前記端面を経由して延伸して第２の定電圧源に接続されてなる
    ことを特徴とする請求項１から１２のいずれか１つに記載の表示デバイス。     The first routing wiring extends through the end face and is connected to a first constant voltage source;
    13. The display device according to claim 1, wherein the second routing wiring extends through the end face and is connected to a second constant voltage source.
  14. 　前記端面における前記第１引き回し線の切断面及び前記第２引き回し線の切断面は、導体化された半導体層によって形成される
    ことを特徴とする請求項１から１３のいずれか１つに記載の表示デバイス。     14. The cut surface of the first lead line and the cut surface of the second lead line at the end surface are formed by a semiconductor layer that is made into a conductor. 14. Display device.
  15. 　前記第１発光素子及び前記第２発光素子は、有機ＥＬ素子である
    ことを特徴とする請求項１から１４のいずれか１つに記載の表示デバイス。     The display device according to claim 1, wherein the first light emitting element and the second light emitting element are organic EL elements.
  16. 　表示領域と、表示領域の周囲に設けられた額縁領域と、表示領域に設けられた第１発光素子を発光させることにより、画像を表示する表示デバイスの製造方法であって、
    　前記画像を表示するデータ信号が供給される複数のデータ線と、
    　前記複数のデータ線と交差するように配設された複数の制御線と、
    　前記複数のデータ線及び前記複数の制御線の各交点に設けられた前記第１発光素子を備えた複数の画素回路と、
    　前記データ線に前記データ信号が供給されるタイミングで、対応する制御線をアクティブにする制御回路と、
    　前記制御線毎に前記額縁領域に設けられた第２発光素子と、前記第２発光素子の発光駆動をオン/オフする第１トランジスタと、を備え、
    　前記第２発光素子は、前記制御線を流れる電気信号又は前記制御回路内に設けられたノードを流れる電気信号が前記第１トランジスタの制御端子に入力されることにより発光が制御され、
    　前記第１トランジスタの第１導通端子は、前記第２発光素子の陽極又は陰極の一方に接続されてなり、
    　前記第１トランジスタの第２導通端子を、前記表示デバイスの端面を経由して第１の定電圧源に接続された第１引き回し線と電気的に導通させ、
    　前記第２発光素子の陽極又は陰極の他方を、前記表示デバイスの端面を経由して第２の定電圧源に接続された第２引き回し線と電気的に導通させ、
    　前記第２発光素子に対して、前記制御線を流れる電気信号又は前記制御回路内に設けられたノードを流れる電気信号を入力し、当該第２発光素子からの発光を検出して評価することにより、前記制御回路を検査する
    ことを特徴とする表示デバイスの製造方法。     A method for manufacturing a display device that displays an image by causing a display region, a frame region provided around the display region, and a first light emitting element provided in the display region to emit light,
    A plurality of data lines to which a data signal for displaying the image is supplied;
    A plurality of control lines arranged to intersect the plurality of data lines;
    A plurality of pixel circuits including the first light emitting elements provided at intersections of the plurality of data lines and the plurality of control lines;
    A control circuit for activating a corresponding control line at a timing when the data signal is supplied to the data line;
    A second light emitting element provided in the frame region for each control line, and a first transistor for turning on / off the light emission driving of the second light emitting element,
    The second light emitting element is controlled to emit light when an electric signal flowing through the control line or an electric signal flowing through a node provided in the control circuit is input to a control terminal of the first transistor,
    A first conduction terminal of the first transistor is connected to one of an anode and a cathode of the second light emitting element;
    Electrically connecting a second conduction terminal of the first transistor to a first lead line connected to a first constant voltage source via an end face of the display device;
    Electrically connecting the other of the anode or the cathode of the second light emitting element to a second lead line connected to a second constant voltage source via an end face of the display device;
    By inputting an electric signal flowing through the control line or an electric signal flowing through a node provided in the control circuit to the second light emitting element, and detecting and evaluating light emission from the second light emitting element. A method of manufacturing a display device, wherein the control circuit is inspected.
  17. 　前記第２発光素子からの発光を検出して評価した後、
    　前記第１引き回し配線及び前記第２引き回し配線を前記端面において切断する
    ことを特徴とする請求項１６に記載の表示デバイスの製造方法。     After detecting and evaluating light emission from the second light emitting element,
    The method of manufacturing a display device according to claim 16, wherein the first routing wiring and the second routing wiring are cut at the end face.
  18. 　前記第２発光素子と前記第１発光素子とは、同時に形成される
    ことを特徴とする請求項１６又は１７に記載の表示デバイスの製造方法。     The method for manufacturing a display device according to claim 16, wherein the second light emitting element and the first light emitting element are formed simultaneously.
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* Cited by examiner, † Cited by third party
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CN111477641A (en) * 2020-05-12 2020-07-31 武汉华星光电技术有限公司 Array substrate, preparation method thereof and display device
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