WO2015012216A1

WO2015012216A1 - El display device and drive method for el display device

Info

Publication number: WO2015012216A1
Application number: PCT/JP2014/069170
Authority: WO
Inventors: 小倉　潤
Original assignee: 凸版印刷株式会社
Priority date: 2013-07-23
Filing date: 2014-07-18
Publication date: 2015-01-29
Also published as: TW201508722A

Abstract

An EL display device that, during a light-emission period, holds a voltage corresponding to a light-emission voltage in a storage capacitor (Cs) and causes a current corresponding to the light-emission voltage to flow to an EL element (11) via a drive transistor (Tr3). During a non-light-emission period, the EL display device holds a voltage corresponding to a non-light-emission voltage in the storage capacitor (Cs) and sets the voltage for a power supply end such that the current that has flowed through the drive transistor (Tr3) does not flow to the EL element (11). The EL display device has a state in which the non-light-emission voltage is lower the higher the light-emission voltage.

Description

EL display device and driving method of EL display device

The technology of the present disclosure relates to an EL display device including an electro-luminescence element (EL element) to which a current is supplied through a drive transistor, and a method for driving the EL display device.

The EL display device includes a plurality of pixel circuits, and each of the plurality of pixel circuits includes a drive transistor, a sampling transistor, and a storage capacitor. The storage capacitor is connected between the gate and source of the driving transistor, and the sampling transistor writes a voltage of a level corresponding to the gradation data to the storage capacitor. The drive transistor is configured to operate in a saturation region, and supplies a drain current corresponding to a voltage held by the storage capacitor to the EL element. The EL element is driven by the drain current and emits light with luminance corresponding to the gradation data (see, for example, Patent Document 1).

JP 2010-128397 A

The voltage that the sampling transistor writes to the storage capacitor gives a single polarity between the gate and source of the drive transistor. In an EL display device that displays an image, such writing is repeated during a period in which the image is displayed. Since voltage application is repeated with a single polarity between the gate and source of the drive transistor, the threshold voltage shift between the gate and source proceeds in the drive transistor.

At this time, the voltage applied between the gate and source of the drive transistor is at a level corresponding to the gradation data, and the luminance gradation required for each pixel is usually different. Differs for each pixel. As a result, each of the plurality of pixels constituting one display surface has different luminance with respect to the gradation data.

An object of the technology of the present disclosure is to provide an EL display device that suppresses a shift in threshold voltage of a drive transistor from pixel to pixel and a method for driving the EL display device.

One aspect of the EL display device of the present disclosure includes a plurality of pixel circuits, and the pixel circuits include a drive transistor, an EL element, and a storage capacitor. The driving transistor has a gate, a source, and a drain, and one of the source and the drain is a connection end, and the other of the source and the drain is a feeding end. The EL element is electrically connected to the connection end, and the storage capacitor is electrically connected to the gate and the source. In the EL display device, a voltage corresponding to a light emission voltage is held in the storage capacitor during the light emission period, and a current corresponding to the light emission voltage is supplied to the EL element through the drive transistor, and the hold is performed during the non-light emission period. A voltage corresponding to a non-light-emitting voltage is held in a capacitor, and the voltage at the power feeding end is set so that a current passing through the driving transistor does not flow to the EL element. The higher the light-emitting voltage, the more the non-light-emitting voltage becomes It is configured to have a low state.

Another aspect of the EL display device according to the present disclosure is a method for driving an EL display device including a plurality of pixel circuits, and the pixel circuits include a drive transistor, an EL element, and a storage capacitor. The driving transistor has a gate, a source, and a drain, and one of the source and the drain is a connection end, and the other of the source and the drain is a feeding end. The EL element is electrically connected to the connection end, and the storage capacitor is electrically connected to the gate and the source. In this EL display device driving method, a voltage corresponding to a light emission voltage is held in the storage capacitor, and a current corresponding to the light emission voltage is supplied to the EL element through the drive transistor, and the light emission voltage is high. The voltage corresponding to the non-light-emitting voltage set so as to have a low state is held in the holding capacitor, and the voltage at the feeding end is set so that the current passing through the driving transistor does not flow to the EL element. A non-light emitting process.

According to one aspect of the EL display device of the present disclosure, the voltage applied between the gate and the source in each of the plurality of drive transistors is higher when the EL element emits light, and when the EL element is not emitting light. Low. Therefore, it is possible to suppress a shift in threshold voltage of the driving transistor from pixel to pixel.

Another aspect of the EL display device according to the present disclosure is configured to repeat a frame including the light emission period and the non-light emission period, and the non-light emission voltage is lower as the frame has a higher light emission voltage. Have

According to another aspect of the EL display device of the present disclosure, the shift of the threshold voltage of the driving transistor is different for each pixel, and is suppressed for each frame which is the shortest repetition period in display.

In another aspect of the EL display device according to the present disclosure, the non-light-emitting voltage is an inverted voltage symmetrical to the light-emitting voltage with reference to an intermediate value in a setting range of the light-emitting voltage.
According to another aspect of the EL display device of the present disclosure, an inversion voltage symmetrical to the light emission voltage is used as the non-light emission voltage. Therefore, the voltage applied between the gate and the source through one light emission period and one non-light emission period is uniform in a plurality of pixels. Therefore, the effect of suppressing the shift of the threshold voltage of the driving transistor from being different for each pixel is further enhanced.

In another aspect of the EL display device of the present disclosure, the pixel circuit has the same polarity as the light emission voltage and the light emission voltage when the light emission voltage in the light emission period is equal to or lower than a switching value. The higher the voltage is, the lower the voltage that is set as the non-light emission voltage is held in the holding capacitor, and when the light emission voltage in the light emission period is higher than the switching value, the voltage having a polarity different from the light emission voltage is The non-light emitting voltage is held in the holding capacitor.

The threshold voltage shift of the drive transistor progresses as the emission voltage during the emission period increases. According to another aspect of the EL display device of the present disclosure, when the light emission voltage is higher than the switching value, the holding capacitor holds a voltage corresponding to a non-light emission voltage having a polarity different from that of the light emission voltage. Therefore, when the threshold voltage shift of the driving transistor proceeds excessively in a specific pixel, the threshold voltage shift is suppressed for the specific pixel. As a result, the range in which the effect of suppressing the shift of the threshold voltage of the drive transistor from pixel to pixel is extended is widened with respect to the degree of shift of the threshold voltage.

In another aspect of the EL display device according to the present disclosure, the pixel circuit is configured to set the non-light-emitting voltage to a constant value when the light-emitting voltage in the light-emitting period is higher than the switching value.

According to another aspect of the EL display device of the present disclosure, the non-light-emitting voltage having a polarity different from that of the light-emitting voltage is a constant value, so that the configuration required for generating the non-light-emitting voltage can be simplified.
In another aspect of the EL display device according to the present disclosure, the pixel circuit includes a detection operation of detecting a threshold voltage of the drive transistor in the non-light emission period, and is based on a previous detection operation in the light emission period. The light emission voltage is corrected in advance using the detection result.

In another aspect of the driving method of the EL display device according to the present disclosure, the non-light emitting step further includes a detecting step of detecting a threshold voltage of the driving transistor, and the light emitting step is based on the previous detecting step. The light emission voltage is corrected in advance using the detection result.

According to another aspect of the technology of the present disclosure, a change in luminance of the EL element due to a change in threshold voltage of the drive transistor can be suppressed.

According to the EL display device and the EL display device driving method of the present disclosure, it is possible to suppress the shift of the threshold voltage of the driving transistor from pixel to pixel.

It is a block diagram which shows the whole structure of the EL display apparatus in 1st Embodiment. FIG. 2 is a block diagram illustrating a configuration of a control unit and a selection driver included in the EL display device of FIG. 1. FIG. 2 is a block diagram illustrating a configuration of a data driver and a pixel circuit included in the EL display device of FIG. 1. 2 is a graph showing a relationship between a light emission voltage applied to a data line and a non-light emission voltage applied to a data line in the EL display device of FIG. 1. FIG. 2 is a circuit diagram showing a pixel circuit included in the EL display device of FIG. 1 and showing a state at the time of writing operation for light emission. It is a circuit diagram which shows the pixel circuit with which the EL display apparatus of FIG. 1 is provided, Comprising: It is a figure which shows the state at the time of light emission operation. FIG. 2 is a circuit diagram showing a pixel circuit included in the EL display device of FIG. 1 and showing a state during a non-light-emission writing operation. It is a circuit diagram which shows the pixel circuit with which the EL display apparatus of FIG. 1 is provided, Comprising: It is a figure which shows the state at the time of non-light emission operation. 2 is a timing chart showing a transition of a scanning line and a voltage applied to a power supply line and a transition of a control signal input to a data driver in a light emission period of the EL display device of FIG. 2 is a timing chart showing a transition of a voltage applied to a scanning line and a power supply line and a transition of a control signal input to a data driver in a non-light emitting period of the EL display device of FIG. It is a graph which shows the relationship between the forward voltage applied to an EL element, and the drive current which flows into an EL element in the EL display apparatus in 2nd Embodiment. FIG. 9 is a potential correlation diagram showing a relative relationship between voltages applied to scanning lines, power supply lines, and data lines included in an EL display device according to a second embodiment, with a ground voltage as a reference. It is a graph which shows the relationship between the light emission voltage applied to a data line in the EL display device of 2nd Embodiment, and the non-light-emission voltage applied to a data line. It is a circuit diagram which shows the pixel circuit with which the EL display apparatus of 2nd Embodiment is provided, Comprising: It is a figure which shows the state at the time of writing operation for non-light emission. It is a circuit diagram which shows the pixel circuit with which the EL display apparatus of 2nd Embodiment is provided, Comprising: It is a figure which shows the state at the time of non-light emission operation. It is a block diagram which shows the structure of the control part with which the EL display apparatus in 3rd Embodiment is provided, and a selection driver. It is a block diagram which shows the structure of the data driver with which the EL display apparatus of 3rd Embodiment is provided, and a pixel circuit. It is a timing chart which shows transition of the level of the control signal in the light emission period in the EL display device of 3rd Embodiment with the state of a switch. 10 is a timing chart showing a transition of a level of a control signal in a non-light emitting period in the EL display device according to the third embodiment together with a switch state. It is a graph which shows the dependence of the light emission voltage with respect to the drain current of the drive transistor with which the EL display apparatus of 3rd Embodiment is provided. It is a timing chart which shows the transition of the level of the control signal in the detection operation in the EL display device of 3rd Embodiment with the state of a switch. It is a graph which shows the relationship between the electric potential of the data line in the EL display device of 3rd Embodiment, and relaxation time. It is a schematic diagram which shows the timing of each operation | movement performed in the 1st flame | frame in the EL display apparatus of 3rd Embodiment about each of the 540th line pixel from the 1st line pixel. It is a schematic diagram which shows the timing of each operation | movement performed in the 2nd frame in the EL display apparatus of 3rd Embodiment about each of the pixel of the 540th line from the 1st line of pixels. It is a schematic diagram which shows the timing of each operation | movement performed by the 540th frame in the EL display apparatus of 3rd Embodiment about each of the pixel of the 540th line from the pixel of the 1st line. 9 is a timing chart showing a transition of a level of a control signal for each scanning line and power supply line in a period in which one frame is displayed in the EL display device according to the third embodiment. It is a graph which shows the relationship between the light emission voltage applied to a data line, and the non-light emission voltage applied to a data line in the EL display device of a modification. It is a graph which shows the relationship between the light emission voltage applied to a data line, and the non-light emission voltage applied to a data line in the EL display device of a modification. It is a circuit diagram which shows the pixel circuit of the EL display apparatus of a modification. It is a figure which shows typically transition of the detection target of the threshold value detection operation | movement for every flame | frame in the EL display apparatus of a modification. It is a figure which shows typically transition of the detection target of the threshold value detection operation | movement for every flame | frame in the EL display apparatus of a modification. It is a figure which shows typically transition of the detection target of the threshold value detection operation | movement for every flame | frame in the EL display apparatus of a modification.

With reference to FIG. 1 to FIG. 10, a first embodiment in which an EL display device apparatus and a driving method of the EL display device according to the present disclosure are embodied will be described.
[First Embodiment]
The overall configuration of the EL display device will be described with reference to FIG.

As shown in FIG. 1, the plurality of pixels Px included in the display panel 10 are positioned in a matrix of m rows × n columns. m is an integer of 1 or more, and n is an integer of 1 or more. Each of the plurality of pixels Px has one pixel circuit including one organic EL element.

The m scanning lines Ls extending along the row direction and the n data lines Ld extending along the column direction intersect with each other in plan view with respect to the display surface. Each of the plurality of pixels Px is located near the intersection of the scanning line Ls and the data line Ld. Each of the n pixels Px arranged in the row direction is connected to one scanning line Ls and one power supply line La. Each of the m pixels Px arranged along the column direction is connected to one data line Ld.

Each of the m scanning lines Ls is electrically connected to the selection driver 20. Each of the m power lines La is electrically connected to the power driver 30. Each of the n data lines Ld is electrically connected to the data driver 40. Each of the driving of the selection driver 20, the driving of the power supply driver 30, and the driving of the data driver 40 is controlled by the control unit 50.

The control unit 50 is mainly configured by a microcomputer having a central processing unit and a storage unit. The control unit 50 receives an image signal from the outside, and generates display data Din for each pixel Px using the image signal. The display data Din for each pixel Px is, for example, gradation data composed of 8 bits. The control unit 50 inputs display data Din for each pixel Px to the data driver 40.

The selection driver 20 includes a shift register and a buffer. The selection driver 20 selects either the selection voltage VgH that is at a high level with respect to the reference voltage or the non-selection voltage VgL that is at a low level with respect to the reference voltage in accordance with a control signal input from the control unit 50. And applied for each scanning line Ls. The selection driver 20 sets the scanning line Ls to which the selection voltage VgH is applied as a selection target. The selection driver 20 sequentially switches the selection target candidates from the first scanning line Ls to the m-th scanning line Ls, which is the last row, and repeats the switching of the selection target candidates.

The power supply driver 30 includes a shift register and a buffer. In accordance with a control signal input from the control unit 50, the power supply driver 30 supplies either the drive voltage ELVDD that is at a high level with respect to the reference voltage or the write voltage WDVSS that is at the same level as the reference voltage. Applied for each line La. The power supply driver 30 sets the power supply line La to which the drive voltage ELVDD is applied as a supply target. The power supply driver 30 sequentially switches the supply target from the first power supply line La to the m-th power supply line La, which is the last row, and repeats the switching of the supply target. The power supply driver 30 is configured such that when the supply target of the power supply driver 30 is the k-th row (k is an integer from 1 to m), the selection target of the selection driver 20 is also the k-th row.

The data driver 40 generates the light emission voltage VD or the non-light emission voltage VDN using the display data Din. When the control unit 50 inputs display data Din for generating the light emission voltage VD to the data driver 40, the data driver 40 generates the light emission voltage VD using the display data Din. When the control unit 50 inputs display data Din for generating the non-light emitting voltage VDN to the data driver 40, the data driver 40 generates the non-light emitting voltage VDN using the display data Din.

The data driver 40 generates the light emission voltage VD for each data line Ld during the light emission period. The data driver 40 applies the light emission voltage VD simultaneously to each of the n data lines Ld according to a control signal input from the control unit 50.

The data driver 40 generates a non-light emission voltage VDN for each data line Ld in the non-light emission period. The data driver 40 applies the non-light emitting voltage VDN simultaneously to each of the n data lines Ld according to a control signal input from the control unit 50.

[Configuration of Control Unit 50]
With reference to FIG. 2, the structure of the control part 50 is demonstrated. As shown in FIG. 2, the control unit 50 includes an image signal input unit 51, a timing controller 52, a storage unit 53, an image signal processing unit 54, and a display data output unit 55.

The image signal input unit 51 holds the image signal input to the control unit 50 and outputs the held image signal to the storage unit 53. The storage unit 53 stores the image signal output from the image signal input unit 51 and outputs the stored image signal to the image signal processing unit 54. The display data output unit 55 outputs the processing result of the image signal processing unit 54 to the data driver 40 as display data Din.

The storage unit 53 stores data indicating the relationship between the light emission voltage VD and the non-light emission voltage VDN. For each pixel Px in one frame, the image signal processing unit 54 uses the display data Din for generating the light emission voltage VD and the relationship between the light emission voltage VD and the non-light emission voltage VDN to generate the non-light emission voltage VDN. Display data Din for generation is generated.

The timing controller 52 controls the timing of writing the image signal to the storage unit 53 and the timing of reading the image signal to the storage unit 53. The timing controller 52 controls the processing timing by the image signal processing unit 54. The timing controller 52 generates a data shift clock signal Clkd and a display shift clock signal Clks. The timing controller 52 outputs the data shift clock signal Clkd to the data driver 40, and outputs the display shift clock signal Clks to the selection driver 20 and the power supply driver 30.

The image signal processing unit 54 uses the image signal read from the storage unit 53 to generate light emission gradation data for each pixel Px. The image signal processing unit 54 performs gamma correction, luminance adjustment, and chromaticity adjustment on the light emission gradation data for each pixel Px. For example, the image signal processing unit 54 uses the lookup table for performing various adjustments and the image signal input to the image signal processing unit 54 to adjust the emission gradation data for each pixel Px. In the light emission period, the image signal processing unit 54 outputs the adjusted light emission gradation data to the display data output unit 55 as display data Din. The image signal processing unit 54 separately generates non-emission gradation data for each pixel Px that does not emit EL elements during the non-emission period, as display data Din, and the generated display data Din is output to the display data output unit 55. Output.

The data driver 40 uses the display data Din input during the light emission period and generates the light emission voltage VD from the display data Din. The data driver 40 uses the display data Din input during the non-light emission period, and generates the non-light emission voltage VDN from the display data Din.

The data shift clock signal Clkd determines the timing at which the display data Din for each pixel Px is input from the display data output unit 55 to the data driver 40. Each time the data shift clock signal Clkd rises, the data driver 40 applies display data Din corresponding to the pixel Px in the first column, display data Din corresponding to the pixel Px in the second column,. Display data Din for each pixel Px is input in the order of corresponding display data Din. The data driver 40 associates the display data Din for each pixel Px with the data line Ld connected to the pixel Px in the clock cycle of the data shift clock signal Clkd.

The display shift clock signal Clks determines the cycle of switching the candidate to be selected and the cycle of switching the candidate to be supplied in the light emission period. In addition, the display shift clock signal Clks also determines the period for switching the candidate to be selected and the period for switching the candidate for supply in the non-light emitting period. Each time the display shift clock signal Clks rises, the selection driver 20 sets one scanning line Ls in the order of the first scanning line Ls, the second scanning line Ls,..., The m-th scanning line Ls. Select one by one. Each time the display shift clock signal Clks rises, the power driver 30 supplies one power line La in the order of the first power line La, the second power line La,..., The m-th power line La. Select one by one. The display clock cycle, which is the clock cycle of the display shift clock signal Clks, is sufficiently longer than the clock cycle of the data shift clock signal Clkd. For example, the display clock cycle is n times the clock cycle of the data shift clock signal Clkd.

The timing controller 52 generates a start pulse signal SP1, a start pulse signal SP2, and a latch pulse signal LP. The timing controller 52 inputs the start pulse signal SP1 and the latch pulse signal LP to the data driver 40. The timing controller 52 inputs the start pulse signal SP2 to the selection driver 20 and the power supply driver 30.

The start pulse signal SP1 is a control signal that controls the processing timing of the data driver 40, and controls the timing at which the display data Din for one row is input from the display data output unit 55 to the data driver 40. For each input of the start pulse signal SP1, the data driver 40 performs the display data Din corresponding to the pixel Px in the mth row and the first column to the display data Din corresponding to the pixel Px in the mth row and the nth column for each pixel Px. The display data Din is fetched for one line.

The latch pulse signal LP is a control signal for controlling the processing timing of the data driver 40, and controls the timing at which the data driver 40 holds the display data Din for one row. For each input of the latch pulse signal LP, the data driver 40 displays one row from the display data Din corresponding to the pixel Px in the mth row and the first column to the display data Din corresponding to the pixel Px in the mth row and the nth column. Holds display data Din.

The start pulse signal SP2 is a control signal for controlling the processing timing of the selection driver 20, and controls the timing for starting the selection of the selection target candidate every time the selection target candidate is switched m times. The start pulse signal SP2 is a control signal that controls the processing timing of the power supply driver 30, and controls the start timing of the supply target candidate switching every time the supply target candidate is switched m times. Each time the start pulse signal SP2 is input, the selection driver 20 sequentially switches from the first scanning line Ls to the m-th scanning line Ls as a selection target candidate. Each time the start pulse signal SP2 is input, the power supply driver 30 sequentially switches from the first power supply line La to the mth power supply line La as candidates for supply.

[Configuration of Selected Driver 20]
The configuration of the selection driver 20 will be described with reference to FIG. The configuration in which the power supply driver 30 selects the supply target candidate is the same as the configuration in which the selection driver 20 selects the selection target candidate. Therefore, in the following, the configuration of the selection driver 20 will be described in detail, and the configuration of the power supply driver 30 will be omitted.

As shown in FIG. 2, the control unit 50 inputs the start pulse signal SP2 and the display shift clock signal Clks to the shift register circuit 21. Each time the start pulse signal SP2 is input, the shift register circuit 21 generates an m-bit parallel signal including one selection target bit and outputs the parallel signal as a shift signal. For each input of the display shift clock signal Clks, the shift register circuit 21 shifts one selection target bit in the shift signal from the position corresponding to the pixel Px in the first row to the position corresponding to the pixel Px in the mth row. The pixels Px for one row are sequentially shifted.

The shift register circuit 21 inputs a shift signal to the level shifter circuit 22. The level shifter circuit 22 is a voltage adjustment circuit that connects the low voltage circuit and the high voltage circuit, and adjusts the voltage of the shift signal to the drive level of the buffer circuit 23. The level shifter circuit 22 inputs a drive level shift signal of the buffer circuit 23 to the buffer circuit 23. The buffer circuit 23 adjusts the voltage of the shift signal to the drive level of the pixel Px.

[Configuration of Data Driver 40]
The configuration of the data driver 40 will be described with reference to FIG.
As shown in FIG. 3, the data driver 40 includes a shift register circuit 41, a data register circuit 42, a data latch circuit 43, a voltage conversion circuit 44, and a buffer circuit 45. The shift register circuit 41, the data register circuit 42, and the data latch circuit 43 are configured as a low withstand voltage circuit, and the logic power supply 60 supplies a high level logic power supply voltage LVDD and a low level logic reference voltage LVSS. Apply to these circuits. The voltage conversion circuit 44 and the buffer circuit 45 are configured as a high voltage circuit, and the analog power supply 70 applies a high level analog power supply voltage DVSS and a low level analog reference voltage VEE to these circuits. Analog power supply voltage DVSS is set to a level equal to write voltage WDVSS and reference voltage ELVSS.

The control unit 50 inputs the start pulse signal SP1 and the data shift clock signal Clkd to the shift register circuit 41. The shift register circuit 41 generates an n-bit parallel signal including one selection target bit for each input of the start pulse signal SP1, and outputs the parallel signal as a shift signal. For each input of the data shift clock signal Clkd, the shift register circuit 41 sequentially shifts and outputs one selection target bit in the shift signal.

The control unit 50 inputs the display data Din to the data register circuit 42. The display data Din is, for example, gradation data composed of 8 bits. The data register circuit 42 includes n registers associated with each bit of the shift signal, and one register takes in display data Din for each pixel Px. The data register circuit 42 inputs the display data Din for each pixel Px to each register selected by one selection target bit. The data register circuit 42 selects all the registers by shifting one selection target bit, and takes the display data Din for one row into n registers.

The control unit 50 inputs the latch pulse signal LP to the data latch circuit 43. The data latch circuit 43 includes n data latches 43a associated with the registers of the data register circuit 42. Each of the n data latches 43a is electrically connected to a register different from the data register circuit 42. Each of the n data latches 43a holds display data Din stored in a register that is a connection destination, and repeats the holding for each latch pulse signal LP. Each of the n data latches 43 a inputs the display data Din held therein to the voltage conversion circuit 44. The data latch circuit 43 holds the display data Din for one row taken into the data register circuit 42 for each input of the latch pulse signal LP, and the display data Din for the held row is stored in the voltage conversion circuit. 44.

The voltage conversion circuit 44 includes n display DACs 44a which are linear voltage digital-analog conversion circuits. Each of the n display DACs 44a is electrically connected to different data latches 43a with respect to the data latch circuit 43 through different level shifters 46a. Each of the n display DACs 44a converts the display data Din held in the data latch 43a as a connection destination into an analog voltage. The display DAC 44a has linearity in the output analog voltage with respect to the input digital data. The analog voltage converted by the display DAC 44a is set between the analog power supply voltage DVSS applied from the analog power supply 70 and the analog reference voltage VEE.

The buffer circuit 45 includes n buffers 45a. Each of the n buffers 45 a is electrically connected to the display DAC 44 a different from the voltage conversion circuit 44. Each of the n buffers 45a is electrically connected to different data lines Ld. Each of the n buffers 45a amplifies the analog voltage generated by the display DAC 44a that is the connection destination to the drive level of the pixel circuit. Each of the n buffers 45a generates a light emission voltage VD corresponding to the display data Din for each pixel Px in the light emission period. Each of the n buffers 45a generates a non-light emitting voltage VDN corresponding to the display data Din for each pixel Px in the non-light emitting period.

[Configuration of Drive Circuit PCC]
The configuration of the drive circuit PCC will be described with reference to FIG.
As illustrated in FIG. 3, the pixel Px includes an EL element 11 and a drive circuit PCC that causes the EL element 11 to emit light. The drive circuit PCC includes three transistors Tr1 to Tr3 and a holding capacitor Cs. The transistors Tr1 to Tr3 are n-channel transistors.

In the sampling transistor Tr1, the source is electrically connected to the data line Ld, the drain is electrically connected to the anode of the EL element 11, and the gate is electrically connected to the scanning line Ls. When the selection voltage VgH is applied to the scanning line Ls, the sampling transistor Tr1 becomes conductive. On the other hand, when the non-selection voltage VgL is applied to the scanning line Ls, the sampling transistor Tr1 is turned off.

In the switching transistor Tr2, the source is electrically connected to the gate of the driving transistor Tr3, the drain is electrically connected to the power supply line La, and the gate is electrically connected to the gate of the sampling transistor Tr1. When the selection voltage VgH is applied to the scanning line Ls, the switching transistor Tr2 becomes conductive. On the other hand, when the non-selection voltage VgL is applied to the scanning line Ls, the switching transistor Tr2 is turned off.

In the driving transistor Tr3, a source that is an example of a connection end is electrically connected to the anode of the EL element 11, a drain that is an example of a power supply end is electrically connected to the drain of the switching transistor Tr2, and a gate is the switching transistor Tr2. Electrical connection to the source.

The holding capacitor Cs is electrically connected between the gate and source of the driving transistor Tr3. The storage capacitor Cs may be a parasitic capacitor formed between the gate and the source of the drive transistor Tr3, or another capacitor element may be connected in parallel to the parasitic capacitor.

The cathode of the EL element 11 is electrically connected to a ground voltage line Lb which is an example of a reference voltage line. The ground voltage line Lb is set to the reference voltage ELVSS, and the reference voltage ELVSS is at a high level with respect to the analog reference voltage VEE and is at a level equal to the analog power supply voltage DVSS. In the pixel Px, the EL element 11 includes the pixel capacitance Ce, and the data line Ld includes the parasitic capacitance Cp.

[Non-light emission voltage VDN]
The relationship between the light emission voltage VD and the non-light emission voltage VDN will be described with reference to FIG. FIG. 4 is a graph showing the relationship between the light emission voltage VD and the non-light emission voltage VDN associated with each other by the image signal processing unit 54.

As shown in FIG. 4, the non-light emission voltage VDN is associated with the light emission voltage VD. When the reference voltage ELVSS and the write voltage WDVSS are 0 V, and the polarity of the drive voltage ELVDD is positive, the polarity of the light emission voltage VD and the polarity of the non-light emission voltage VDN are both negative. The non-light emission voltage VDN is lower as the light emission voltage VD associated therewith is higher.

For example, when the light emission voltage VD is −10V, 0V is associated with the non-light emission voltage VDN, and when the light emission voltage VD is −8V, −2V is associated with the non-light emission voltage VDN. Further, when the light emission voltage VD is −2V, −8V is associated with the non-light emission voltage VDN, and when the light emission voltage VD is 0V, −10V is associated with the non-light emission voltage VDN.

-5V is an intermediate value in the range where the light emission voltage VD is set, and the non-light emission voltage VDN is an inverted voltage symmetrical to the light emission voltage VD with the intermediate value as a reference. The range in which the light emission voltage VD is set is appropriately set according to the reference voltage, the write voltage WDVSS, the drive voltage ELVDD, and the drive of the EL element 11, and is other than 0V to −10V. Also good.

Then, for each pixel Px in one frame, display data Din for generating the light emission voltage VD and display data Din for generating a non-light emission voltage VDN that is an inverted voltage of the light emission voltage VD are generated. Thus, the control unit 50 is configured. For example, the image signal processing unit 54 of the control unit 50 generates a difference value between the display data Din (light emission gradation data) for generating the light emission voltage VD and the maximum gradation value of the display data Din. Is provided. Then, every time the display signal Din for generating the light emission voltage VD is generated, the image signal processing unit 54 of the control unit 50 applies the display data Din to the difference circuit to generate the non-light emission voltage VDN. Display data Din (non-light emitting gradation data) is generated.

The operation of the drive circuit PCC to which the light emission voltage VD and the non-light emission voltage VDN are applied will be described with reference to FIGS.
As shown in FIG. 5, when the write voltage WDVSS is applied to the power supply line La and the selection voltage VgH is applied to the scanning line Ls, the sampling transistor Tr1 and the switching transistor Tr2 are in a conductive state. When the sampling transistor Tr1 and the switching transistor Tr2 are in a conductive state, the drive transistor Tr3 is driven in a saturation region. In this state, when the light emission voltage VD is applied to the data line Ld, the write voltage corresponding to the potential difference between the voltage of the power supply line La and the voltage of the data line Ld is the gate-source voltage Vgs of the drive transistor Tr3. Is held in the holding capacitor Cs.

At this time, since the light emission voltage VD is lower than the reference voltage ELVSS, the reverse voltage of the EL element 11 is applied to the EL element 11. Further, since the light emission voltage VD is at a lower level than the write voltage WDVSS, the current Ie flowing through the drive transistor Tr3 does not flow to the EL element 11 but is drawn toward the data line Ld.

As shown in FIG. 6, when the non-selection voltage VgL is applied to the scanning line Ls while the write voltage for light emission is held in the holding capacitor Cs, the sampling transistor Tr1 and the switching transistor Tr2 are It is a non-conducting state. In this state, when the drive voltage ELVDD is applied to the power supply line La, the drive voltage ELVDD is higher than the reference voltage ELVSS, so that the drive transistor Tr3 has a drain current corresponding to the gate-source voltage Vgs. It flows in the EL element 11. At this time, the drain current in the drive transistor Tr3 varies in the saturation region according to the difference between the gate-source voltage Vgs and the threshold voltage Vth in the drive transistor Tr3. As a result, a drain current corresponding to the difference between the write voltage held in the holding capacitor Cs and the threshold voltage Vth in the drive transistor Tr3 flows in the EL element 11.

As shown in FIG. 7, when the write voltage WDVSS is applied to the power supply line La and the selection voltage VgH is applied to the scanning line Ls, the sampling transistor Tr1 and the switching transistor Tr2 are in a conductive state. When the sampling transistor Tr1 and the switching transistor Tr2 are in a conductive state, the drive transistor Tr3 is driven in a saturation region. In this state, when the non-light emission voltage VDN is applied to the data line Ld, the write voltage corresponding to the potential difference between the voltage of the power supply line La and the voltage of the data line Ld is the gate-source voltage of the drive transistor Tr3. Vgs is held in the holding capacitor Cs.

At this time, since the non-light-emitting voltage VDN is at a lower level than the reference voltage ELVSS, the reverse voltage of the EL element 11 is applied to the EL element 11. Further, since the non-light emitting voltage VDN is at a lower level than the write voltage WDVSS, the current Iue flowing through the drive transistor Tr3 does not flow to the EL element 11 but is drawn toward the data line Ld.

Here, in each of the plurality of pixels Px included in the EL display device, the application of the light emission voltage VD is repeated during the period in which the image is displayed. Since the application of the light emission voltage VD having a single polarity is repeated between the gate and the source of the drive transistor Tr3, the threshold voltage shift between the gate and the source proceeds in the drive transistor Tr3. Since the non-light-emitting voltage VDN has the same polarity as the light-emitting voltage VD, the threshold voltage shift proceeds even when the non-light-emitting voltage VDN is applied. At this time, since the non-light emission voltage VDN is an inverted voltage of the light emission voltage VD, the gate-source voltage Vgs of the drive transistor Tr3 is lower as the previous light emission voltage VD is higher. Therefore, in each of the plurality of pixels Px, the larger the shift due to the application of the light emission voltage VD, the smaller the shift due to the application of the non-light emission voltage VDN. The shift due to the application of the light emission voltage VDN is increased. As a result, the shift of the threshold voltage is made uniform in a plurality of pixels Px having different light emission voltages VD.

As shown in FIG. 8, when the non-selection voltage VgL is applied to the scanning line Ls in a state where the non-emission write voltage is held in the holding capacitor Cs, the sampling transistor Tr1 and the switching transistor Tr2 Is a non-conductive state. In this state, when the write voltage WDVSS is continuously applied to the power supply line La, no current flows through the drive transistor Tr3 as in the above-described write. Further, since the source of the driving transistor Tr3 after the writing operation is at a lower level than the reference voltage ELVSS, the reverse voltage is continuously applied to the EL element 11.

[Operation of EL display device]
With reference to FIG. 9 and FIG. 10, the operation during the light emission period of the EL display device and the operation during the non-light emission period of the EL display device will be described. First, the operation during the light emission period of the EL display device will be described.

As shown in FIG. 9, at timing td1, the control unit 50 inputs a start pulse signal SP1 to the data driver 40. Thereby, the shift register circuit 41 inputs a shift signal to the data register circuit 42, and the data register circuit 42 takes in the display data Din of the first row. Then, the control unit 50 inputs the start pulse signal SP2 to the selection driver 20 and the power supply driver 30.

At timing td2, the control unit 50 applies the selection voltage VgH to the scanning line Ls in the first row, and changes each sampling transistor Tr1 in the first row and each switching transistor Tr2 in the first row to a conductive state. Further, the control unit 50 inputs the latch pulse signal LP to the data driver 40, thereby holding the display data Din of the first row in each data latch 43a. The display data Din in the first row held in the n data latches 43a is converted into an analog voltage by the n display DACs 44a through the n level shifters 46a, and applied to each data line Ld as the light emission voltage VD. Is done.

On the other hand, the control unit 50 continues to apply the write voltage WDVSS to the power supply line La in the first row. As a result, the gate-source voltage Vgs of each drive transistor Tr3 in the first row becomes a value corresponding to the difference between the write voltage WDVSS and the light emission voltage VD, and is held in the holding capacitor Cs as the write voltage. As a result, the control unit 50 holds the gate-source voltage Vgs in the forward direction of the drive transistor Tr3 for each pixel Px in the first row, and drives each drive transistor Tr3 in the first row in the saturation region. In a ready state, the light emission writing operation for each pixel Px in the first row is completed.

During this time, the control unit 50 inputs the start pulse signal SP1 to the data driver 40 again. As a result, the shift register circuit 41 inputs the shift signal to the data register circuit 42 and takes in the display data Din of the second row from the control unit 50.

At timing td3, the control unit 50 applies the non-selection voltage VgL to the scanning line Ls in the first row, and turns off the sampling transistors Tr1 in the first row and the switching transistors Tr2 in the first row. Change. Further, the control unit 50 applies the drive voltage ELVDD to the power supply line La in the first row. As a result, each driving transistor Tr3 in the first row has a drain corresponding to the difference between the write voltage held in the holding capacitor Cs in the first row and the threshold voltage Vth in the driving transistor Tr3 to which it is connected. A current is supplied to the corresponding EL element 11. Accordingly, the control unit 50 starts a light emission operation for each pixel Px in the first row.

During this time, the control unit 50 applies the selection voltage VgH to the scanning line Ls in the second row, and applies the write voltage WDVSS to the power supply line La in the second row, thereby performing each sampling in the second row. The transistor Tr1 and each switching transistor Tr2 in the second row are changed to a conductive state. Further, the control unit 50 inputs the latch pulse signal LP to the data driver 40 again, and holds the display data Din of the second row in each data latch 43a. The display data Din in the second row held in each data latch 43a is converted into an analog voltage by the display DAC 44a through the level shifter 46a and input to the data line Ld as the light emission voltage VD. The gate-source voltage Vgs of each drive transistor Tr3 in the second row becomes a value corresponding to the difference between the write voltage WDVSS and the light emission voltage VD, and is held as the write voltage in each holding capacitor Cs in the second row. Is done. Thus, the control unit 50 finishes the writing operation for each pixel Px in the second row.

Thereafter, the light emission process including the light emission write operation and the light emission operation is performed in this order for each row of the pixels Px, and the light emission process is sequentially repeated from the first line to the nth line in the display clock cycle. . As a result, the control unit 50 displays the gradation-represented image as one subframe.

Next, an operation during a non-light emitting period of the EL display device will be described.
As illustrated in FIG. 10, the control unit 50 inputs a start pulse signal SP1 to the data driver 40 at timing ta1. Thereby, the shift register circuit 41 inputs the shift signal to the data register circuit 42 and takes in the display data Din of the first row into the data register circuit 42. Then, the control unit 50 inputs the start pulse signal SP2 to the selection driver 20 and the power supply driver 30.

At timing ta2, the control unit 50 applies the selection voltage VgH to the scanning line Ls in the first row, and changes each sampling transistor Tr1 in the first row and each switching transistor Tr2 in the first row to a conductive state. Further, the control unit 50 inputs the latch pulse signal LP to the data driver 40 and holds the display data Din of the first row in the data latch 43a. The display data Din held in the data latch 43a is converted into an analog voltage by the display DAC 44a through the level shifter 46a and applied to the data line Ld as the non-light emitting voltage VDN.

At this time, the control unit 50 applies the write voltage WDVSS to the power supply line La in the first row. The gate-source voltage Vgs of each drive transistor Tr3 in the first row has a value corresponding to the difference between the write voltage WDVSS and the non-light emission voltage VDN, and is held in the holding capacitor Cs as the write voltage. Thus, the control unit 50 causes the storage capacitor Cs to hold the gate-source voltage Vgs corresponding to the inverted voltage of the light emission voltage VD applied immediately before, for each pixel Px in the first row. Each of the driving transistors Tr3 is set in a state where it can be driven in the saturation region, and the non-light-emission writing operation for each pixel Px in the first row is completed.

During this time, the control unit 50 inputs the start pulse signal SP1 to the data driver 40 again. As a result, the shift register circuit 41 inputs the shift signal to the data register circuit 42 and takes in the display data Din of the second row to the data register circuit 42.

At timing td3, the control unit 50 applies the non-selection voltage VgL to the scanning line Ls in the first row, and turns off the sampling transistors Tr1 in the first row and the switching transistors Tr2 in the first row. Change. The control unit 50 continues to apply the write voltage WDVSS to the power supply line La in the first row. As a result, the control unit 50 causes each drive transistor Tr3 in the first row to write to the write voltage held in the holding capacitor Cs in the first row, that is, between the gate and source corresponding to the inverted voltage of the previous light emission voltage VD. Continue to apply voltage Vgs.

During this time, the control unit 50 applies the selection voltage VgH to the scanning line Ls in the second row, and applies the write voltage WDVSS to the power supply line La in the second row, thereby performing each sampling in the second row. The transistor Tr1 and each switching transistor Tr2 in the second row are changed to a conductive state. Further, the control unit 50 inputs the latch pulse signal LP to the data driver 40 again, and causes each data latch 43a to hold the display data Din on the second row. The display data Din in the second row held in the data latch 43a is converted into an analog voltage by the display DAC 44a through the level shifter 46a and output to the data line Ld as the non-light emission voltage VDN of each column. Then, the control unit 50 sets the gate-source voltage Vgs of each driving transistor Tr3 in the second row to a value corresponding to the difference between the write voltage WDVSS and the non-light-emitting voltage VDN, and sets the storage capacitance Cs in the second row. It is held as a write voltage. Thereby, the control unit 50 finishes the non-light-emission writing operation for each pixel Px in the second row.

Thereafter, a non-emission process in which a non-emission writing operation and a non-emission operation are performed is performed in this order for each row of the pixels Px, and such non-emission period is displayed in order from the first row to the n-th row. Repeated with clock period. Thereby, an image expressed in black is displayed as one subframe.

According to the first embodiment, the advantages listed below can be obtained.
(1) In each of the plurality of drive transistors Tr3, the gate-source voltage Vgs is higher when the EL element 11 emits light and is lower when the EL element 11 is not emitting light. Therefore, it is possible to suppress the threshold voltage shift of the driving transistor Tr3 from being different for each pixel Px.

(2) For each frame composed of a light emission period and a non-light emission period, the higher the light emission voltage VD, the lower the non-light emission voltage VDN. Therefore, the shift of the threshold voltage Vth of the drive transistor Tr3 differs for each pixel Px can be suppressed for each frame which is the shortest repetition period in display. As a result, in the plurality of pixels Px, the threshold voltage Vth of the drive transistor Tr3 is made uniform in the shortest repetition period in display.

(3) An inversion voltage symmetrical to the light emission voltage VD is used as the non-light emission voltage VDN. Therefore, the voltage applied between the gate and source of the drive transistor Tr3 is uniform in the plurality of pixels Px through one light emission period and one non-light emission period. Therefore, the effect of suppressing the threshold voltage shift of the drive transistor Tr3 from being different for each pixel Px is further enhanced.

(4) The write voltage for light emission is set by applying the light emission voltage VD through the sampling transistor Tr1 to the source of the drive transistor Tr3. Also, the non-emission write voltage is set by applying the non-emission voltage VDN through the sampling transistor Tr1 to the source of the drive transistor Tr3. The setting of the light emission voltage VD and the setting of the non-light emission voltage VDN are realized by driving the sampling transistor. Therefore, the configuration required for the write operation for light emission and the configuration required for the write operation for non-light emission can be shared.

(5) The conduction of the sampling transistor Tr1 and the conduction of the switching transistor Tr2 are synchronized, and the non-conduction of the sampling transistor Tr1 and the non-conduction of the switching transistor Tr2 are synchronized. Therefore, in each of the write operation for light emission, the light emission operation, the write operation for non-light emission, and the non-light emission operation, the voltage change smoothly proceeds at the gate, source, and drain of the drive transistor Tr3. .

[Second Embodiment]
With reference to FIGS. 11 to 15, a second embodiment in which the EL display device and the driving method of the EL display device according to the present disclosure are embodied will be described. Note that the EL display device of the second embodiment and the driving method of the EL display device are based on the relationship between the light emission voltage VD and the non-light emission voltage VDN associated with each other in the control unit 50, and the EL display device of the first embodiment. This is different from the driving method of the EL display device. Therefore, in the following, the relationship between the light emission voltage VD and the non-light emission voltage VDN will be described in detail, and the same components as those described in the first embodiment will be denoted by the same reference numerals and detailed description thereof will be given. Description is omitted.

First, as one of the characteristics of the EL element 11, the relationship between the forward voltage applied to the EL element 11 and the drive current flowing through the EL element 11 will be described. In FIG. 11, the current that flows along with the light emission operation of the EL element 11 is the drive current of the EL element 11, and the drive voltage applied to the EL element 11 in the direction in which the drive current flows through the EL element 11. Is the forward voltage.

As shown in FIG. 11, when the forward voltage of the EL element 11 is equal to or lower than the light emission start voltage Vels, the drive current of the EL element 11 hardly flows. And even if the drive current of the EL element 11 flows, the magnitude of the drive current is not enough to cause the EL element 11 to emit light. After all, when the forward voltage of the EL element 11 is equal to or lower than the light emission start voltage Vels, the EL element 11 does not emit light.

On the other hand, when the forward voltage of the EL element 11 exceeds the light emission start voltage Vels, the drive current of the EL element 11 is larger as the forward voltage is higher. When the forward voltage of the EL element 11 exceeds the light emission start voltage Vels, the magnitude of the drive current of the EL element 11 is such that the EL element 11 emits light, and the higher the forward voltage, The brightness of the light generated by 11 is high.

In short, if the voltage applied to the EL element 11 is a reverse voltage, the EL element 11 does not emit light, and even if the voltage applied to the EL element 11 is a forward voltage, the order is equal to or lower than the light emission start voltage Vels. At the directional voltage, the EL element 11 also does not emit light. When the forward voltage of the EL element 11 exceeds the light emission start voltage Vels, the EL element 11 emits light.

Next, a correlation between voltages applied to the scanning line Ls, the power supply line La, and the data line Ld will be described using the light emission start voltage Vels with reference to the ground voltage. In FIG. 12, as an example of voltages applied to the scanning line Ls, the power supply line La, and the data line Ld, the reference voltage ELVSS is set to the ground voltage, and the reference voltage ELVSS and the write voltage WDVSS are A configuration is shown in which are equal potentials.

As shown in FIG. 12, the write voltage WDVSS applied to the power supply line La is set to the same potential as the reference voltage ELVSS applied to the ground voltage line Lb. The light emission voltage VD applied to the data line Ld is different for each gradation indicated by the gradation data. In the range of the light emission voltage VD, an intermediate value between the lowest gradation value VDL, which is the level closest to the write voltage WDVSS, and the highest gradation value VDH, which is the level where the potential difference between the write voltage WDVSS is the largest, An intermediate value M is set. In the range of the light emission voltage VD, a switching value Vp is set as a value between the maximum gradation value VDH and the intermediate value M.

The non-light emitting voltage applied to the data line Ld is composed of a first non-light emitting voltage VDN1 and a second non-light emitting voltage VDN2. The first non-emission voltage VDN1 is an inverted voltage with respect to a voltage between the lowest gradation value VDL and the switching value Vp in the emission voltage VD. The second non-light emission voltage VDN2 is higher than the reference voltage ELVSS and the write voltage WDVSS, and is set to a constant value.

The polarity of the first non-light-emitting voltage VDN1 based on the write voltage WDVSS is the same as the polarity of the light-emitting voltage VD based on the write voltage WDVSS. The polarity of the second non-light emission voltage VDN2 with respect to the write voltage WDVSS is different from the polarity of the light emission voltage VD with respect to the write voltage WDVSS, and these have opposite polarities. The polarity of the light emission voltage VD with respect to the write voltage WDVSS is negative, and the polarity of the first non-light emission voltage VDN1 with respect to the write voltage WDVSS is also negative. On the other hand, the polarity of the second non-emission voltage VDN2 with the write voltage WDVSS as a reference is positive.

Note that the polarity of the first non-light-emitting voltage VDN1 with respect to the write voltage WDVSS is negative, as is the polarity of the non-selection voltage VgL with respect to the write voltage WDVSS. The polarity of the second non-light-emitting voltage VDN2 with respect to the write voltage WDVSS is as positive as the polarity of the selection voltage VgH with reference to the write voltage WDVSS. The second non-light emitting voltage VDN2 is lower than the level of the driving voltage ELVDD and the selection voltage VgH, and the polarity of the driving voltage ELVDD with the second non-light emitting voltage VDN2 as a reference is the second non-light emitting voltage VDN2. Is different from the polarity of the write voltage WDVSS.

The polarity of the light emission voltage VD with respect to the write voltage WDVSS is negative, as is the polarity of the non-selection voltage VgL with reference to the write voltage WDVSS. The level of the light emission voltage VD is set between the non-selection voltage VgL and the write voltage WDVSS.

Incidentally, the reference voltage ELVSS may be higher than the ground voltage or may be lower than the ground voltage. Further, the write voltage WDVSS may be at a lower level than the reference voltage ELVSS.

Referring to FIG. 13, the relationship between the light emission voltage VD and the first non-light emission voltage VDN1 and the relationship between the light emission voltage VD and the second non-light emission voltage VDN2 will be described. FIG. 13 is a graph showing the relationship between the light emission voltage VD and the first non-light emission voltage VDN1 associated with the image signal processing unit 54 and the relationship between the light emission voltage VD and the second non-light emission voltage VDN2 associated with the image signal processing unit 54. It is.

As shown in FIG. 13, the first non-light emission voltage VDN1 corresponds to the non-light emission voltage when the light emission voltage VD is equal to or lower than the switching value Vp. That is, the first non-light emission voltage VDN1 is associated with a value of the light emission voltage VD that is not less than the switching value Vp and not more than the lowest gradation value VDL. For example, when the light emission voltage VD is 0V of the lowest gradation value VDL, -9.2V is associated as the first non-light emission voltage VDN1, and when the light emission voltage VD is -5V of the intermediate value M, the first non-light emission voltage VDL The light emission voltage VDN1 is associated with −4.2V. When the light emission voltage VD is the switching value Vp of −9.2V, 0V is associated with the first non-light emission voltage VDN1. The range in which the light emission voltage VD is set is appropriately set according to the reference voltage, the write voltage WDVSS, the drive voltage ELVDD, and the drive of the EL element 11, and is other than 0V to −10V. Also good.

When a light emission voltage VD that is not less than the switching value Vp and not more than the lowest gradation value VDL is required for each pixel Px in one frame, display data Din for generating the light emission voltage VD is generated. The control unit 50 is configured. Further, when a light emission voltage VD not less than the switching value Vp and not more than the lowest gradation value VDL is required for each pixel Px in one frame, the first non-light emission voltage VDN1 that is an inverted voltage of the light emission voltage VD is generated. The control unit 50 is configured to generate display data Din for the purpose.

The second non-emission voltage VDN2 corresponds to a non-emission voltage when the emission voltage VD is higher than the switching value Vp. That is, the second non-emission voltage VDN2 is associated with the value of the emission voltage VD that is greater than or equal to the maximum gradation value VDH and less than the switching value Vp. For example, when the light emission voltage VD is -10V of the maximum gradation value VDH, 3V is associated as the second non-light emission voltage VDN2, and when the light emission voltage VD is a value closest to the switching value Vp, this is also 3 V is associated as the second non-light-emitting voltage VDN2.

When a light emission voltage VD that is greater than or equal to the maximum gradation value VDH and less than the switching value Vp is required for each pixel Px in one frame, display data Din for generating the light emission voltage VD is generated. The control unit 50 is configured. Further, when a light emission voltage VD that is greater than or equal to the maximum gradation value VDH and less than the switching value Vp is required for each pixel Px in one frame, a display for generating a second non-light emission voltage VDN2 of 3V that is a constant value. The control unit 50 is configured so that the data Din is generated.

For example, the image signal processing unit 54 of the control unit 50 generates a difference value between the display data Din (light emission gradation data) for generating the light emission voltage VD and the maximum gradation value of the display data Din. Is provided. Further, the image signal processing unit 54 of the control unit 50 includes a comparison circuit that compares the display data Din for generating the light emission voltage VD with a switching gradation value that is a gradation value corresponding to the switching value Vp. The image signal processing unit 54 of the control unit 50 compares the display data Din with the switching gradation value every time the display data Din for generating the light emission voltage VD is generated. When the display data Din is equal to or lower than the switching gradation value, the image signal processing unit 54 of the control unit 50 applies the display data Din to the difference circuit, and the first data as in the first embodiment. Display data Din (non-light emission gradation data) for generating the non-light emission voltage VDN1 is generated. On the other hand, when the display data Din is higher than the switching gradation value, the image signal processing unit 54 of the control unit 50 displays the display data Din (non-emission gradation data) for generating the second non-emission voltage VDN2. ) Is generated.

The second non-light emission voltage VDN2 is at a level equal to or lower than the light emission start voltage Vels. Based on the drive mode of the EL element 11 by the drive circuit PCC in the non-light emission period and the light emission start voltage Vels described below, Is set to

As shown in FIG. 14, when the write voltage WDVSS is applied to the power supply line La and the selection voltage VgH is applied to the scanning line Ls, the sampling transistor Tr1 and the switching transistor Tr2 are in a conductive state. When the sampling transistor Tr1 and the switching transistor Tr2 are in a conductive state, the drive transistor Tr3 is driven in a saturation region. In this state, when the second non-light-emitting voltage VDN2 is applied to the data line Ld, the write voltage corresponding to the potential difference between the voltage of the power supply line La and the voltage of the data line Ld is the gate-source of the drive transistor Tr3. The voltage Vgs is held in the holding capacitor Cs.

At this time, since the second non-light-emitting voltage VDN2 is higher than the write voltage WDVSS, no current flows through the drive transistor Tr3. On the other hand, since the second non-light emitting voltage VDN2 is higher than the reference voltage ELVSS, the forward voltage of the EL element 11 is applied to the EL element 11.

Here, the second non-light emission voltage VDN2 sets a potential difference equal to or lower than the light emission start voltage Vels between the source of the drive transistor Tr3 and the reference voltage ELVSS at the time of the write operation in the non-light emission write operation. If the potential difference between the source of the driving transistor Tr3 and the reference voltage ELVSS during the writing operation is equal to or lower than the light emission start voltage Vels, even if the voltage applied to the EL element 11 is a forward voltage, the EL The element 11 does not emit light.

As shown in FIG. 15, when the non-selection voltage VgL is applied to the scanning line Ls with the non-emission write voltage held in the holding capacitor Cs, the sampling transistor Tr1 and the switching transistor Tr2 Is a non-conductive state. In this state, when the write voltage WDVSS is continuously applied to the power supply line La, no current flows through the drive transistor Tr3 as in the above-described write operation. On the other hand, since the source of the drive transistor Tr3 after the writing operation is at a level higher than the reference voltage ELVSS, the forward voltage is continuously applied to the EL element 11. The storage capacitor Cs is discharged when a current that does not cause the EL element 11 to emit light flows through the EL element 11.

[Operation of EL display device]
Next, an operation during a non-light emitting period of the EL display device will be described.
First, the control unit 50 applies the selection voltage VgH to the scanning line Ls in the first row, changes the sampling transistors Tr1 in the first row and the switching transistors Tr2 in the first row into a conductive state, and generates a non-light emitting voltage. Is applied to the data line Ld. At this time, the control unit 50 applies the write voltage WDVSS to the power supply line La in the first row. The gate-source voltage Vgs of each driving transistor Tr3 in the first row becomes a value corresponding to the difference between the write voltage WDVSS and the non-light-emitting voltage VDN, and is held in the holding capacitor Cs as the write voltage.

At this time, when the light emission voltage VD in the light emission period in one pixel Px is not less than the switching value Vp and not more than the minimum gradation value VDL, the control unit 50 performs the light emission voltage in the non-light emission period following the light emission period. The data driver 40 is caused to generate a first non-light-emitting voltage VDN1 that is an inverted voltage of VD. On the other hand, when the light emission voltage VD in the light emission period in one pixel Px is equal to or higher than the maximum gradation value VDH and lower than the switching value Vp, the control unit 50 is constant in the non-light emission period following the light emission period. The data driver 40 generates the second non-light-emitting voltage VDN2 that is a value.

As a result, when the light emission voltage VD is not less than the switching value Vp and not more than the minimum gradation value VDL for each pixel Px in the first row, the control unit 50 performs gate-- corresponding to the inverted voltage of the immediately preceding light emission voltage VD. The source voltage Vgs is held in the holding capacitor Cs, and the non-light-emission writing operation for each pixel Px in the first row is completed. Further, when the light emission voltage VD is greater than or equal to the maximum gradation value VDH and less than the switching value Vp for each pixel Px in the first row, the control unit 50 performs the second non-reduction regardless of the value of the immediately preceding light emission voltage VD. The gate-source voltage Vgs corresponding to the light emission voltage VDN2 is held in the storage capacitor Cs, and the writing operation for non-light emission for each pixel Px in the first row is completed.

According to the second embodiment, the advantages listed below can be obtained.
(1) When the light emission voltage VD is higher than the switching value Vp, the storage capacitor Cs holds the second non-light emission voltage VDN2 having a polarity different from that of the light emission voltage VD. Therefore, when the shift of the threshold voltage Vth of the driving transistor Tr3 proceeds excessively in the specific pixel Px, the shift of the threshold voltage Vth is suppressed for the specific pixel Px. As a result, the range in which the effect of suppressing the shift of the threshold voltage Vth of the drive transistor Tr3 from being different for each pixel Px is expanded with respect to the degree of shift of the threshold voltage Vth.

(2) In the drive circuit PCC to which the second non-emission voltage VDN2 is applied, the storage capacitor Cs is discharged through the EL element 11. Therefore, when the operation of the EL display device is switched from the non-light emitting period to the light emitting period, it is possible to suppress a sudden change in the potential difference held by the storage capacitor Cs.

[Third Embodiment]
With reference to FIGS. 16 to 26, a third embodiment in which the EL display device and the driving method of the EL display device according to the present disclosure are embodied will be described. The EL display device of the third embodiment and the driving method of the EL display device are the EL display device of the first embodiment, the driving method of the EL display device, the EL display device of the second embodiment, and A detection operation for detecting the threshold voltage Vth of the drive transistor Tr3 and a detection step are further added to the driving of the EL display device. Therefore, in the following, the detection operation and the detection process will be described in detail, and the configuration similar to the configuration described in the first embodiment and the configuration similar to the configuration described in the second embodiment will be described. Are given the same reference numerals and their detailed description is omitted.

[Configuration of Control Unit 50]
As shown in FIG. 16, the timing controller 52 generates a data shift clock signal Clkd, a display shift clock signal Clks, and a detection shift clock signal Clkr. The timing controller 52 outputs the data shift clock signal Clkd to the data driver 40, outputs the display shift clock signal Clks to the selection driver 20 and the power supply driver 30, and outputs the detection shift clock signal Clkr to the selection driver 20 and the power supply. Output to the driver 30.

The detection shift clock signal Clkr determines a cycle in which selection candidates are switched in the detection operation. Each time the detection shift clock signal Clkr rises, the selection driver 20 applies the selection voltage VgH in the order of the first scanning line Ls, the second scanning line Ls,..., The m-th scanning line Ls. Select one candidate at a time. Each time the shift clock signal Clkr for detection rises, the power supply driver 30 supplies one power supply line La in the order of the first power supply line La, the second power supply line La,..., The mth power supply line La. Select one by one. The detection clock cycle that is the clock cycle of the detection shift clock signal Clkm is preferably sufficiently shorter than the display cycle. For example, the detection clock cycle is preferably the same as the clock cycle of the data shift clock signal Clkd.

In the light emission period, the selection driver 20 scans the selection target candidates in the display clock cycle, and in the non-light emission period, the selection driver 20 scans the selection target candidates in the display clock cycle. On the other hand, in the detection operation, the selection driver 20 scans the selection target candidates in the detection clock cycle. In the light emission period, the power supply driver 30 scans the supply target candidates in the display clock cycle, and also scans the supply target candidates in the display clock cycle in the non-light emission period. On the other hand, in the detection operation, the power supply driver 30 scans the supply target candidates at the detection clock cycle.

The detection shift clock signal Clkr includes a shift standby portion in which the low level is maintained only during the detection period while the high level and the low level are repeated in the detection clock cycle. The timing at which the shift standby portion is output is shifted every time the detection shift clock signal Clkr is output, that is, every time a detection operation is performed.

For example, in this detection operation, the detection shift clock signal Clkr repeats the high level and the low level q times (1 ≦ q ≦ m) in the clock cycle, and then continues the shift standby part. On the other hand, in the next detection operation, the detection shift clock signal Clkr repeats the high level and the low level q + 1 times (1 ≦ q ≦ m), and then continues the shift standby portion. Thus, in the current detection operation, the first scanning line Ls to the qth scanning line Ls are sequentially switched in the detection clock cycle as candidates for selection. After the detection period elapses, the q + 1th scanning line Ls to the mth scanning line Ls are sequentially switched again in the detection clock cycle as selection candidates. In the next detection operation, the first scanning line Ls to the q + 1th scanning line Ls are sequentially switched in the detection clock cycle as selection candidates. Then, after the detection period has elapsed, from the (q + 2) -th scanning line Ls to the m-th scanning line Ls are sequentially switched in the detection clock cycle as candidates for selection.

The timing controller 52 generates a start pulse signal SP1, a start pulse signal SP2, a latch pulse signal LP, and a mask pulse signal MP. The timing controller 52 inputs the start pulse signal SP1 and the latch pulse signal LP to the data driver 40. The timing controller 52 inputs the start pulse signal SP <b> 2 and the mask pulse signal MP to the selection driver 20, the power supply driver 30, and the image signal processing unit 54.

The start pulse signal SP2 is a control signal for controlling the processing timing of the selection driver 20, and switches the shift clock signal used for switching the candidate to be selected between the display clock cycle and the detection clock cycle. The start pulse signal SP2 is a control signal for controlling the processing timing of the power supply driver 30, and switches the shift clock signal used for switching the candidate to be supplied between the display clock cycle and the detection clock cycle. The timing controller 52 switches the shift clock signal used for switching the candidate to be selected from the display clock cycle to the detection clock cycle every time the start pulse signal SP2 is input a set number of times. The timing controller 52 switches the shift clock signal used for switching the candidate to be supplied from the display clock cycle to the detection clock cycle every time the start pulse signal SP2 is input a set number of times.

In the third embodiment, the set number of times is set to 3, and the timing controller 52 changes the shift clock signal from the display clock cycle to the detection clock cycle every time the start pulse signal SP2 is input three times. . For example, when the 3n-th start pulse signal SP2 is input, the m scanning lines Ls are sequentially switched in the display clock cycle as candidates for selection, and the light-emission writing operation and the light-emission operation are advanced. Next, in response to the input of the 3n + 1th start pulse signal SP2, the m scanning lines Ls are sequentially switched in the display clock cycle as candidates for selection, and the writing operation for non-light emission and the non-light emission operation are advanced. . In response to the input of the 3n + 2th start pulse signal SP2, the m scanning lines Ls are sequentially switched in the detection clock cycle as candidates for selection, and the detection operation proceeds.

The mask pulse signal MP is a control signal for controlling the processing timing of the selection driver 20, and controls the output of the shift signal generated by the selection driver 20. When the mask pulse signal MP is at a high level, the selection driver 20 applies the selection voltage VgH to one of the scanning lines Ls based on the shift signal generated by the selection driver 20. On the other hand, when the mask pulse signal MP is at the low level, the selection driver 20 applies the non-selection voltage VgL to all the scanning lines Ls regardless of the shift signal generated by the selection driver 20.

The mask pulse signal MP is normally set to a high level, and every time the start pulse signal SP2 is output a set number of times, the mask pulse signal MP is switched from the high level to the low level, and the high level is maintained for the detection period. Including parts. The output timing of the mask release portion is synchronized with the output of the shift standby portion and is shifted every time a detection operation is performed.

For example, in this detection operation, the high level and the low level are repeated q times (1 ≦ q ≦ m) in the detection shift clock signal Clkr, and then the mask release portion is output. On the other hand, in the next detection operation, the high level and the low level are repeated q + 1 times (1 ≦ q ≦ m) in the detection shift clock signal Clkr, and then the mask release portion is output. Thus, in the current detection operation, first, the first scanning line Ls to the qth scanning line Ls are sequentially switched in the detection clock cycle as candidates for selection. During this period, application of the selection voltage VgH to the scanning line Ls is prohibited. Next, in the detection period in which switching of the candidate for selection is stopped, the selection voltage VgH is applied to the scanning line Ls in the qth row that is the candidate at that time. On the other hand, in the next detection operation, first, the first scanning line Ls to the (q + 1) th scanning line Ls are scanned as detection target candidates in the detection clock cycle. During this period, application of the selection voltage VgH to the scanning line Ls is prohibited. Next, in the detection period in which the selection of the candidate to be selected is stopped, the selection voltage VgH is applied to the scanning line Ls of the q + 1th row that is the candidate at that time.

The storage unit 53 includes a storage area of m rows × n columns associated with each of the plurality of pixels Px. The storage unit 53 takes in the detection data Dout from the data driver 40. The detection data Dout is data related to the threshold voltage Vth for each pixel Px, for example, 8-bit data. The storage unit 53 stores detection data Dout for each pixel Px in a storage area associated with the pixel Px. The storage unit 53 stores each time data in a storage area associated with the pixel Px, and updates the detection data Dout.

The image signal processing unit 54 reads the detection data Dout for each pixel Px stored in the storage unit 53. The image signal processing unit 54 performs an addition / subtraction operation on the gradation data for light emission for each pixel Px based on the detection data Dout for each pixel Px, and outputs the result as display data Din for each pixel Px. The image signal processing unit 54 generates non-light emitting gradation data for each pixel Px using the display data Din subjected to the addition / subtraction calculation.

[Configuration of Selected Driver 20]
The configuration of the selection driver 20 will be described with reference to FIG. The configuration for selecting the supply target candidate in the power supply driver 30 is the same as the configuration for selecting the selection target candidate in the selection driver 20. Therefore, in the following, the configuration of the selection driver 20 will be described in detail, and the configuration of the power supply driver 30 will be omitted.

As shown in FIG. 16, the control unit 50 inputs the detection shift clock signal Clkr to the shift register circuit 21. The shift register circuit 21 sequentially shifts one selection target bit in the shift signal line by line from the first line to the m-th line for every input of the detection shift clock signal Clkr.

The control unit 50 inputs the mask pulse signal MP to the shift register circuit 21. When the mask pulse signal MP is at high level, the shift register circuit 21 outputs a shift signal. On the other hand, when the mask pulse signal MP is at the low level, the shift register circuit 21 outputs a shift signal that does not include the selection target bit. When the shift clock signal is the display shift clock signal Clks, the shift register circuit 21 outputs a shift signal including the selection target bit based on the mask pulse signal MP being at a high level. On the other hand, when the shift clock signal is the detection shift clock signal Clkr, the shift register circuit 21 shifts the selection target bit not included based on the fact that the mask pulse signal MP is at a low level in a period other than the detection period. Output a signal.

Control of such shift signal output is performed, for example, by connecting m logical product circuits corresponding to each bit of the shift signal to the input terminal of the shift register circuit 21, and mask pulse signal MP to each of the m logical product circuits. This is realized by inputting.

[Configuration of Data Driver 40]
The configuration of the data driver 40 will be described with reference to FIG.
As shown in FIG. 17, the data latch circuit 43 includes n data latches 43a, n input switches SW1 connected to the input terminals of the n data latches 43a, and n data latches 43a. And n output switches SW2 connected to the respective output terminals. The data latch circuit 43 includes an output switch SW2 in the first column and a transfer switch SWtrs connected to the control unit 50.

The input switch SW1 is driven based on a control signal from the control unit 50, and the input end of the p-th column data latch 43a is connected to the p-th column register in the data register circuit 42 and the p-th column detection ADC 44b. , Connected to any one of the output ends of the data latches 43a in the (p + 1) th column.

When the input terminal of the data latch 43a and the data register circuit 42 are connected, the data latch 43a holds the display data Din stored in the data register circuit 42 at a timing synchronized with the latch pulse signal LP.

When the input terminal of the data latch 43a and the detection ADC 44b are connected, the data latch 43a holds the data output from the detection ADC 44b as detection data Dout at a timing synchronized with the latch pulse signal LP.

When the input end of the data latch 43a in the p-th column is connected to the output end of the data latch 43a in the p + 1-th column, the data latch 43a in the p-th column is synchronized with the latch pulse signal LP at the timing of the p + 1-th column. The detection data Dout held by the data latch 43a is held. Note that the data latch 43a in the nth column, which is the last column, is connected to the logic power supply 60, and the logic reference voltage LVSS is applied to the data latch 43a in the nth column.

The output switch SW2 is driven based on a control signal from the control unit 50, and the input terminal of the data latch 43a in the (p + 1) th column is connected to the display DAC 44a of the voltage conversion circuit 44 and the input terminal of the data latch 43a in the pth column. Connect to one of these.

When the input terminal of the data latch 43a and the display DAC 44a of the voltage conversion circuit 44 are connected, the display data Din held by the data latch 43a is input to the display DAC 44a at a timing synchronized with the latch pulse signal LP.

When the output terminal of the data latch 43a in the p + 1 column and the input terminal of the data latch 43a in the p column are connected, the detection data Dout held in the data latch 43a in the p + 1 column is synchronized with the latch pulse signal LP. Thus, it is held in the data latch 43a in the p-th column.

The transfer switch SWtrs is driven based on a control signal from the control unit 50, and switches between connection and disconnection between the data latch 43a in the first column and the control unit 50. When the data latch 43a in the first column is connected to the control unit 50, the detection data Dout held by the data latch 43a in the first column is output to the control unit 50.

The voltage conversion circuit 44 includes n display DACs 44a and n detection ADCs 44b which are analog-digital conversion circuits. Each of the n detection ADCs 44b converts an analog voltage input from the buffer circuit 45 connected to the detection ADC 44b into, for example, 8-bit detection data Dout, and a data latch connected to the detection ADC 44b. The detection data Dout is output to 43a. The detection ADC 44b has linearity in the output digital data with respect to the input analog voltage. The display DAC 44a and the detection ADC 44b are set to the same bit length, for example, 8 bits, as the bit length of the digital data at the time of voltage conversion.

The buffer circuit 45 includes a buffer 45a for each data line Ld, a buffer 45b for each data line Ld, and a display switch SWd for each data line Ld for switching connection and disconnection between the data line Ld and the buffer 45a. Yes. The buffer circuit 45 also includes a detection switch SWm for each data line Ld that switches connection and disconnection between the data line Ld and the buffer 45b, and a data line Ld that switches connection and disconnection between the data line Ld and the analog power supply 70. And a detection voltage switch SWs.

The display switch SWd is driven based on a control signal from the control unit 50, connects the buffer 45a and the data line Ld, and applies the light emission voltage VD and the non-light emission voltage VDN from the buffer 45a to the data line Ld. . The buffer 45b takes in the voltage of the data line Ld, amplifies the taken-in voltage to the drive level of the detection ADC 44b, and outputs the amplified voltage to the detection ADC 44b. The detection switch SWm is driven based on a control signal from the control unit 50, connects the buffer 45b and the data line Ld, and takes the voltage of the data line Ld into the buffer 45b. The detection voltage switch SWs controls application of the detection voltage VM from the analog power supply 70 to the data line Ld.

Each input terminal of the n data latches 43a is connected to a corresponding register in the data register circuit 42 in the light emission period and the non-light emission period. Each of the n data latches 43a holds the gradation data stored in the corresponding register, and synchronizes the holding with the latch pulse signal LP. Each of the n data latches 43 a outputs the display data Din held in the data latch 43 a to the voltage conversion circuit 44. As a result, the data latch circuit 43 holds the display data Din for one row fetched by the data register circuit 42 for each input of the latch pulse signal LP, and converts the held display data Din for one row into a voltage. Output to the circuit 44.

Each input terminal of the n data latches 43a is connected to the corresponding detection ADC 44b in the display DAC / ADC 44 in the detection operation. Each of the n data latches 43a holds the data output from the corresponding detection ADC 44b as detection data Dout, and synchronizes the holding with the latch pulse signal LP.

The input terminal of the data latch 43a in the p-th column (1 ≦ p ≦ n) is connected to the output terminal of the data latch 43a in the p + 1 column in the detection operation. Each of the data latches 43a in the p-th column holds the data held in the data latches 43a in the (p + 1) th column as detection data Dout, and synchronizes the holding with the latch pulse signal LP.

The output terminal of the data latch 43a in the first column is connected to the control unit 50 in the detection operation, and outputs the detection data Dout held in the data latch 43a in the first column to the control unit 50. As a result, the data latch 43a in the first column holds all data held in the data latch 43a in the p + 1 column in order from the data latch 43a in the second column, and outputs the held data to the control unit 50 in order. To do.

[Operation of EL display device]
With reference to FIGS. 18 to 25, the operation during the light emission period of the EL display device and the operation during the non-light emission period of the EL display device including the detection operation will be described. First, the operation during the light emission period of the EL display device will be described.

[Flash duration]
With reference to FIG. 18, the transition of the drive state of the selection driver 20, the power supply driver 30, and the data driver 40 in the light emission period will be described. In the light emission period, as in the first embodiment and the second embodiment, the light emission writing operation and the light emission operation are performed in this order.

As shown in FIG. 18, in the light emission period, the control unit 50 keeps the detection switch SWm, the detection voltage switch SWs, and the transfer switch SWtrs off. The control unit 50 keeps the output switch SW2 in a state where the data latch 43a and the display DAC 44a are connected, and keeps the input switch SW1 in a state where the data latch 43a and the data register circuit 42 are connected. And the control part 50 controls the input of start pulse signal SP1, the input of start pulse signal SP2, and the input of latch pulse signal LP similarly to the light emission period in 1st Embodiment.

That is, at the timing tk1, the control unit 50 switches on the display switch SWd to connect the shift register circuit 41, the data register circuit 42, the data latch 43a, the display DAC 44a, the buffer 45a, and the data line Ld in series. Connect to.

At timing tk2, the control unit 50 inputs the start pulse signal SP1 to the data driver 40, and causes the data register circuit 42 to capture the display data Din of the first row. Then, the control unit 50 inputs the start pulse signal SP2 to the selection driver 20 and the power supply driver 30.

At timing tk3, the control unit 50 applies the selection voltage VgH to the first scanning line Ls, and applies the writing voltage WDVSS to the first power supply line La. At this time, the control unit 50 inputs the latch pulse signal LP to the data driver 40 and causes the data latch 43a to simultaneously hold the display data Din for the first row. The display data Din in the first row held in the data latch 43a is input to the data line Ld as the light emission voltage VD which is an analog voltage. Thus, the control unit 50 finishes the light emission writing operation for the pixels Px in the first row. At this time, the control unit 50 inputs the start pulse signal SP1 to the data driver 40 again, and causes the data register circuit 42 to capture the display data Din on the second row.

The control unit 50 handles the difference between the detection data Dout associated with the pixel Px in the first row and the reference threshold voltage Vth as a correction value. Then, the control unit 50 calculates and corrects the correction value for the adjusted light emission gradation data, and sets the calculation result as the light emission voltage VD applied to each data line Ld.

At timing td4, the control unit 50 applies the non-selection voltage VgL to the first scanning line Ls and applies the driving voltage ELVDD to the first power supply line La. Each of the driving transistors Tr3 in the first row has a drain corresponding to the difference between the write voltage held in the holding capacitor Cs in the first row and the threshold voltage Vth in the driving transistor Tr3 to which the driving transistor Tr3 is connected. A current is supplied to the corresponding EL element 11. At this time, in the light emission voltage VD applied to each data line Ld, the fluctuation amount of the threshold voltage Vth is corrected. Therefore, the drain current supplied to the EL element 11 is also changed in the threshold voltage Vth. The minutes are corrected. Accordingly, the control unit 50 ends the light emission period for the pixels Px in the first row.

At this time, the control unit 50 applies the selection voltage VgH to the second scanning line Ls and applies the write voltage WDVSS to the second power supply line La. Further, the control unit 50 inputs the latch pulse signal LP to the data driver 40 again, and causes each data latch 43a to hold the display data Din on the second row. The display data Din in the second row held in the data latch 43a is input to the data line Ld as the light emission voltage VD which is an analog voltage. Thus, the control unit 50 finishes the light emission writing operation for the pixels Px in the second row. Thereafter, the write operation for light emission and the light emission operation are performed in this order for each row, and such a light emission period is repeated in order from the first row to the nth row in the display clock cycle.

[Non-light emission period]
The transition of the driving state of the selection driver 20, the power supply driver 30, and the data driver 40 during the non-light emission period of the EL display device will be described with reference to FIGS. In the non-emission period, non-emission writing operation, non-emission operation, and detection operation are performed in this order. FIG. 19 shows transition of the driving state of the selection driver 20, the power supply driver 30, and the data driver 40 in the non-light emission writing operation and the non-light emission operation, and FIG. 21 shows the selection driver in the detection operation. 20, the transition of the drive state of the power supply driver 30 and the data driver 40 is shown.

As shown in FIG. 19, in the period in which the non-light emission writing operation and the non-light emission operation are performed, the control unit 50 follows the light emission period, and includes a detection switch SWm, a detection voltage switch SWs, and The transfer switch SWtrs is kept off. The control unit 50 keeps the output switch SW2 in a state where the data latch 43a and the display DAC 44a are connected, and keeps the input switch SW1 in a state where the data latch 43a and the data register circuit 42 are connected. Further, the control unit 50 keeps the display switch SWd on, and continues to connect the shift register circuit 41, the data register circuit 42, the data latch 43a, the display DAC 44a, the buffer 45a, and the data line Ld in series. The control unit 50 receives the start pulse signal SP1, the start pulse signal SP2, and the latch pulse signal LP as in the non-light emission writing operation and the non-light emission operation in the first embodiment.

That is, at timing tj1, the control unit 50 inputs the start pulse signal SP1 to the data driver 40, and causes the data register circuit 42 to take in the display data Din of the first row. Then, the control unit 50 inputs the start pulse signal SP2 to the selection driver 20 and the power supply driver 30.

At timing tj2, the control unit 50 applies the selection voltage VgH to the scanning line Ls in the first row and applies the writing voltage WDVSS to the power supply line La in the first row. At this time, the control unit 50 inputs the latch pulse signal LP to the data driver 40 and causes the data latch 43a to simultaneously hold the display data Din for the first row. The display data Din in the first row held in the data latch 43a is input to the data line Ld as a non-light emission voltage VDN that is an analog voltage. As a result, the control unit 50 holds, for each pixel Px in the first row, a lower gate-source voltage Vgs as the pixel Px with the immediately higher light emission voltage VD causes non-light emission to the pixel Px in the first row. Finish the writing operation. At this time, the control unit 50 inputs the start pulse signal SP1 to the data driver 40 again, and causes the data register circuit 42 to capture the display data Din on the second row.

The control unit 50 handles the difference between the detection data Dout associated with the pixel Px in the first row and the reference threshold voltage Vth as a correction value. Then, the control unit 50 applies the non-light emission voltage VDN to which the correction value is added to each data line Ld.

At timing tj3, the control unit 50 continues to apply the non-selection voltage VgL to the scanning line Ls of the first row and the writing voltage WDVSS to the power supply line La of the first row. As a result, the control unit 50 applies a lower gate-source to each driving transistor Tr3 in the first row, as the writing voltage held in the holding capacitor Cs in the first row, that is, the pixel Px having the immediately higher light emission voltage VD. The voltage Vgs is continuously applied. Thus, the control unit 50 finishes the non-light emission operation for the pixels Px in the first row.

At this time, the control unit 50 applies the selection voltage VgH to the second scanning line Ls and applies the write voltage WDVSS to the second power supply line La. Further, the control unit 50 inputs the latch pulse signal LP to the data driver 40 again, and causes each data latch 43a to hold the display data Din on the second row. The display data Din in the second row held in the data latch 43a is input to the data line Ld as the non-light emission voltage VDN that is an analog voltage. Thereby, the control unit 50 finishes the non-light emission writing operation for the pixels Px in the second row. Thereafter, the non-emission writing operation and the non-emission operation are performed in this order for each row, and the non-emission writing operation and the non-emission operation are sequentially displayed from the first line to the nth line. Repeated with clock period.

Next, the transition of the driving state of the selection driver 20, the power supply driver 30, and the data driver 40 in the detection operation will be described. First, the dependence of the light emission voltage VD on the drain current of the drive transistor Tr3 will be described with reference to FIG. FIG. 20 illustrates the above dependency on two drive transistors Tr3 having different threshold voltages Vth of the drive transistor Tr3.

A curve L1 indicated by a solid line in FIG. 20 shows the dependence of the light emission voltage VD on the drain current Id of the drive transistor Tr3, and the threshold voltage Vth of the drive transistor Tr3 and the current amplification factor β in the drive circuit PCC are Indicates the dependency when it is the initial value. Assuming that the initial value of the threshold voltage Vth is Vth ₀ , the drain current Id flowing through the drive circuit PCC in the initial state is expressed by the following formula (1). V ₀ is the write voltage WDVSS.

Id = β (V ₀ −Vd−Vth ₀ ) ² (1)
A curve L2 indicated by a broken line in FIG. 20 shows the dependency of the light emission voltage VD on the drain current Id of the driving transistor Tr3, and shows the time when the drain current Id of the driving transistor Tr3 changes from the initial state over time. When the threshold voltage Vth is Vth ₁ (= Vth ₀ + ΔVth), the drain current Id flowing through the drive circuit PCC in this state is expressed by the following formula (2).

Id = β (V ₀ −Vd−Vth ₁ ) ² (2)
As shown in FIG. 20 and the above equations (1) and (2), the curve L2 shows a shape in which the curve L1 is translated by the shift amount ΔVth, and before and after the fluctuation of the threshold voltage Vth, The shapes of the curve L1 and the curve L2 are not substantially changed. This is because the fluctuation of the current amplification factor β is negligible compared to the fluctuation of the threshold voltage Vth, and the light emission voltage VD is corrected using the shift amount ΔVth in the driving transistor Tr3. This suggests that the drain current Id of the driving transistor Tr3 is corrected. In the detection operation of the threshold voltage Vth, the EL display device of the second embodiment detects the threshold voltage Vth of the drive transistor Tr3 and corrects the light emission voltage VD applied to the drive circuit PCC.

Referring to FIG. 21, the transition of the driving state of the selection driver 20, the power supply driver 30, and the data driver 40 in the detection operation will be described. In the detection operation, a voltage holding operation, a voltage saturation operation, a voltage measurement operation, and a voltage output operation are performed in this order. Note that the detection operation of the threshold voltage Vth is equal to each other for each row where the pixels Px are arranged. Therefore, hereinafter, a case where the row to be detected is the q-th row will be described as an example.

As shown in the lower side of FIG. 21, the control unit 50 continues to apply the write voltage WDVSS to the q-th power supply line La during the period in which the detection operation of the pixel Px in the q-th row is performed. Further, the control unit 50 keeps the display switch SWd off, and keeps disconnecting the driving circuit PCC in the q-th row from the shift register circuit 41 and the data register circuit 42. Further, the control unit 50 continues to connect the output switch SW2 to another adjacent data latch 43a.

At timing t1, the control unit 50 connects the input switch SW1 to the detection ADC 44b and keeps the transfer switch SWtrs off. In this state, the control unit 50 applies the selection voltage VgH to the scanning line Ls in the q-th row so that the switching transistor Tr2 in the q-th row and the sampling transistor Tr1 in the q-th row are in a conductive state. The eye driving transistor Tr3 is changed to a state of driving in the saturation region. Further, the control unit 50 switches on the detection voltage switch SWs to apply the detection voltage VM to the data lines Ld from the analog power supply 70 at the same time.

At this time, the detection voltage VM is set in advance so that a voltage higher than the assumed threshold voltage Vth is applied as the gate-source voltage Vgs. That is, the control unit 50 causes the detection voltage VM between the gate and the source of the drive transistor Tr3 so that the difference between the write voltage WDVSS and the detection voltage VM is larger than the assumed threshold voltage Vth. Apply. Note that the potential of each data line Ld to which the detection voltage VM is applied is lower than the write voltage WDVSS and lower than the cathode of the EL element 11.

When the detection voltage VM is applied to each data line Ld, the current for each pixel Px corresponding to the difference between the detection voltage VM and the write voltage WDVSS is supplied to the q-th drive transistor Tr3 and the q-th row. It flows to the analog power supply 70 through the sampling transistor Tr1. Accordingly, the gate-source voltage Vgs of the driving transistor Tr3 is held in the holding capacitor Cs in the q-th row, and thus the voltage holding operation is finished. Note that the EL element 11 does not emit light because the potential of the anode of the EL element 11 is lower than the potential of the cathode of the EL element 11.

At timing t2, the control unit 50 switches off only the detection voltage switch SWs while maintaining the application of the selection voltage VgH to the scanning line Ls in the q-th row and keeping the detection switch SWm off. As a result, a portion of each data line Ld that is closer to the data driver 40 than a portion that is connected to the sampling transistor Tr1 is switched to a high impedance state.

At this time, since the holding capacitor Cs in the q-th row holds the gate-source voltage Vgs of the driving transistor Tr3 in the q-th row, the potential of the source of the driving transistor Tr3 in the q-th row becomes the q-th row. The drain current flows in the driving transistor Tr3 in the q-th row so as to approach the drain potential of the driving transistor Tr3. As the relaxation time t, which is the time elapsed from the timing t2, advances, the q-th storage capacitor Cs discharges, and the voltage between both ends of the q-th storage capacitor Cs is, that is, the q-th storage capacitor Cs. The gate-source voltage Vgs in the drive transistor Tr3 decreases to the threshold voltage Vth at which the drain current does not flow.

As a result, the holding capacitor Cs in the q-th row holds a voltage corresponding to the threshold voltage Vth of the driving transistor Tr3 in the q-th row, and the voltage saturation operation ends. The control unit 50 keeps the detection switch SWm for applying the detection voltage VM to each data line Ld off after the timing t2.

At timing t3, the control unit 50 keeps applying the selection voltage VgH to the q-th scanning line Ls, and turns on only the detection switch SWm. As a result, the data line Ld and the detection ADC 44b are connected, and the potential of the data line Ld in the high impedance state is taken into the detection ADC 44b.

At this time, the holding capacitor Cs in the q-th row holds a voltage corresponding to the threshold voltage Vth of the driving transistor Tr3 in the q-th row. Therefore, from the potential difference between the potential taken in the detection ADC 44b and the write voltage WDVSS, the gate-source voltage Vgs in the q-th drive transistor Tr3, that is, the threshold voltage of the q-th drive transistor Tr3. A voltage corresponding to Vth is detected. The potential of the data line Ld taken into the detection ADC 44b is converted into detection data Dout which is digital data by the detection ADC 44b, and is output to the data latch 43a through the level shifter 46b. The data latch 43a holds the detection data Dout, thereby ending the voltage measurement operation.

At timing t4, the control unit 50 applies the non-selection voltage VgL to the scanning line Ls in the qth row, and switches the switching transistor Tr2 in the qth row and the sampling transistor Tr1 in the qth row to a non-conductive state. In this state, the control unit 50 switches the detection switch SWm off and switches the transfer switch SWtrs on. Further, the control unit 50 connects the input switch SW1 to the adjacent data latch 43a and connects the data latches 43a in series.

At this time, the control unit 50 inputs the latch pulse signal LP to the data driver 40, and sequentially transfers the detection data Dout held in each data latch 43a in synchronization with the timing of the latch pulse signal LP. As a result, the control unit 50 causes the data driver 40 to sequentially transfer data regarding the threshold voltage Vth of each of the driving transistors Tr3 in the q-th row. In FIG. 21, the number of times the latch pulse signal LP is repeated is omitted for convenience of explaining the transition of the driving state.

At timing t5, the control unit 50 keeps applying the non-selection voltage VgL to the q-th scanning line Ls and switches off the transfer switch SWtrs. The control unit 50 connects the input end of the data latch 43 a to the register of the data register circuit 42. As a result, the voltage output operation ends, and the detection operation for the driving transistor Tr3 in the q-th row ends.

With reference to FIG. 22, the transition of the data line potential VLd which is the potential of the data line Ld in the period from the timing t2 to the timing t3 will be described.
As shown in FIG. 22, when the relaxation time t, which is the time elapsed from the timing t2, progresses, the data line potential VLd becomes the detection voltage VM according to the discharge of the charge in the storage capacitor Cs connected to the data line Ld. Approaches the write voltage WDVSS. When the relaxation time t advances to the saturation time ts, the data line potential VLd is saturated at the saturation voltage VLds and the drain current does not flow. At this time, the difference between the write voltage WDVSS and the saturation voltage VLds is set as the threshold voltage Vth. The saturation time ts is, for example, 3 nsec to 10 nsec, and the period from timing t2 to timing t3 is set to be equal to or longer than the saturation time ts.

[Detection operation timing]
The timing of the detection operation included in the non-light emission period will be described with reference to FIGS. In the following, for the sake of convenience in explaining the timing of the detection operation using the number of rows and the number of frames in the arrangement of the pixels Px, a configuration in which the pixels Px are located in 540 rows × 960 columns and the frame rate is 60 fps. This will be described as an example. FIG. 23 shows the timing of the detection operation in the non-light emission period of the first frame, FIG. 24 shows the timing of the detection operation in the non-light emission period of the second frame, and FIG. 25 shows the timing in the non-light emission period of the 540 frame. The timing of detection operation is shown. Note that the number of rows in the arrangement of the pixels Px may be other than 540. When the number of rows in the arrangement of the pixels Px is m rows, the timing of the detection operation of the m-th frame corresponds to the content shown in FIG.

As shown in FIG. 23, at timing Tf1a, the light emission writing operation starts in the pixel Px in the first row. When the write operation for light emission ends at the pixel Px in the first row, the light emission operation starts at the pixel Px in the first row, and the write operation for light emission starts at the pixel Px in the second row. Thus, the light-emission writing operation is sequentially repeated from the pixel Px in the first row to the pixel Px in the 540-th row at the display clock cycle, and the light-emission operation starts in order from the row where the light-emission writing operation is completed. .

At timing Tf1b, the write operation for light emission proceeds in the pixel Px on the 540th row, and the write operation for non-light emission starts on the pixel Px on the first row. When the non-emission writing operation ends at the pixel Px in the first row, the non-emission operation starts at the pixel Px in the first row, and the non-emission writing operation starts at the pixel Px in the second row. . Thus, the non-light-emission writing operation is sequentially repeated from the pixel Px in the first row to the pixel Px in the 540-th row in the display clock cycle, and the non-light emission is sequentially performed from the row where the non-emission writing operation is completed. The operation starts.

At timing Tf1c, the non-light emission operation proceeds in the pixel Px on the 540th row, and then the candidate for selection is sequentially scanned in the detection clock cycle from the pixel Px on the first row to the pixel Px on the 540th row. . At this time, first, the pixel Px in the first row is set as a detection target from which the threshold voltage Vth is detected, and the detection operation for the pixel Px in the first row proceeds. The detection data Dout for the driving transistor Tr3 in the first row is stored in the storage unit 53.

When the detection operation is completed at the pixel Px in the first row, the selection target candidates are sequentially scanned from the pixel Px in the second row to the pixel Px in the 540 row in the detection clock cycle. During this scanning, the non-selection voltage VgL is applied to all the scanning lines Ls, and all the pixels Px maintain a state in which the EL elements 11 are not caused to emit light.

When the candidate for selection is scanned up to the pixel Px in the 540th row at the timing Tf2a, the light emission writing operation for the pixel Px in the first row starts again.
As shown in FIG. 24, at the timing Tf2a, the writing operation for light emission starts in the pixels Px in the first row. When the write operation for light emission ends at the pixel Px in the first row, the light emission operation starts at the pixel Px in the first row, and the write operation for light emission starts at the pixel Px in the second row. Thus, the light-emission writing operation is sequentially repeated from the pixel Px in the first row to the pixel Px in the 540-th row at the display clock cycle, and the light-emission operation starts in order from the row where the light-emission writing operation is completed. .

At timing Tf2b, the write operation for light emission proceeds in the pixel Px in the 540th row, and the write operation for non-light emission starts in the pixel Px in the first row. When the non-emission writing operation ends at the pixel Px in the first row, the non-emission operation starts at the pixel Px in the first row, and the non-emission writing operation starts at the pixel Px in the second row. . Thus, the non-light-emission writing operation is sequentially repeated from the pixel Px in the first row to the pixel Px in the 540-th row in the display clock cycle, and the non-light emission is sequentially performed from the row where the non-emission writing operation is completed. The operation starts.

At timing Tf2c, the non-light emission operation proceeds at the pixel Px in the 540th row, and then the candidate for selection is sequentially scanned in the detection clock cycle from the pixel Px in the first row to the pixel Px in the 540th row. . At this time, first, the pixel Px in the second row is set as the detection target from which the threshold voltage Vth is detected, and the shift of the selection target bit in the detection clock cycle proceeds to the pixel Px in the second row. Here, when the selection target candidate is the pixel Px in the first row, the non-selection voltage VgL is applied to the scanning line Ls. When the candidate for selection is the pixel Px in the second row, the detection operation proceeds for the pixel Px in the second row.

Thereby, the detection data Dout related to the driving transistor Tr3 in the second row is stored in the storage unit 53 of the control unit 50. When the detection operation for the pixel Px in the second row is completed, the selection candidate is sequentially scanned from the pixel Px in the third row to the pixel Px in the 540 row in the detection clock cycle. During this scanning, the non-selection voltage VgL is applied to all the scanning lines Ls, and all the pixels Px maintain a state in which the EL elements 11 are not caused to emit light.

When the candidate for selection is scanned up to the pixel Px in the 540th row at the timing Tf3a, the light emission writing operation for the pixel Px in the first row starts again.
As shown in FIG. 25, at the timing Tfma, the light emission writing operation starts in the pixels Px in the first row. When the write operation for light emission ends at the pixel Px in the first row, the light emission operation starts at the pixel Px in the first row, and the write operation for light emission starts at the pixel Px in the second row. Thus, the light-emission writing operation is sequentially repeated from the pixel Px in the first row to the pixel Px in the 540-th row at the display clock cycle, and the light-emission operation starts in order from the row where the light-emission writing operation is completed. .

At timing Tfmb, the light emission write operation proceeds in the pixel Px in the 540th row, and the non-light emission write operation starts in the pixel Px in the first row. When the non-emission writing operation ends at the pixel Px in the first row, the non-emission operation starts at the pixel Px in the first row, and the non-emission writing operation starts at the pixel Px in the second row. . Thus, the non-light-emission writing operation is sequentially repeated from the pixel Px in the first row to the pixel Px in the 540-th row in the display clock cycle, and the non-light emission is sequentially performed from the row where the non-emission writing operation is completed. The operation starts.

At timing Tfmc, the non-light emission operation proceeds in the pixel Px on the 540th row, and then the candidate to be selected is sequentially scanned from the pixel Px on the first row to the pixel Px on the 540th row in the detection clock cycle. . At this time, first, the pixel Px in the 540th row is set as the detection target for which the threshold voltage Vth is detected, and the shift of the selection target bit in the detection clock cycle proceeds to the pixel Px in the 539th row. Here, when the candidate to be selected is the pixel Px in the first row from the pixel Px in the first row, the non-selection voltage VgL is applied to the scanning line Ls. When the candidate for selection is the pixel Px in the 540th row, the detection operation proceeds for the pixel Px in the 540th row. As a result, the detection data Dout regarding the drive transistor Tr3 in the 540th row is stored in the storage unit 53 of the control unit 50. At the timing Tfmd, the detection operation for the pixel Px in the 540th row is finished, and the write operation for light emission is started again for the pixel Px in the first row.

As described above, every time one frame is displayed, the non-light emission operation proceeds to the pixel Px in the 540th row, and thereafter, the detection operation for the pixel Px in a specific row is performed. The detection target of the threshold voltage Vth is shifted from the pixel Px in the first row one by one along the scanning direction for each frame. That is, when the detection operation for the pixel Px in the q-th row (1 ≦ q ≦ 539) is performed in the k-th frame (k is an integer equal to or greater than 1), the detection operation for the pixel Px in the q + 1-th row is performed in the k + 1-th frame. Is done. When the detection target advances to the pixel Px in the last row, the detection target returns to the pixel Px in the first row again.

At this time, the detection data Dout obtained when the detection target is the q-th row is stored and updated in the storage area in the control unit 50 in which the pixel Px in the q-th row is associated. Is done. The control unit 50 uses the latest detection data Dout as the detection data Dout in the q-th row when generating the display data Din in the (k + 1) th frame. Note that the control unit 50 uses again the detection data Dout used in the k-th frame as the detection data Dout other than the q-th row. Thus, the detection data Dout of each row is updated every time the frame display is repeated 540 times.

Referring to FIG. 26, the transition of the control signal during the period in which one frame is displayed will be described in detail. Since the transition of the control signal during the period in which one frame is displayed is the same for each detection target, hereinafter, the transition of the control signal when the detection target in the k-th frame is the pixel Px in the q-th row. Will be described as an example.

The selection driver 20 generates a shift signal at a display clock period in accordance with the input of the start pulse signal SP2, and applies the selection voltage VgH to each scanning line Ls in order at a timing based on the shift signal. At this time, the selection driver 20 applies the selection voltage VgH in the display clock cycle in order from the first scanning line Ls to the 540th scanning line Ls.

The power supply driver 30 generates a shift signal at a display clock cycle in accordance with the input of the start pulse signal SP2, and sequentially selects candidates for supply at a timing based on the shift signal. At this time, the power supply driver 30 applies the write voltage WDVSS in order from the power supply line La of the first row to the power supply line La of the 540th row in the display clock cycle.

When the selection voltage VgH is applied to the scanning line Ls of the q-th row (q is an integer from 1 to 540) and the write voltage WDVSS is applied to the power line La of the q-th row, the display data Din Is applied to the data line Ld. Further, in order from the row to which the selection voltage VgH is applied, the non-selection voltage VgL is applied to the scanning line Ls, and the driving voltage ELVDD is applied to the power supply line La in order from the row to which the write voltage WDVSS is applied. . When the non-selection voltage VgL is applied to the q-th scanning line Ls and the driving voltage ELVDD is applied to the q-th power line La, a drain current based on the display data Din is applied to the EL element 11. Supplied.

When the light emission operation proceeds to the pixel Px in the 540th row, the selection driver 20 starts scanning for applying the selection voltage VgH again in response to the input of the start pulse signal SP2. When the application of the drive voltage ELVDD proceeds to the pixel Px in the 540th row, the power supply driver 30 starts scanning for the application of the write voltage WDVSS again in response to the input of the start pulse signal SP2.

When the selection voltage VgH is applied to the q-th scanning line Ls and the write voltage WDVSS is applied to the q-th power line La, the non-light-emitting voltage VDN based on the display data Din is the data Applied to line Ld. As a result, the gate-source voltage Vgs in the reverse direction of the drive transistor Tr3 is applied to the drive transistor Tr3.

When the non-light emission operation proceeds to the pixel Px in the 540th row, the input of the start pulse signal SP2 reaches the set number of times, and the shift clock signal used for scanning the scanning line Ls changes from the display clock cycle to the detection clock cycle. Switch. The selection driver 20 shifts the selection target candidates in the detection clock cycle, and the power supply driver 30 shifts the supply target candidates in the detection clock cycle. Since the mask pulse signal MP is at a low level during this period, the selection driver 20 does not apply the selection voltage VgH to the selection target candidate. During this period, the power supply driver 30 continues to apply the write voltage WDVSS to the candidate to be supplied.

When the candidate to be selected is shifted to the q-th row, the mask pulse signal MP is switched to the high level, and the selection driver 20 applies the selection voltage VgH to the scanning line Ls of the q-th row. Then, the control unit 50 detects the threshold voltage Vth of the pixel Px in the q-th row.

When the control unit 50 acquires the detection data Dout for the pixel Px in the q-th row, the mask pulse signal MP is switched to the low level again. The selection driver 20 shifts the selection target candidate to the 540th row in the detection clock cycle, and the power supply driver 30 also shifts the supply target candidate to the 540th row in the detection clock cycle. Since the mask pulse signal MP is at a low level during this period, the selection driver 20 does not apply the selection voltage VgH to the selection target candidate. During this period, the power supply driver 30 continues to apply the write voltage WDVSS to the candidate to be supplied.

When the candidate for selection is shifted to the 540th line, the mask pulse signal MP is switched to the high level again. Then, the light emission writing operation and the light emission operation are started again in order from the first scanning line Ls to the 540th scanning line Ls.

According to the third embodiment, the advantages listed below can be obtained.
(1) The threshold voltage Vth of the drive transistor Tr3 is detected, and the display data Din is corrected by the threshold voltage Vth. Therefore, image quality deterioration due to fluctuations in the threshold voltage Vth can be suppressed.

(2) Since the detection operation is performed during a period in which one frame is displayed, deterioration of the displayed image quality can be suppressed even when the variation of the threshold voltage Vth increases in a short period.
(3) The detection target of the threshold voltage Vth is n pixels Px connected to one scanning line Ls in one detection operation. Therefore, the detection time of the threshold voltage Vth in one detection operation is shorter than the time required for one detection operation as compared with the configuration of all the pixels Px. As a result, when the detection operation is incorporated in one non-emission period, it is possible to suppress a reduction in image quality due to the longer non-emission period.

(4) In particular, since the detection operation is performed during a non-light emitting period inserted in order to display a moving image clearly, the influence of the detection operation on the image display performance can be effectively suppressed.
(5) The selection of candidates to be selected is advanced in the detection operation in the same manner as the write operation for light emission, the light emission operation, the write operation for non-light emission, and the non-light emission operation. Therefore, the selection driver 20 also functions as a configuration that changes the detection target every time one frame is displayed.

(6) In the detection operation, the detection target candidate switching period is a detection clock period shorter than the display clock period. Therefore, for example, the time required for the detection operation is shorter than that in the configuration in which the detection target candidate switching cycle is the display clock cycle.

(7) Every time one frame is displayed, the detection target of the threshold voltage Vth is shifted by one row from the pixel Px in the first row along the scanning direction. Therefore, the correction of the display data Din based on the threshold voltage Vth is finer in the scanning direction than in the configuration in which the detection target of the threshold voltage Vth is intermittently set along the scanning direction.

[Modification]
The above embodiment can be implemented with the following modifications.
[Non-light emission voltage VDN]
The relationship between the light emission voltage VD and the non-light emission voltage VDN associated with each other by the control unit 50 can be changed as follows.

As shown by the broken line LC1 in FIG. 27, the level of the non-light emission voltage VDN may be two different levels. When the light emission voltage VD is equal to or higher than the switching value Vp, the light emission voltage VD is associated with the low-level non-light emission voltage VDN among two different levels. Further, when the light emission voltage VD is less than the switching value Vp, a high level non-light emission voltage VDN of two different levels is associated with the light emission voltage VD. That is, the light emission voltage VD corresponding to the gradation value lower than the gradation value corresponding to the switching value Vp is associated with the non-light emission voltage VDN having a large potential difference from the write voltage WDVSS among two different levels. It is done. In addition, the light emission voltage VD corresponding to a gradation value equal to or higher than the gradation value corresponding to the switching value Vp is associated with a non-light emission voltage VDN that is close to the write voltage WDVSS among two different levels. Even if the light emission voltage VD and the non-light emission voltage VDN are associated with each other, the higher the light emission voltage VD is, the lower the non-light emission voltage VDN is in the vicinity of the switching value Vp.

At this time, as indicated by a broken line LC2 in FIG. 27, the high level non-light-emitting voltage VDN of the two different levels is the same level as the second non-light-emitting voltage VDN2 of the second embodiment. Good. That is, when the level of the non-light emitting voltage VDN is two different levels, at least one level is a level in the reverse direction between the gate and the source of the driving transistor Tr3 in the non-light emitting writing operation. There may be. Note that all of the levels of the non-light emitting voltage VDN may be levels in the reverse direction between the gate and the source of the driving transistor Tr3 in the non-light emitting writing operation.

Note that, as indicated by a one-dot chain line LC3 in FIG. 27, the non-light-emitting voltage VDN may have three different levels, or four or more different levels. In short, as a correspondence between the light emission voltage VD and the non-light emission voltage VDN, a configuration including a state in which the non-light emission voltage VDN is lower as the light emission voltage VD is higher may be used.

As shown by a curve LC4 in FIG. 28, the non-light emission voltage VDN may continuously change over the entire range of the light emission voltage VD. That is, in all the ranges of the light emission voltage VD, the non-light emission voltage VDN may be associated with a lower value as the light emission voltage VD is higher.

At this time, as indicated by a one-dot chain line LC5 in FIG. 28, the non-light emission voltage VDN having the same level as the second non-light emission voltage VDN2 of the second embodiment with respect to the light emission voltage VD corresponding to the highest gradation value. May be associated.

Note that, as indicated by a broken line LC6 in FIG. 28, the change in the non-light emission voltage VDN with respect to the change in the light emission voltage VD may be different for each light emission voltage VD. In addition, association in which the non-light emission voltage VDN does not change with respect to the change in the light emission voltage VD may be included. Further, as shown by the solid line LC7, the non-light-emitting voltage VDN (for example, −5V) when the light-emitting voltage VD is low becomes higher than the minimum value (for example −10V) of the light-emitting voltage VD. The non-light emission voltage VDN may be associated. In short, as a correspondence between the light emission voltage VD and the non-light emission voltage VDN, a configuration including a state in which the non-light emission voltage VDN is lower as the light emission voltage VD is higher may be used.

The light emission voltage VD and the non-light emission voltage VDN associated with the light emission voltage VD may be applied to the data line Ld in different frames. In short, it is most important that the non-light emission voltage VDN has a lower state as the light emission voltage VD is higher. The time when the light emission voltage VD is high may be a frame that is a predetermined number of times before the frame in which the non-light emission voltage VDN is applied to the data line Ld, or may be a frame that is a predetermined number of times. .

For example, the control unit 50 stores the average value of the gradation data for light emission in a plurality of light emission periods, and updates the average value of the light emission gradation data for each of the plurality of light emission periods. Then, the control unit 50 uses the latest value of the average value of the light emission gradation data in a plurality of light emission periods, and generates the same non-light emission gradation data in a plurality of non-light emission periods immediately thereafter. That is, the non-light-emitting voltage VDN may be updated every multiple non-light-emission periods, using the same value in multiple non-light-emission periods. Even in such a configuration, the higher the light emission voltage VD, the lower the non-light emission voltage VDN is included.

[Drive circuit PCC]
As shown in FIG. 29, the three transistors Tr1 to Tr3 included in the drive circuit PCC are not limited to n-type transistors but may be p-type transistors. At this time, the anode of the EL element 11 is electrically connected to the power supply line La which is an example of the reference voltage line, the source Ns of the driving transistor Tr3 is electrically connected to the cathode of the EL element 11, and the drain of the driving transistor Tr3. Nd is electrically connected to the ground voltage line Lb. Even in such a configuration, (1) to (5) of the first embodiment, (1) and (2) of the second embodiment, and (1) to (7) of the third embodiment. Similar advantages are obtained.

The driving transistor Tr3 has a gate, a source, and a drain, and one of the source and the drain may be a connection end, and the other of the source and the drain may be a power feeding end. The drive circuit PCC includes a reference voltage line having a reference voltage, a drive transistor Tr3, an EL element 11 that is electrically connected to the ground voltage line Lb and the connection end, and a storage capacitor that connects the gate and the source. It is most important to prepare. In such a drive circuit PCC, at least one of the sampling transistor Tr1 and the switching transistor Tr2 may be omitted.

For example, in the EL display device, the sampling transistor Tr1 and the switching transistor Tr2 are omitted, the scanning line Ls is electrically connected to the gate of the driving transistor Tr3, and the data line Ld is electrically connected to the source of the driving transistor Tr3. May be. In short, the drive circuit PCC, and hence the EL display device, holds a voltage corresponding to the light emission voltage VD in the storage capacitor Cs during the light emission period, and passes a current corresponding to the light emission voltage VD to the EL element 11 through the drive transistor Tr3. . In the non-light emitting period, the EL display device holds the voltage corresponding to the non-light emitting voltage in the holding capacitor Cs, and sets the voltage at the power feeding end so that the current passing through the driving transistor Tr3 does not flow to the EL element 11. As long as the light emission voltage VD is higher, the non-light emission voltage VDN may be lower.

[Detection operation]
The m scanning lines may be partitioned into a plurality of scanning line groups each including 10 scanning lines adjacent to each other, and the detection target of the threshold voltage Vth for each frame may be set for each scanning line group. .

As shown in FIG. 30, in the first frame detection operation, the pixel Px in the first row is set as the detection target from the first scanning line group. In the detection operation of the second frame, the pixel Px in the eleventh row is set as a detection target from the second scanning line group. As described above, every time one frame is displayed, the detection target is shifted every ten rows from the pixel Px in the first row to the pixel Px in the 531 row.

As shown in FIG. 31, in the 55th frame, the pixel Px in the second row is set as a detection target from the first scanning line group. In the 56th frame, the pixel Px in the 12th row is set as the detection target from the second scanning line group. As described above, every time one frame is displayed, the detection target is shifted every ten rows from the pixel Px in the second row to the pixel Px in the 532 row.

As shown in FIG. 32, in the 487th frame, the pixel Px in the 10th row is set as the detection target from the first scanning line group. In the 488th frame, the pixel Px on the 20th row is set as the detection target from the second scanning line group. Thus, every time one frame is displayed, the detection target is shifted every ten rows from the pixel Px on the tenth row to the pixel Px on the 540th row. Thereby, the detection data Dout of each row is updated once every time the frame is displayed m times.

In addition, when the m scanning lines are divided into a plurality of scanning line groups including 10 scanning lines adjacent to each other, the correction of the display data Din based on the detection data Dout is performed in the following manner. May be.

That is, the storage unit 53 in the control unit 50 includes a storage area of m / 10 rows × n columns, and associates each of the ten pixels Px arranged in the column direction with one storage area. For example, the storage unit 53 associates the pixel Px in the first column in the first scanning line group with the storage area in the first row and first column, and sets the pixel Px in the second column in the second scanning line group, The storage area is associated with the second row and the second column. Further, the storage unit 53 associates the 959th column pixel Px in the 54th scanning line group with the storage region in the 54th row 959 column, and the 960th column pixel Px in the 54th scanning line group. It is associated with the storage area in the 54th row and the 960th column.

The image signal processing unit 54 of the control unit 50 reads the gradation data for each pixel Px and the detection data Dout associated with the pixel Px from the storage unit 53 when generating the display data Din. Then, the image signal processing unit 54 performs addition / subtraction operation on the gradation data for each pixel Px based on the detection data Dout associated with the pixel Px to generate display data Din for each pixel Px.

The detection data Dout obtained in the period in which the current frame is displayed may be handled as the detection data Dout for all rows in the period in which the next frame is displayed.

· The detection target may be set in the same row for each frame. Further, the detection target may be set irregularly for each frame. When the detection target is irregularly set for each frame, for example, the control unit 50 uses a random function that generates a random number for each frame between 1 and m. The timing at which the shift standby portion is output by the detection shift clock signal Clkr and the timing at which the mask release portion is output by the mask pulse signal MP are synchronized, and only the time corresponding to the generated random number. It is sufficient if these are delayed from the start pulse signal SP2.

· Two or more detection targets may be set for each frame. At this time, the detection shift clock signal Clkr outputs two shift standby portions at different timings, and the mask pulse signal MP outputs two mask release portions at different timings. The timing at which each of the two shift standby portions is output is synchronized with the timing at which each of the two mask release portions is output.

-For example, when the EL display device is activated or when the EL display device is paused and then returned, the drive circuits for all rows or some rows other than the period in which one frame is displayed A detection operation may be performed on the PCC.

The detection voltage VM applied in one detection operation may have a different configuration for each data line Ld. At this time, in the detection operation, each of the plurality of data lines Ld may be connected to the analog power supply 70 through different wirings. Alternatively, the detection voltage VM may be supplied from the data driver 40 to the data line Ld as digital data.

The data line Ld to which the detection voltage VM is applied in one detection operation may be a part of all the data lines Ld. At this time, in one detection operation, only some data lines Ld to which the detection voltage VM is applied are connected to the analog power supply 70 via the detection voltage switch SWs.

In the above embodiment, the threshold voltage Vth is detected as a characteristic of the drive transistor Tr3, and the light emission voltage VD is corrected based on the detected threshold voltage Vth. However, the current amplification factor β may be detected as a characteristic of the drive transistor Tr3, and the light emission voltage VD may be corrected based on the detected current amplification factor β. Further, both the threshold voltage Vth and the current amplification factor β may be detected as the characteristics of the drive transistor Tr3. In short, the detection target in the detection operation may be a parameter that affects the drive current supplied to the EL element 11 among the element characteristics of the drive transistor Tr3.

In the correction of the light emission voltage VD, the light emission characteristics of the EL element 11 such as light emission luminance may be used in addition to the element characteristics of the drive transistor Tr3.
-An organic EL element may be sufficient as a light emitting element, and an inorganic EL element may be sufficient as it.

β ... current amplification factor, t ... relaxation time, Ce ... pixel capacitance, Cp ... parasitic capacitance, Cs ... holding capacitance, Id ... drain current, L1, L2 ... curve, La ... power supply line, Lb ... ground voltage line, Ld ... Data line, LP ... Latch pulse signal, Ls ... Scan line, MP ... Mask pulse signal, Px ... Pixel, ts ... Saturation time, VD ... Light emission voltage, VDN ... Non-light emission voltage, VDN1 ... First non-light emission voltage, VDN2 ... Second non-emission voltage, VM ... detection voltage, Din ... display data, 11 ... organic EL element, PCC ... drive circuit, SP1, SP2 ... start pulse signal, SW1 ... input switch, SW2 ... output switch, SWd ... for display Switch, SWm: Detection switch, SWs: Detection voltage switch, Tr1: Sampling transistor, Tr2: Switching transistor, Tr3: Drive transistor , VEE ... analog reference voltage, VgH ... selection voltage, VgL ... non-selection voltage, Vgs ... gate-source voltage, VLd ... data line potential, Vth ... threshold voltage, ΔVth ... shift amount, Clkd ... data shift clock signal , Clks ... display shift clock signal, Clkr ... detection shift clock signal, Dout ... detection data, DVSS ... analog power supply voltage, LVDD ... logic power supply voltage, LVSS ... logic reference voltage, VLds ... saturation voltage, ELVDD ... drive voltage, ELVSS ... reference voltage, SWtrs ... transfer switch, WDVSS ... write voltage, 10 ... display panel, 20 ... select driver, 21 ... shift register circuit, 22 ... level shifter circuit, 23 ... buffer circuit, 30 ... power supply driver, 40 ... data Driver 41... Shift register circuit 42 Data register circuit, 43 ... Data latch circuit, 43a ... Data latch, 44 ... Voltage conversion circuit, 45 ... Buffer circuit, 46 ... Level shifter, 50 ... Control unit, 51 ... Image signal input unit, 52 ... Timing controller, 53 ... Memory 54, an image signal processing unit, 55, a display data output unit, 60, a logic power supply, and 70, an analog power supply.

Claims

A plurality of pixel circuits,
The pixel circuit includes:
A drive transistor having a gate, a source, and a drain, wherein one of the source and the drain is a connection end, and the other of the source and the drain is a feeding end;
An EL element electrically connected to the connection end;
A storage capacitor electrically connected to the gate and the source,
In the light emission period, a voltage corresponding to a light emission voltage is held in the storage capacitor, and a current corresponding to the light emission voltage is supplied to the EL element through the drive transistor,
In the non-light emitting period, the voltage corresponding to the non-light emitting voltage is held in the holding capacitor, and the voltage at the feeding end is set so that the current passing through the driving transistor does not flow to the EL element,
An EL display device configured such that the higher the light emission voltage is, the lower the non-light emission voltage is.
It is configured to repeat a frame composed of the light emission period and the non-light emission period,
The EL display device according to claim 1, wherein the frame having a higher light emission voltage has a lower state of the non-light emission voltage.
The EL display device according to claim 1, wherein the non-light emitting voltage is an inversion voltage symmetrical to the light emitting voltage with reference to an intermediate value in a setting range of the light emitting voltage.
The pixel circuit includes:
When the light emission voltage in the light emission period is equal to or lower than a switching value, the holding capacitor is set to a voltage that has the same polarity as the light emission voltage and is set lower as the light emission voltage is higher as the non-light emission voltage. Hold on to
4. The device according to claim 1, wherein when the light emission voltage in the light emission period is higher than the switching value, a voltage having a polarity different from the light emission voltage is held in the storage capacitor as the non-light emission voltage. 2. An EL display device according to item 1.
The pixel circuit includes:
The EL display device according to claim 4, wherein the non-light emission voltage is set to a constant value when the light emission voltage in the light emission period is higher than the switching value.
A detection operation for detecting a threshold voltage of the drive transistor in the non-light-emitting period;
The EL display device according to claim 1, wherein the light emission voltage is corrected in advance using a detection result obtained by a previous detection operation in the light emission period.
A method for driving an EL display device including a plurality of pixel circuits,
The pixel circuit includes:
A drive transistor having a gate, a source, and a drain, wherein one of the source and the drain is a connection end, and the other of the source and the drain is a feeding end;
An EL element electrically connected to the connection end;
A storage capacitor electrically connected to the gate and the source,
A light emission step of holding a voltage corresponding to a light emission voltage in the storage capacitor and flowing a current corresponding to the light emission voltage to the EL element through the drive transistor;
A voltage corresponding to a non-light-emitting voltage set so as to have a lower state as the light-emitting voltage is higher is held in the holding capacitor, and the power supply is performed so that a current passing through the driving transistor does not flow to the EL element. A non-light emitting process for setting the voltage at the end;
A method for driving an EL display device comprising:
The non-light emitting step further includes a detecting step of detecting a threshold voltage of the driving transistor,
The method for driving an EL display device according to claim 7, wherein, in the light emission step, the light emission voltage is corrected in advance using a detection result obtained in the previous detection step.