CN116343677A

CN116343677A - Electroluminescent display device

Info

Publication number: CN116343677A
Application number: CN202211259977.6A
Authority: CN
Inventors: 洪锡显; 金相润; 裵宰润
Original assignee: LG Display Co Ltd
Current assignee: LG Display Co Ltd
Priority date: 2021-12-16
Filing date: 2022-10-14
Publication date: 2023-06-27
Also published as: KR20230091666A; US20230196983A1

Abstract

The invention provides an electroluminescent display device. The electroluminescent display device includes: a pixel including a driving element having a gate electrode connected to the data line and a source electrode connected to a reference voltage line; and a pixel driving circuit applying a sensing data voltage to the gate electrode of the driving element through the data line in a plurality of vertical blanking periods, detecting a source electrode voltage of the driving element shifted from the sensing reference voltage based on the sensing data voltage through the reference voltage line to obtain a detection voltage, calculating an offset voltage based on the detection voltage, and lowering a level of the sensing data voltage based on the offset voltage.

Description

Electroluminescent display device

Cross reference to related applications

The present application claims the benefit of korean patent application No. 10-2021-0181004, filed on 12 months 16 of 2021, which is incorporated by reference as if fully set forth herein.

Technical Field

The present disclosure relates to electroluminescent display devices.

Background

In an electroluminescent display device having an active matrix type, a plurality of pixels each including a light emitting device and a driving element are arranged in a matrix type, and brightness of an image realized by the pixels is adjusted based on gray scale of image data. The driving element controls a pixel current flowing in the light emitting device based on a voltage applied between its gate electrode and source electrode (hereinafter referred to as a gate-source voltage). The amount of light emitted by the light emitting device and the brightness of the screen are determined based on the pixel current.

Since the threshold voltages of the driving elements determine the driving characteristics of the pixels, the threshold voltages of the driving elements in all the pixels should be equal, but the threshold voltages may be different from pixel to pixel due to various reasons such as process deviation and degradation characteristic deviation. Such a difference in threshold voltage causes a luminance deviation between pixels, and thus, there is a limit in realizing a desired image.

Conventional techniques for sensing and compensating for a difference in threshold voltage between driving elements are known, but it is difficult to apply the conventional techniques to real-time driving (i.e., display driving) of displaying an input image.

Disclosure of Invention

In order to overcome the above-described problems of the related art, the present disclosure may provide an electroluminescent display device for sensing and compensating a threshold voltage of a driving element in real-time driving.

To achieve these objects and other advantages and in accordance with the purpose of the disclosure, as embodied and broadly described herein, in one or more aspects, an electroluminescent display device may comprise: a pixel including a driving element having a gate electrode connected to the data line and a source electrode connected to a reference voltage line; and a pixel driving circuit for applying a sensing data voltage to the gate electrode of the driving element through the data line in a plurality of vertical blanking periods, detecting a source electrode voltage of the driving element shifted from the sensing reference voltage based on the sensing data voltage through the reference voltage line to obtain a detection voltage, calculating an offset voltage based on the detection voltage, and lowering a level of the sensing data voltage based on the offset voltage. The pixel driving circuit may apply an n-th (where n is a natural number of 2 or more) sensing data voltage to the gate electrode of the driving element in a vertical blanking period of an n-th frame, and may apply an n-1-th sensing data voltage to the gate electrode of the driving element in a vertical blanking period of an n-1-th frame before the n-th frame. The nth sensing data voltage may be lower than the n-1 th sensing data voltage.

In one or more aspects of the present disclosure, an electroluminescent display device may include: a pixel including a driving element including a gate electrode connected to the data line and a source electrode connected to a reference voltage line; and a pixel driving circuit for applying an nth (where n is a natural number of 2 or more) sensing data voltage to the gate electrode of the driving element through the data line, storing a source electrode voltage of the driving element shifted from the sensing reference voltage based on the nth sensing data voltage as an nth offset voltage, and calculating an nth detection voltage reduced by the nth offset voltage according to the nth sensing data voltage. The pixel driving circuit may apply the n-1 th sensing data voltage to the gate electrode of the driving element in a vertical blanking period of an n-1 th frame before the n-th frame. The nth sensing data voltage may be lower than the n-1 th sensing data voltage.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure. In the drawings:

Fig. 1 is a schematic view showing an electroluminescent display device according to an embodiment of the present disclosure;

fig. 2 is a diagram showing a configuration of a data driver connected to the pixel array and the power circuit of fig. 1;

fig. 3 is a diagram showing a connection configuration between a pixel driving circuit and a pixel for sensing a threshold voltage of a driving element included in the pixel;

fig. 4 is a diagram showing driving waveforms for implementing a conventional technical implementation in a comparative example for sensing driving the pixel driving circuit of fig. 3;

fig. 5A and 5B are diagrams showing a technical implementation for sensing a threshold voltage of a driving element in an embodiment of a pixel driving circuit of sensing driving fig. 3;

fig. 6 and 7 are diagrams showing application examples of the technical implementation of the present disclosure based on threshold voltage levels of driving elements;

fig. 8 is a diagram showing other connection configurations between a pixel driving circuit and a pixel for sensing a threshold voltage of a driving element included in the pixel;

fig. 9 is a diagram showing a driving waveform for driving the pixel driving circuit of fig. 8 displayed in a vertical effective period of a plurality of frames;

fig. 10A and 10B are diagrams showing a node voltage variation and a driving waveform of the pixel driving circuit of fig. 8 for the first sensing driving in the vertical effective period of the first frame;

Fig. 11A and 11B are diagrams showing a change in node voltage and a driving waveform of the pixel driving circuit of fig. 8 for the second sensing driving in the vertical effective period of the second frame;

fig. 12 is a diagram showing a driving waveform of the (n-1) -th sensing driving pixel driving circuit of fig. 8 in a vertical effective period of the n-1-th frame; and

fig. 13 is a diagram showing a driving waveform of the n-th sensing driving pixel driving circuit of fig. 8 in a vertical effective period of the n-th frame.

Detailed Description

Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the disclosure are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope and implementation of the disclosure to those skilled in the art.

The advantages and features of the present disclosure and methods of accomplishing the same may be apparent from the following embodiments described in connection with the accompanying drawings. Furthermore, the present disclosure is limited only by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing various embodiments of the present disclosure are merely exemplary, and the present disclosure is not limited thereto. Like numbers refer to like elements throughout. Like elements are denoted by like reference numerals throughout the specification. As used herein, the terms "comprising," "having," "including," and the like are intended to be inclusive and mean that additional portions may be added unless the term "only" is used. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

Elements in various embodiments of the present disclosure will be construed as including error ranges even if not explicitly indicated.

In describing the positional relationship, for example, when the positional relationship between two parts is described as "upper", "above", "below", and "immediately adjacent", one or more other parts may be located between the two parts unless "just" or "direct" is used.

It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.

Like numbers refer to like elements throughout.

In this specification, a pixel circuit provided on a substrate of a display panel may be implemented with a Thin Film Transistor (TFT) having an n-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) structure, but is not limited thereto, and may be implemented with a TFT having a p-type MOSFET structure. The TFT may be a three-electrode element including a gate electrode, a source electrode, and a drain electrode. The source may be an electrode that provides carriers to the transistor. In the TFT, carriers can flow from the source. The drain electrode may be an electrode that causes carriers to flow out of the TFT. That is, in the MOSFET, carriers flow from the source to the drain. In an n-type TFT (NMOS), since carriers are electrons, a source voltage may have a lower voltage than a drain voltage, so that electrons flow from a source to a drain. In an n-type TFT, since electrons flow from the source to the drain, current can flow from the drain to the source. On the other hand, in a p-type TFT (PMOS), since carriers are holes, the source voltage is higher than the drain voltage, so that holes flow from the source to the drain. In a p-type TFT, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed, but are switched between them. For example, the source and drain of a MOSFET may be switched between them.

Further, in the present disclosure, the semiconductor layer of the TFT may be implemented with at least one of an oxide element, an amorphous silicon element, and a polysilicon element.

In the following description, when a detailed description of related known functions or configurations is determined to unnecessarily obscure the gist of the present disclosure, the detailed description will be omitted. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

Fig. 1 is a diagram illustrating an electroluminescent display device according to an embodiment of the present disclosure. Fig. 2 is a diagram showing a configuration of a data driver connected to the pixel array and the power circuit of fig. 1.

Referring to fig. 1 and 2, an electroluminescent display device according to an embodiment of the present disclosure may include a display panel 10, a gate driving circuit 15, a timing controller 20, a data driving circuit 25, and a power circuit 30.

The display panel 10 may include a plurality of pixel lines PNL1 to PNL4, and each of the pixel lines PNL1 to PNL4 may include a plurality of pixels PXL and a plurality of signal lines. The "pixel line" described herein may not be a physical signal line, and may represent a set of signal lines and pixels PXL adjacent to each other in the extending direction of the gate line. The signal line may be connected to the pixel PXL. The signal line may include: a plurality of data lines 140 for supplying a display data voltage Vdata and a sensing data voltage Svdata to the pixels PXL; a plurality of reference voltage lines 150 for supplying a pixel reference voltage VPRER and a sensing reference voltage VPRES to the pixels PXL and reading an offset voltage VSIO from the pixels PXL; a plurality of gate lines 160 for supplying a gate signal SCAN to the pixels PXL; and a plurality of high-level power lines PWL for supplying high-level pixel voltages to the pixels PXL.

The pixels PXL of the display panel 10 may be arranged in a matrix to configure a pixel array. Each of the pixels PXL included in the pixel array may be connected to one of the data lines 140, one of the reference voltage lines 150, one of the high-level power lines PWL, and one of the gate lines 160. Each pixel PXL may also supply a low-level pixel voltage from the power circuit 30.

The timing controller 20 may generate a gate timing control signal GDC for controlling an operation timing of the gate driving circuit 15 and a data timing control signal DDC for controlling an operation timing of the data driving circuit 25 with reference to timing signals (e.g., a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE) input from a host system.

The data timing control signal DDC may include a source start pulse, a source sampling clock, and a source output enable signal, but is not limited thereto. The gate timing control signal GDC may include a gate start signal and a gate shift clock, but is not limited thereto.

The timing controller 20 may control operation timings of the gate driving circuit 15 and the data driving circuit 25 to sense driving characteristics of the pixels PXL in a vertical blanking period of each frame, and in this case, the timing controller 20 may sense driving characteristics of the same pixel a plurality of times by using a plurality of vertical blanking periods, thereby allowing sensing and compensating for threshold voltages of driving elements included in each pixel PXL in real-time driving in which an input image is displayed. The real-time sensing method according to the present embodiment may be the following method: based on the previous sensing result for the same pixel, the sensing data voltage SVdata to be applied to the same pixel is repeatedly and continuously reduced, and thus, the threshold voltage of the driving element included in the same pixel is sensed. According to the real-time sensing method, sensing accuracy can be improved, power consumption can be reduced, and a separate power-off period for sensing a threshold voltage of a driving element may not be required, thereby reducing power-off time. In addition, the threshold voltage of the driving element can be sensed and compensated in real-time driving without waiting for a power-off time, and thus display quality can be improved.

Here, the vertical blanking period may be a period in which the display DATA voltage Vdata disposed between adjacent vertical effective periods and corresponding to the image DATA is not supplied to the pixels. The vertical effective period may be a period in which the image DATA for the input video is converted into the display DATA voltage Vdata and supplied to the pixel PXL.

The timing controller 20 may control the sensing driving timing and the display driving timing of the pixel lines PNL1 to PNL4 of the display panel 10 based on a predetermined order, and thus may implement display driving and sensing driving. The display driving timing may correspond to a vertical active period, and the sensing driving timing may correspond to a vertical blanking period.

The timing controller 20 may variously generate the timing control signals GDC and DDC for the display driving and the timing control signals GDC and DDC for the sensing driving.

Each time the sensing data voltage SVdata lower than the previous data voltage is repeatedly applied to the sensing target pixel PXL based on the previous sensing result, the sensing drive may obtain a new sensing result from the corresponding pixel PXL, and may detect the sensing data voltage SVdata when the variation of the new sensing result is 0V as the driving characteristic (i.e., the threshold voltage of the driving element) of the corresponding pixel PXL. The sensing driving may further include an operation of updating a compensation value for compensating for a variation in driving characteristics of the corresponding pixel PXL. The timing controller 20 may compensate the input image DATA to be supplied to the corresponding pixel PXL based on the compensation value, thereby preventing degradation of image quality caused by a variation in threshold voltage of the driving element.

The display driving may mean correcting the digital image DATA to be input to the corresponding pixel PXL based on the updated compensation value, and applying the display DATA voltage Vdata corresponding to the corrected image DATA to the corresponding pixel PXL to display the input image.

The gate driving circuit 15 may be embedded in the display panel 10. The gate driving circuit 15 may be disposed in a non-display region (frame region) other than the display region in which the pixel array is disposed.

The gate driving circuit 15 may include a plurality of gate stages connected to the gate lines 160 of the pixel array. The gate stage may generate a gate signal SCAN for controlling the switching element of the pixel PXL and may supply the gate signal to the gate line 160. In the display driving, the gate signal SCAN may be used to select one pixel line to which the display data voltage Vdata is to be supplied. In the sensing driving, the gate signal SCAN may be used to select one pixel line to which the sensing data voltage SVdata is to be supplied.

The data driving circuit 25 may include a data voltage generating circuit DAC and a sensing circuit 22.

The data voltage generating circuit DAC may be connected to each data line 140 through each data channel DCH. The data voltage generation circuit DAC may be implemented as a digital-to-analog converter (DAC) that converts a digital signal into an analog signal. The data voltage generating circuit DAC may generate the sensing data voltage SVdata required for the sensing driving and the display data voltage Vdata required for the display driving, and supply the sensing data voltage SVdata and the display data voltage Vdata to the pixels PXL through the data lines 140.

The sensing circuit 22 may be connected to the reference voltage line 150 through each sensing channel SCH. The sensing circuit 22 may include a reference voltage circuit, a sampling circuit, and an analog-to-digital converter (see fig. 3), or may include a reference voltage circuit, a sampling circuit, an offset storage circuit, a calculation circuit, and an analog-to-digital converter (see fig. 8).

The sensing circuit 22 may supply the display reference voltage VPRER to the pixels PXL through the reference voltage line 150 in the display driving. In the sensing driving, the sensing circuit 22 may supply the sensing reference voltage VPRES to the pixels PXL through the reference voltage line 150.

In the sensing driving, the sensing circuit 22 may detect a source electrode voltage of a driving element shifted from a sensing reference voltage to a different level as a detection voltage through the reference voltage line 150 based on the sensing data voltage SVdata having a different level in a plurality of vertical blanking periods (see fig. 3).

In the sensing driving, the sensing circuit 22 may detect and store the source electrode voltages of the driving elements shifted from the sensing reference voltage to different levels as offset voltages through the reference voltage line 150 based on the sensing data voltages SVdata having different levels in a plurality of vertical blanking periods (see fig. 8).

The power circuit 30 may generate a high-level pixel voltage and a low-level pixel voltage to be supplied to the pixel PXL. Further, the power circuit 30 may generate the display reference voltage VPRER, the sensing reference voltage VPRES, and the ground voltage GND to be supplied to the sensing circuit 22. In order to satisfy the driving characteristics of the pixel PXL and the sensing range of the sensing circuit 22, the display reference voltage VPRER may be higher than the sensing reference voltage VPRES. The sensing reference voltage VPRES may have the same voltage level as the ground voltage GND, but is not limited thereto.

< first example embodiment >

Fig. 3 is an example of a diagram showing a connection configuration between a pixel driving circuit and a pixel for sensing a threshold voltage of a driving element included in the pixel.

Referring to fig. 3, the pixel PXL may include a light emitting device EL, a driving Thin Film Transistor (TFT) DT, a plurality of switching TFTs ST1 and ST2, and a storage capacitor Cst. The driving TFT DT and the switching TFTs ST1 and ST2 may each be implemented as an NMOS transistor, but are not limited thereto.

The light emitting device EL can emit light with the pixel current supplied from the driving TFT DT. The light emitting device EL may be implemented with an organic light emitting diode including an organic light emitting layer, or may be implemented with an inorganic light emitting diode including an inorganic light emitting layer. An anode electrode of the light emitting device EL may be connected to the source node N2, and a cathode electrode may be connected to an input terminal of the low-level pixel voltage EVSS.

The driving TFT DT may be a driving element that generates a pixel current based on its gate-source voltage. A gate electrode of the driving TFT DT may be connected to the gate node N1, a first electrode may be connected to an input terminal of the high-level pixel voltage EVDD through the high-level power line PWL, and a second electrode may be connected to the source node N2.

The switching TFTs STl and ST2 may be switching elements that set the gate-source voltage of the driving TFT DT and connect the first electrode of the driving TFT DT to the data line 140 or the second electrode of the driving TFT DT to the reference voltage line 150.

The first switching TFT STl may be connected between the data line 140 and the gate node Nl, and may be turned on based on a gate signal SCAN from the gate line 160. The first switching TFT STl may be turned on in the display driving or the sensing driving. When the first switching TFT ST1 is turned on, the display data voltage Vdata or the sensing data voltage SVdata may be applied to the gate node N1. A gate electrode of the first switching TFT ST1 may be connected to the gate line 160, a first electrode thereof may be connected to the data line 140, and a second electrode thereof may be connected to the gate node N1.

The second switching TFT ST2 may be connected between the reference voltage line 150 and the source node N2, and may be turned on based on a gate signal SCAN from the gate line 160. The second switching TFT ST2 may be turned on in the display driving or the sensing driving, and may apply the display reference voltage VPRER or the sensing reference voltage VPRES to the source node N2. The second switching TFT ST2 may be turned on in the sensing driving and may connect the source node N2 to the reference voltage line 150, and thus the voltage of the source node N2 reflecting the driving characteristics of the driving TFT DT may be charged into the reference voltage line 150. A gate electrode of the second switching TFT ST2 may be connected to the gate line 160, a first electrode thereof may be connected to the reference voltage line 150, and a second electrode thereof may be connected to the source node N2.

The storage capacitor Cst may be connected between the gate node Nl and the source node N2, and may maintain a gate-source voltage of the driving TFT DT in the display driving or the sensing driving.

The pixel PXL may allow the light emitting device EL to emit light at the first pixel current based on a voltage difference between the display data voltage Vdata and the display reference voltage VPRER in the display driving, and thus, an input image may be displayed. In addition, the pixel PXL may allow the source node N2 and the reference voltage line 150 to be charged with the second pixel current based on a voltage difference between the sensing data voltage SVdata and the sensing reference voltage VPRES in the display driving. In the sensing driving, the light emitting device EL does not emit light.

The pixels PXL may be connected to the pixel driving circuits PNL-DRV for sensing driving.

The pixel driving circuit PNL-DRV may include the reference voltage circuit INT, the sampling circuit SH, the analog-to-digital converter ADC, the timing controller 20, and the data voltage generating circuit DAC, and may further include the above-described gate driving circuit (not shown).

The reference voltage circuit INT may include: a first reference voltage switch RPRE for supplying the display reference voltage VPRER to the reference voltage line 150; and a second reference voltage switch SPRE for supplying the sensing reference voltage VPRES to the reference voltage line 150. The first reference voltage switch RPRE may be turned on in the display driving and may remain turned off in the sensing driving. The second reference voltage switch SPRE may be turned on in the sensing driving and may remain turned off in the display driving.

The sampling circuit SH may sample the voltage (detection voltage) of the reference voltage line 150 reflecting the source node voltage of the pixel PXL in the sensing driving. The sampling circuit SH may be configured with a sampling switch SAM, a sampling capacitor CSAM, and a HOLD switch HOLD. The sampling switch SAM may be connected between the reference voltage line 150 and the node NA, the sampling capacitor CSAM may be connected to the node NA at one electrode, and the HOLD switch HOLD may be connected between the node NA and the analog-to-digital converter ADC.

The analog-to-digital converter ADC may convert the output of the sampling circuit SH into the digital detection voltage VSIO and may supply the digital detection voltage VSIO to the timing controller 20.

The timing controller 20 may perform digital operations required for the sensing driving based on the digital detection voltage VSIO. In detail, the timing controller 20 may calculate a digital offset voltage based on the digital detection voltage VSIO. The timing controller 20 may previously store the digital level of the sensing reference voltage VPRES and the digital level of the sensing data voltage SVdata provided in the current vertical blanking period. The timing controller 20 may calculate a difference between the detection voltage VSIO and the sensing reference voltage VPRES as a digital offset voltage. When the digital offset voltage is greater than 0V, the timing controller 20 may decrease the digital level of the sensing data voltage SVdata to be supplied in the subsequent vertical blanking period by the digital offset voltage, and may supply the decreased sensing data voltage SVdata to the data voltage generating circuit DAC. Accordingly, the data voltage generating circuit DAC may generate the sensing data voltage SVdata reduced by the offset voltage in the sensing driving performed in the subsequent vertical blanking period, and may supply the generated sensing data voltage SVdata to the pixel PXL.

Further, when the digital offset voltage is 0V (i.e., when the detection voltage VSIO is equal to the sensing reference voltage VPRES), the timing controller 20 may determine the level of the sensing data voltage SVdata provided in the current vertical blanking period as the threshold voltage level of the driving element, and may stop the sensing operation of the corresponding pixel PXL.

In the sense driving, the operation of the pixel driving circuit PNL-DRV will be briefly described below.

In the vertical blanking period of the n-1 th frame, the reference voltage circuit INT may output the sensing reference voltage VPRES to the reference voltage line 150, the data voltage generation circuit DAC may output the n-1 th sensing data voltage SVdata to the data line 140, and the sampling circuit SH may sample the n-1 th sensing voltage VSIO through the reference voltage line 150. Then, the timing controller 20 may subtract the sensing reference voltage VPRES from the n-1 th sensing voltage VSIO to calculate an n-1 th offset voltage, and may calculate an n-th sensing data voltage Svdata, which decreases the n-1 th offset voltage, from the n-1 th sensing data voltage Svdata.

Subsequently, in the vertical blanking period of the nth frame, the reference voltage circuit INT may output the sensing reference voltage VPRES to the reference voltage line 150, the data voltage generating circuit DAC may output the nth sensing data voltage SVdata to the data line 140, and the sampling circuit SH may sample the nth detection voltage VSIO through the reference voltage line 150. Then, the timing controller 20 may subtract the sensing reference voltage VPRES from the nth detection voltage VSIO to calculate an nth offset voltage. For example, when the nth offset voltage is 0V, the timing controller 20 may detect the nth sensing data voltage as a threshold voltage of the driving element.

Fig. 4 is a diagram showing driving waveforms for implementing a conventional technical implementation in a comparative example for sensing driving the pixel driving circuit of fig. 3.

Referring to fig. 4, in the conventional art implementation, the driving element DT may operate based on a source follower scheme until a gate-source voltage difference Δv of the driving element DT is a threshold voltage Vth of the driving element DT. For this, the sensing data voltage SVdata may be supplied to the gate electrode of the driving element DT, and the sensing reference voltage VPRES may be supplied to the source electrode of the driving element DT. Based on the pixel current flowing in the driving element DT, the voltage Vs of the source node may increase toward the voltage Vg of the gate node, and such source follower operation may be continuously performed until the gate-source voltage difference Δv of the driving element DT is the threshold voltage Vth of the driving element DT (i.e., until the driving element DT is turned off).

According to the conventional art implementation, the voltage Vg of the gate node may be fixed by the sensing data voltage SVdata having a fixed level, and in this state, the sensing time XY taken until the gate-source voltage difference Δv of the driving element DT is the threshold voltage Vth of the driving element DT may be long because the voltage Vs of the source node gradually increases toward the voltage Vg of the gate node. Since the sensing time XY is much longer than the vertical blanking period BLK, it may be difficult to implement using conventional techniques in real-time driving (i.e., display driving) in which an input image is displayed.

Fig. 5A and 5B are diagrams showing a technical implementation for sensing a threshold voltage of a driving element in an embodiment for sensing and driving the pixel driving circuit of fig. 3.

The technical implementation of the present embodiment may be based on the pixel PXL and the pixel driving circuit PNL-DRV of fig. 3. Referring to fig. 5A, the pixel driving circuit PNL-DRV may repeat the sensing driving as in fig. 5 by using a plurality of vertical blank periods BLK until the threshold voltage Vth of the corresponding pixel PXL is detected. The pixel driving circuit PNL-DRV may accumulate the offset voltages V1 to Vn each time the sensing driving is repeated, and may decrease the level of the sensing data voltage SVdata by the accumulated offset voltage. Each time the sensing driving is repeated, the pixel driving circuit PNL-DRV may supply the sensing data voltage SVdata, which is reduced by the previous offset voltage, to the corresponding pixel PXL, and thus, may repeatedly obtain a new sensing result VSIO. As the sensing driving is repeated, the new sensing result VSIO may decrease, and thus, the pixel driving circuit PNL-DRV may detect the sensing data voltage SVdata when the change of the new sensing result VSIO is 0V as the driving characteristic (i.e., the threshold voltage of the driving element) of the corresponding pixel PXL.

According to the technical implementation of the present embodiment, the n-th sensing data voltage SVdata (Fn) applied to the gate electrode of the driving element in the vertical blanking period BLK of the n-th frame Fn may be lower than the n-1-th sensing data voltage SVdata (Fn-1) applied to the gate electrode of the driving element in the vertical blanking period BLK of the n-1-th frame Fn-1 preceding the n-th frame.

Further, the n-1-th detection voltage VSIO detected through the reference voltage line 150 in the vertical blanking period BLK of the n-1-th frame Fn-1 may be increased from the sensing reference voltage VPRES by the n-1-th offset voltage Vn-1, and the n-th detection voltage VSIO detected through the reference voltage line 150 in the vertical blanking period BLK of the n-th frame Fn may be increased from the sensing reference voltage VPRES by the n-th offset voltage Vn lower than the n-1-th offset voltage Vn. Accordingly, the nth sensing data voltage SVdata (Fn) may be an nth-1 offset voltage Vn-1 lower than the nth-1 sensing data voltage SVdata (Fn-1).

The nth sensing data voltage SVdata (Fn) may have

Is set in the above-described voltage level. Here, "VF1" may be the first sensing data voltage SVdata (F1) applied to the gate electrode of the driving element DT in the vertical blank period BLK of the first frame F1, and +.>

There may be a cumulative offset voltage obtained by summing the offset voltages V1 to Vn-1 of the vertical blanking period BLK from the first frame F1 up to the vertical blanking period BLK of the n-1 th frame Fn-1.

The timing at which the change of the new sensing result VSIO is 0V may be the timing at which the level of the new offset voltage is 0V. For example, when the nth offset voltage Vn is 0V, the nth sensing data voltage SVdata (Fn) may be detected as the threshold voltage Vth of the driving element. In this case, the threshold voltage Vth detection value may be "VF1- (v1+v2+vn-1)".

Fig. 6 and 7 are diagrams showing application examples of the technical implementation of the present disclosure based on the threshold voltage level of the driving element.

Referring to fig. 6, the threshold voltage Vth of the driving element may vary in a negative direction as in

cases

1 and 2, or may vary in a positive direction as in

cases

3 and 4. The threshold voltage levels for cases 1 through 4 may be different. In the technical implementation of the present disclosure, as shown in fig. 6, the sensing result may be obtained by supplying the sensing data voltage to the gate electrode of the driving element while reducing the sensing data voltage, and in this case, the sensing data voltage when the sensing result is not changed may be detected as the threshold voltage Vth of the driving element.

The output allowable range of the data voltage generation circuit DAC may be a positive voltage of 0V or more. The data voltage generation circuit DAC may not output a negative voltage. In

cases

3 and 4 where the threshold voltage Vth of the driving element is a positive voltage, since the sense data voltage detected as the threshold voltage Vth of the driving element is detected at different levels within a positive voltage range greater than 0V, the technical implementation of the present disclosure can be fully applied. On the other hand, in

cases

1 and 2 in which the threshold voltage Vth of the driving element is a negative voltage, since the sensing data voltage detected as the threshold voltage Vth of the driving element is saturated to the same 0V, the technical implementation of the present disclosure can be fully applied. When the technical implementations of the present disclosure are fully applied to

cases

1 and 2, an accurate threshold voltage may not be detected.

In order to solve such a problem, when the threshold voltage Vth of the driving element is 0V or less as in

cases

1 and 2, the pixel driving circuit PNL-DRV may obtain a specific sensing data voltage when the sensing result is not changed, convert the specific sensing data voltage into an estimated sensing data voltage lower than the specific sensing data voltage by using a predetermined lookup table LUT, and detect the estimated sensing data voltage as the threshold voltage Vth of the driving element. In the lookup table LUT, the level of the estimated sensing data voltage may be differently set based on the time when the specific sensing data voltage is 0V (N value of fig. 7). For example, since the timing at which the specific sensing data voltage is 0V is earlier in case 1 than in case 2, the estimated sensing data voltage of case 1 may be set to be lower than the estimated sensing data voltage of case 2.

In one or more examples, the value of N may vary from 1 to N (see fig. 6), where N may be a natural number. As the value of n decreases, the estimated sense data voltage may be set relatively low. In one or more examples, when n is a first value, the estimated sense data voltage may be set to a first voltage value. When n is a second value, the estimated sense data voltage may be set to a second voltage value. In this regard, the first voltage value is lower than the second voltage value when the first value may be lower than the second value.

< second example embodiment >

Fig. 8 is an example of a diagram showing another connection configuration between a pixel driving circuit and a pixel for sensing a threshold voltage of a driving element included in the pixel. The pixel PXL configuration of fig. 8 may be substantially the same as the pixel PXL configuration described for fig. 3. However, the pixel driving circuit PNL-DRV of fig. 8 may have a configuration different from that of fig. 3.

Referring to fig. 8, the pixels PXL may be connected to the pixel driving circuits PNL-DRV for sensing driving.

By using a plurality of vertical blanking periods, the pixel driving circuit PNL-DRV of fig. 8 may repeat the sensing driving until the threshold voltage of the corresponding pixel PXL is detected. The pixel driving circuit PNL-DRV may accumulate and store offset voltages by analog operation every time the sensing driving is repeated, and may reduce the level of the sensing data voltage by the accumulated offset voltage by analog operation. Each time the sensing driving is repeated, the pixel driving circuit PNL-DRV may supply the sensing data voltage reduced by the previous offset voltage to the corresponding pixel PXL, and thus may repeatedly obtain a new sensing result VSIO. The new sensing result VSIO may decrease with repetition of the sensing driving, and thus, the pixel driving circuit PNL-DRV may detect the sensing data voltage sensed when the change of the new sensing result VSIO is 0V as the driving characteristic (i.e., the threshold voltage of the driving element) of the corresponding pixel PXL. The pixel driving circuit PNL-DRV of fig. 3 may accumulate offset voltages through digital operation and may lower the level of the sensing data voltage by the accumulated offset voltages through digital operation, but there may be a difference in performing analog operation by using additional analog circuits included in the data driving circuit 25 in the pixel driving circuit PNL-DRV of fig. 8. Since the pixel driving circuit PNL-DRV of fig. 8 lowers the level of the sensing data voltage through analog operation, side effects such as digital noise caused by digital operation can be prevented.

The sensing operation of the pixel driving circuit PNL-DRV including the analog operation will be briefly described below. In the vertical blanking period of the nth frame (where n is a natural number of 2 or more), the pixel driving circuit PNL-DRV may apply the nth sensing data voltage to the gate electrode of the driving element DT through the data line 140, store the source voltage of the driving element DT shifted from the sensing reference voltage VPRES based on the nth sensing data voltage as the nth offset voltage, and calculate the nth detection voltage lower than the nth offset voltage according to the nth sensing data voltage. Here, the nth sensing data voltage may be lower than the nth-1 sensing data voltage applied to the gate electrode of the driving element DT in the vertical blanking period of the nth-1 frame before the nth frame.

The n-1 th sensing data voltage based on analog operation may have

Level, and the nth sensing data voltage may have +.>

A level. Here, "VF1" may be the initial sensing data voltage, +_f, applied to the gate electrode of the driving element DT>

May be a first accumulated offset voltage obtained by summing offset voltages up to a vertical blanking period of an n-1 th frame, an

The second accumulated offset voltage may be obtained by summing the offset voltages up to the vertical blanking period of the n-2 th frame before the n-1 th frame. In this case, the first accumulated offset voltage may be higher than the second accumulated offset voltage.

The pixel driving circuit PNL-DRV may calculate the nth sensing data voltage as the nth-1 detection voltage VSIO in the vertical blanking period of the nth-1 frame. The pixel driving circuit PNL-DRV may compare the nth detection voltage with the nth-1 detection voltage through a digital operation, and when the nth detection voltage is equal to the nth-1 detection voltage, the pixel driving circuit PNL-DRV may detect the nth detection voltage as a threshold voltage of the driving element.

For this, the pixel driving circuit PNL-DRV may include a reference voltage circuit INT, a sampling circuit SH, an analog-to-digital converter ADC, a timing controller 20, a data voltage generating circuit DAC, an offset storing circuit XX1, and an analog operating circuit XX2. The pixel driving circuit PNL-DRV may further include the above-described gate driving circuit (not shown).

The sampling circuit SH may sample the voltage (detection voltage) of the reference voltage line 150 reflecting the source node voltage of the pixel PXL in the sensing driving. The sampling circuit SH may be configured with a sampling switch SAM, a sampling capacitor CSAM, and a HOLD switch HOLD. The sampling switch SAM may be connected between the node NA and the node G connected to the reference voltage line 150, the sampling capacitor CSAM may be connected to the node NA at one electrode thereof, and the HOLD switch HOLD may be connected between the node NA and the analog-to-digital converter ADC.

The analog-to-digital converter ADC may convert the output of the sampling circuit SH into a digital detection voltage VSIO, and may supply the digital detection voltage VSIO to the timing controller 20.

The timing controller 20 may perform digital operations required for the sensing driving based on the digital detection voltage VSIO. In detail, the timing controller 20 may compare the current detection voltage (e.g., the nth detection voltage) with the previous detection voltage (e.g., the nth-1 detection voltage), and may repeat the sensing driving until the current detection voltage is equal to the previous detection voltage. That is, the timing controller 20 may compare the nth detection voltage with the nth-1 detection voltage, and when the nth detection voltage is equal to the nth-1 detection voltage, the timing controller 20 may detect the nth detection voltage as a threshold voltage of the driving element and may end the sensing driving.

The data voltage generation circuit DAC may generate a start sensing data voltage VFl in a vertical blanking period of each frame in which the sensing driving is performed, and may supply the start sensing data voltage VFl to the offset storage circuit XXl.

The offset storage circuit XX1 may include an odd capacitor CO and an even capacitor CE. The offset storage circuit XX1 may detect the accumulated offset voltage every time the sensing drive is repeated in the vertical blanking period of each frame up to a corresponding time, and may alternately store the accumulated offset voltage in the odd-numbered capacitor CO and the even-numbered capacitor CE.

The offset storage circuit XX1 may include an odd capacitor CO connected between a node a and a node B, an even capacitor CE connected between a node C and a node D, a first odd switch SWO-1 connected between a node NE and a node B, a first even switch SWE-1 connected between a node NE and a node D, a second odd switch SWO-2 connected between a node a and a node ND to which an initial sensing data voltage is applied, a second even switch SWE-2 connected between a node NC and a node a, a third odd switch SWO-3 connected between a node NC and a node C, a third even switch SWE-3 connected between a node ND and a node C, a fourth odd switch SWO-4 connected between a node D and a ground voltage source GND, a fourth even switch SWE-4 connected between a node B and a ground voltage source GND, and a first initialization switch INIT1 connected between a node NC and a ground voltage source GND.

The analog operation circuit XX2 may output an nth sensing data voltage obtained by subtracting the first accumulated offset voltage from the start sensing data voltage VFl to the data line 140, detect and store the nth offset voltage, and subtract the nth offset voltage from the nth sensing data voltage to calculate an nth detection voltage.

The analog operation circuit XX2 may include a first subtractor DIF1 and a second subtractor DIF2. The first subtractor DIF1 may include a first non-inverting input terminal (+) connected to the node NC, a first inverting input terminal (-) connected to the node ND, and a first output terminal connected to the node E. The second subtractor DIF2 may include a second non-inverting input terminal (+) connected to the node E, a second inverting input terminal (-) connected to the node NB, and a second output terminal connected to the data line 140 through the node F.

Further, the analog operation circuit XX2 may include a second initialization switch INIT2 connected between the node NB and the ground voltage source GND, a first switch SW1 connected between the node NB and the node H, a capacitor C connected to the node H, a second switch SW2 connected between the node H and the node NA, a third switch SW2 connected between the node F and the node G connected to the reference voltage line 150, and a fourth switch SW4 connected between the node NE and the node F.

Fig. 9 is a diagram showing a driving waveform for displaying a driving circuit for driving the pixel driving circuit of fig. 8 in a vertical effective period of a plurality of frames.

In order to display driving the pixel driving circuit PNL-DRV of fig. 8, the switch RPRE and the first and second initialization switches INIT1 and INIT2 may be turned on based on the SCAN signal SCAN in the vertical active period ACT. With the first and second initialization switches INIT1 and INIT2 turned on, the display data voltage generated by the data voltage generating circuit DAC may pass through the analog operation circuit XX2 and may be applied to the gate node N1 of the driving element DT. At this time, the display reference voltage VPRER may be applied to the source node N2 of the driving element DT through the switch RPRE. Then, a pixel current proportional to a voltage difference between the display data voltage and the display reference voltage VPRER may flow into the driving element DT, and based on such a pixel current, the light emitting device EL may emit light, so that an image may be realized with a luminance corresponding to a gray level of the display data voltage.

In addition, all of the switches SPRE, SAM, HOLD, SW1, SW2, SW3, SW4, SWO-1, SWO-2, SWO-3, SWO-4 and SWE-1, SWE-2, SWE-3, SWE-4 may be turned off in the display driving.

Fig. 10A and 10B are diagrams showing a change in node voltage and a driving waveform for first sensing driving the pixel driving circuit PNL-DRV of fig. 8 in the vertical effective period BLK of the first frame F1.

Referring to fig. 10A and 10B, the first sensing driving may be performed by the first to fifth periods P1 to P5.

In the first period Pl, the first initialization switch INITl and the third and fourth odd switches SWO-3 and SWO-4 of the offset storage circuit XXl may be turned on, and thus the even capacitor CE may be reset.

In the second period P2, the pixel current 1 proportional to the "start sensing data voltage VF 1-sensing reference voltage VPRES" may flow into the driving element DT of the pixel PXL. The voltage of the node G connected to the source node of the driving element DT may be increased by the first offset voltage V1 based on the pixel current 1.

In the third period P3, the node G may be connected to the capacitor C of the analog operation circuit XX2, and the first offset voltage V1, which is the voltage of the node G, may be stored in the capacitor C. Accordingly, the voltage of the node H connected to the capacitor C may be the first offset voltage V1.

In the fourth period P4, the subtraction operation between the start sensing data voltage VFl and the first offset voltage Vl may be performed by the second subtractor DIF2 of the analog operation circuit XX2, and the voltage of the node F connected to the output terminal of the second subtractor DIF2 may be "VF1-V1". Further, "VF1-V1", which is the voltage of the node F, may be supplied to the node B of the offset storage circuit XX1 through the fourth switch SW4 and the first odd switch SWO-1. At this time, the start-sensing data voltage VF1 has been supplied to the node a of the offset storage circuit XX 1. Thus, the first offset voltage V1 may be stored in the odd capacitor CO between the node a and the node B. In addition, "VF1-V1", which is the voltage of the node F, may be supplied to the node G through the third switch SW 3.

In the fifth period P5, "VF1-V1", which is the voltage of the node G, may be sampled by the sampling circuit SH and may be output to the timing controller 20 as the first detection voltage VSIO.

Fig. 11A and 11B are diagrams showing a change in node voltage and a driving waveform for the second sensing driving of the pixel driving circuit of fig. 8 in the vertical effective period of the second frame.

Referring to fig. 11A and 11B, the second sensing driving may be performed by the first to fifth periods P1 to P5.

In the first period P1, as the first to fourth even switches SWE-1 to SWE-4 of the offset storage circuit XX1 are turned on, "VF1" may be applied to the node C and "VF1-V1" may be applied to the node D, and thus, the first offset voltage V1 may be stored in the even capacitor CE of the offset storage circuit XX1 connected to the node C and the node D. At this time, the odd capacitor CO of the offset storage circuit XX1 may hold the first offset voltage V1 stored in the vertical blanking period of the first frame.

In the second period P2, the pixel current 2 proportional to "(VF 1-V1) -VPRES" may flow into the driving element DT of the pixel PXL. The voltage of the node G connected to the source node of the driving element DT may be increased by the second offset voltage V2 based on the pixel current 2. Here, the pixel current 2 may be lower than the above-described pixel current 1, and thus, the second offset voltage V2 may be lower than the above-described first offset voltage V1.

In the third period P3, the node G may be connected to the capacitor C of the analog operation circuit XX2, and the second offset voltage V2, which is the voltage of the node G, may be stored in the capacitor C. Accordingly, the voltage of the node H connected to the capacitor C may be the second offset voltage V2.

In the fourth period P4, the subtraction operation between "VF1-V1" and the first offset voltage V1 may be performed by the second subtractor DIF2 of the analog operation circuit XX2, and the voltage of the node F connected to the output terminal of the second subtractor DIF2 may be "VF 1-V2". In addition, "VF1-V1-V2", which is the voltage of the node F, can be supplied to the node D of the offset memory circuit XX1 through the fourth switch SW4 and the first even-numbered switch SWE-1. At this time, the start-sensing data voltage VF1 has been supplied to the node C of the offset storage circuit XX 1. Accordingly, the accumulated offset voltage "v1+v2" obtained by summing the first offset voltage V1 and the second offset voltage V2 may be stored in the even capacitor CE between the node C and the node D. In addition, "VF 1-V2", which is the voltage of the node F, may be supplied to the node G through the third switch SW 3.

In the fifth period P5, "VF 1-V2", which is the voltage of the node G, may be sampled by the sampling circuit SH and may be output to the timing controller 20 as the second detection voltage VSIO.

Fig. 12 is a diagram showing a driving waveform of the (n-1) -th sensing driving pixel driving circuit of fig. 8 in a vertical effective period of the n-1-th frame.

Referring to fig. 12, the (n-1) th sensing driving may be performed through the first to fifth periods P1 to P5. With the (n-1) -th sense drive, the n-1-th offset voltage Vn-1 may be stored in the capacitor C, and the voltage of the node F may be "VF 1-V2- … -Vn-1" based on the second subtractor DIF2 of the analog operation circuit XX 2. The accumulated offset voltage "v1+v2+ … +vn-1" may be stored in the odd capacitor CO of the offset storage circuit XX 1. Further, "VF 1-V2- … -Vn-1", which is the voltage of the node G, may be sampled by the sampling circuit SH and may be output to the timing controller 20 as the n-1 th detection voltage VSIO.

Referring to fig. 13, the nth sensing driving may be performed by the first to fifth periods P1 to P5. By the nth sensing driving, the nth offset voltage Vn may be stored in the capacitor C, and the voltage of the node F may be "VF 1-V2- … -Vn-1" based on the second subtractor DIF2 of the analog operation circuit XX 2. The accumulated offset voltage "v1+v2+ … +vn-1+vn" may be stored in the odd capacitor CO of the offset storage circuit XX 1. Further, "VF 1-V2- … -Vn-1-Vn" as the voltage of the node G may be sampled by the sampling circuit SH and may be output to the timing controller 20 as the nth detection voltage VSIO.

In the present embodiment, the same pixel may be sensed a plurality of times in succession by using a plurality of vertical blanking periods, and thus a threshold voltage of a driving element included in each pixel may be sensed and compensated in real-time driving in which an input image is displayed.

In the present embodiment, the sensing data voltage to be applied to the same pixel may be repeatedly and continuously reduced based on the previous sensing result for the same pixel, and thus, the threshold voltage of the driving element included in the same pixel may be sensed. According to the present embodiment, the accuracy of sensing may be improved, power consumption may be reduced, and a separate power-off period for sensing the threshold voltage of the driving element may not be required, thereby reducing power-off time. In addition, the threshold voltage of the driving element can be sensed and compensated in real-time driving without waiting for a power-off time, and thus display quality can be improved.

Effects according to the present disclosure are not limited to the above examples, and other various effects may be included in the specification.

While the present disclosure has been particularly shown and described with reference to exemplary embodiments, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims.

Claims

1. An electroluminescent display device comprising:

a pixel including a driving element having a gate electrode connected to a data line and a source electrode connected to a reference voltage line; and

a pixel driving circuit for applying a sensing data voltage to the gate electrode of the driving element through the data line in a plurality of vertical blanking periods, detecting a source electrode voltage of the driving element shifted from a sensing reference voltage based on the sensing data voltage through the reference voltage line to obtain a detection voltage, calculating an offset voltage based on the detection voltage, and lowering a level of the sensing data voltage based on the offset voltage,

wherein:

the pixel driving circuit is configured to apply an nth sensing data voltage to the gate electrode of the driving element in a vertical blanking period of an nth frame,

the pixel driving circuit is configured to apply an n-1 th sensing data voltage to the gate electrode of the driving element in a vertical blanking period of an n-1 th frame before the n-th frame,

the nth sensing data voltage is lower than the n-1 th sensing data voltage, and

where n is a natural number of 2 or greater.

2. The electroluminescent display device according to claim 1 wherein:

the pixel driving circuit is configured to detect an nth-1 detection voltage through the reference voltage line in a vertical blanking period of the nth-1 frame and increase the nth-1 detection voltage by an nth-1 offset voltage from the sensing reference voltage;

the pixel driving circuit is configured to detect an nth detection voltage through the reference voltage line in a vertical blanking period of the nth frame and increase the nth detection voltage by an nth offset voltage from the sensing reference voltage;

the n-th offset voltage is lower than the n-1-th offset voltage; and is also provided with

The nth sensing data voltage is lower than the nth sensing data voltage by the nth-1 offset voltage.

3. The electroluminescent display device according to claim 2, wherein the pixel driving circuit detects the nth sensing data voltage as a threshold voltage of the driving element when the nth offset voltage is 0V.

4. The electroluminescent display device according to claim 2, wherein the voltage level of the nth sensing data voltage is

And is also provided with

"VF1" is the first sensing data voltage applied to the gate electrode of the driving element in the vertical blanking period of the first frame, and

Is a cumulative offset voltage obtained by summing the offset voltages from the vertical blanking period of the first frame up to the vertical blanking period of the n-1 th frame.

5. The electroluminescent display device according to claim 1, wherein the pixel driving circuit detects the nth sensing data voltage as the threshold voltage of the driving element when the threshold voltage of the driving element is higher than 0V.

6. The electroluminescent display device according to claim 1, wherein when the threshold voltage of the driving element is lower than or equal to 0V,

the pixel driving circuit detects an estimated sense data voltage different from the nth sense data voltage as a threshold voltage of the driving element, and

the estimated sense data voltage is differently set based on a time when the nth sense data voltage is 0V.

7. The electroluminescent display device according to claim 6 wherein:

when n is a first value, the estimated sense data voltage is set to a first voltage value;

when n is a second value, the estimated sense data voltage is set to a second voltage value; and is also provided with

When the first value is lower than the second value, the first voltage value is lower than the second voltage value.

8. The electroluminescent display device according to claim 4, wherein the pixel driving circuit comprises:

a reference voltage circuit for outputting the sensing reference voltage to the reference voltage line in a vertical blanking period of the n-1 th frame;

a sampling circuit for sampling the n-1 th detection voltage through the reference voltage line in a vertical blanking period of the n-1 th frame;

a timing controller for subtracting the sensing reference voltage from the n-1 th sensing voltage to calculate the n-1 th offset voltage, and calculating the n-th sensing data voltage lower than the n-1 th sensing data voltage by the n-1 th offset voltage; and

a digital-to-analog converter for outputting the n-1 th sensing data voltage to the data line in a vertical blanking period of the n-1 th frame and outputting the n-th sensing data voltage to the data line in a vertical blanking period of the n-th frame.

9. The electroluminescent display device according to claim 8 wherein, in the vertical blanking period of the nth frame,

the reference voltage circuit is configured to output the sensing reference voltage to the reference voltage line,

The sampling circuit is configured to sample the nth detection voltage inputted through the reference voltage line, and

the timing controller is configured to subtract the sensing reference voltage from the nth detection voltage to calculate the nth offset voltage, and when the nth offset voltage is 0V, the timing controller detects the nth sensing data voltage as a threshold voltage of the driving element.

10. An electroluminescent display device comprising:

a pixel including a driving element including a gate electrode connected to a data line and a source electrode connected to a reference voltage line; and

a pixel driving circuit for applying an nth sensing data voltage to the gate electrode of the driving element through the data line, storing a source electrode voltage of the driving element shifted from a sensing reference voltage based on the nth sensing data voltage as an nth offset voltage, and calculating an nth detection voltage reduced by the nth offset voltage according to the nth sensing data voltage, where n is a natural number of 2 or more,

wherein:

the pixel driving circuit is configured to apply an n-1 th sensing data voltage to the gate electrode of the driving element in a vertical blanking period of an n-1 th frame before the n-th frame; and is also provided with

The nth sensing data voltage is lower than the n-1 th sensing data voltage.

11. The electroluminescent display device according to claim 10 wherein the nth sensing data voltage is at a level

The calculated number of the positions,

the n-1 th sensing data voltage is at a level

Where calculated, "VF1" is the initial sense data voltage applied to the gate electrode of the drive element, +.>

Is a first accumulated offset voltage obtained by summing the offset voltages up to the vertical blanking period of the n-1 th frame, and

is a second accumulated offset voltage obtained by summing the offset voltages up to the vertical blanking period of the n-2 th frame preceding the n-1 th frame, and

the first accumulated offset voltage is higher than the second accumulated offset voltage.

12. The electroluminescent display device according to claim 11, wherein the pixel driving circuit is configured to calculate the nth sensing data voltage as an nth-1 detection voltage in a vertical blanking period of the nth-1 frame, and

when the nth detection voltage is equal to the nth-1 detection voltage, the pixel driving circuit detects the nth detection voltage as a threshold voltage of the driving element.

13. The electroluminescent display device according to claim 12, wherein the pixel driving circuit comprises:

a reference voltage circuit for outputting the sensing reference voltage to the reference voltage line in a vertical blanking period of the nth frame;

an analog operation circuit for outputting the nth sensing data voltage obtained by subtracting the first accumulated offset voltage from the start sensing data voltage to a data line in a vertical blanking period of the nth frame, detecting and storing the nth offset voltage, and subtracting the nth offset voltage from the nth sensing data voltage to calculate the nth detection voltage;

an offset storage circuit for supplying the start sensing data voltage and the first accumulated offset voltage to the analog operation circuit in a vertical blanking period of the nth frame;

a digital-to-analog converter for supplying the start sensing data voltage to the offset storage circuit in a vertical blanking period of the nth frame;

a sampling circuit for sampling the nth detection voltage in a vertical blanking period of the nth frame; and

And a timing controller for determining whether the nth detection voltage is equal to the nth-1 detection voltage.

14. The electroluminescent display device according to claim 13 wherein the offset storage circuit comprises:

an odd capacitor connected between node a and node B;

an even capacitor connected between the node C and the node D;

a first odd switch connected between the node NE and the node B;

a first even-numbered switch connected between the node NE and the node D;

a second odd switch connected between node a and node ND, wherein the second odd switch is configured to receive the start sensing data voltage;

a second even-numbered switch connected between the node NC and the node a;

a third odd switch connected between the node NC and the node C;

a third even-numbered switch connected between the node ND and the node C;

a fourth odd switch connected between the node D and a node for a ground voltage source;

a fourth even-numbered switch connected between the node B and the node for the ground voltage source; and

a first initialisation switch connected between node NC and said node for the ground voltage source.

15. The electroluminescent display device according to claim 14, wherein the analog operation circuit comprises:

A first subtractor including a first non-inverting input terminal connected to the node NC, a first inverting input terminal connected to the node ND, and a first output terminal connected to the node E;

a second subtractor including a second non-inverting input terminal connected to node E, a second inverting input terminal connected to node NB, and a second output terminal connected to the data line through node F;

a second initialization switch connected between node NB and the node for the ground voltage source;

a first switch connected between node NB and node H;

a capacitor connected to node H;

a second switch connected between node H and node NA;

a third switch connected between the node F and a node G connected to the reference voltage line; and

a fourth switch connected between node NE and node F.

16. The electroluminescent display device according to claim 15, wherein the sampling circuit comprises:

a sampling switch connected between node G and node NA;

a sampling capacitor connected to node NA; and

a holding capacitor connected to node NA.

17. The electroluminescent display device according to claim 10, wherein the pixel driving circuit detects the nth sensing data voltage as the threshold voltage of the driving element when the threshold voltage of the driving element is higher than 0V.

18. The electroluminescent display device according to claim 10, wherein when the threshold voltage of the driving element is lower than or equal to 0V,

19. The electroluminescent display device according to claim 18 wherein: