TW201508722A - El display device and drive method for el display device - Google Patents

Abstract

An EL display device that, during a light-emission period, holds a voltage corresponding to a light-emission voltage in a storage capacitor (Cs) and causes a current corresponding to the light-emission voltage to flow to an EL element (11) via a drive transistor (Tr3). During a non-light-emission period, the EL display device holds a voltage corresponding to a non-light-emission voltage in the storage capacitor (Cs) and sets the voltage for a power supply end such that the current that has flowed through the drive transistor (Tr3) does not flow to the EL element (11). The EL display device has a state in which the non-light-emission voltage is lower the higher the light-emission voltage.

Description

EL display device and driving method of EL display device

The technology disclosed in the present disclosure relates to an EL display device including an Electro-Luminesence element (EL element, electroluminescence device) that supplies a current through a driving transistor, and a driving method of the EL display device.

The EL display device has a plurality of pixel circuits, and each of the plurality of pixel circuits includes a driving transistor, a sampling transistor, and a holding capacitor. The holding capacitor is connected between the gate and the source of the driving transistor, and the sampling transistor writes the voltage to the holding capacitor according to the level of the gray scale data. The driving electro-crystal system is configured to operate in a saturation region, and supplies a drain current in accordance with a voltage held by the holding capacitor to the EL element. The EL element is driven by the drain current and emits light in accordance with the luminance of the gray scale data (for example, refer to Patent Document 1).

[Previous Technical Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2010-128397

The voltage written by the sampling transistor to the holding capacitor imparts a single polarity to the gate-source of the driving transistor. EL showing image In the display device, such writing is repeated while the image is being displayed. Further, since the voltage is repeatedly applied to the gate and the source of the driving transistor with a single polarity, the shift of the threshold voltage between the gate and the source is performed in the driving transistor.

At this time, the voltage applied between the gate and the source of the driving transistor is in accordance with the level of the gray scale data, because the gray scale of the luminance obtained by each pixel is generally different, so The degree of displacement of the limit voltage also varies from pixel to pixel. As a result, each of the plurality of pixels constituting one display surface is different in brightness from the gray scale data.

An object of the technology of the present disclosure is to provide an EL display device and a driving method of an EL display device that suppress displacement of a threshold voltage of a driving transistor depending on each pixel.

One aspect of the EL display device of the present disclosure includes a plurality of pixel circuits including a driving transistor, an EL element, and a holding capacitor. The driving transistor system has a gate, a source and a drain, and the source is connected to one of the drains, and the other of the source and the drain is a power supply end. The EL element is electrically connected to the connection end, and the holding capacitor is electrically connected to the gate and the source. The EL display device is configured to maintain a voltage corresponding to a light-emitting voltage in the light-holding period during light-emitting, and to cause a current corresponding to the light-emitting voltage to flow to the EL element via the driving transistor; During the illuminating period, the holding capacitor maintains a voltage corresponding to the non-emissive voltage, and sets the voltage of the power supply terminal so that the current that has passed through the driving transistor does not flow to the EL element; the higher the illuminating voltage, the lower the illuminating voltage The lower the voltage state.

Another aspect of the EL display device of the present disclosure is a driving method of an EL display device including a plurality of pixel circuits including a driving transistor, an EL element, and a holding capacitor. The driving transistor system has a gate, a source and a drain, and the source is connected to one of the drains, and the other of the source and the drain is a power supply end. The EL element is electrically connected to the connection end, and the holding capacitor is electrically connected to the gate and the source. The driving method of the EL display device includes: a light emitting step of maintaining a voltage corresponding to a light emitting voltage at the holding capacitor, and causing a current corresponding to the light emitting voltage to flow to the EL element via the driving transistor; and a non-light emitting step, A voltage of a non-light-emitting voltage that is set so as to maintain a state in which the holding capacitance is lower than a state in which the light-emitting voltage is higher, and is set such that a current that has passed through the driving transistor does not flow to the EL element. The voltage at the supply terminal.

According to an aspect of the EL display device of the present disclosure, in each of the plurality of driving transistors, a voltage applied between the gate and the source is higher when the EL element emits light, and when the EL element does not emit light The lower. Therefore, the displacement of the threshold voltage of the driving transistor is suppressed depending on each pixel.

Another aspect of the EL display device of the present disclosure is configured to repeat a frame formed by the light-emitting period and the non-light-emitting period, and the frame having the higher light-emitting voltage has a lower non-light-emitting voltage. status.

According to another aspect of the EL display device of the present disclosure, each frame in the shortest period of display repetition suppresses the driving transistor The displacement of the threshold voltage varies from pixel to pixel.

In another aspect of the EL display device of the present disclosure, the non-light-emitting voltage is a reverse voltage symmetrical with the light-emitting voltage with an intermediate value in a set range of the light-emitting voltage as a reference.

According to another aspect of the EL display device of the present disclosure, an inverted voltage that is symmetrical with the light-emitting voltage is used as the non-light-emitting voltage. Therefore, the voltage applied between the gate and the source through one light-emitting period and one-time non-light-emitting period is uniform in a plurality of pixels. Therefore, the effect of suppressing the displacement of the threshold voltage of the driving transistor to be different depending on each pixel is further improved.

In another aspect of the EL display device of the present disclosure, the pixel circuit is configured to have the same polarity as the light-emitting voltage when the light-emitting voltage is the same as or lower than the switching value during the light-emitting period. Further, the higher the illuminating voltage is set, the lower the voltage is used as the non-emissive voltage, and is held by the holding capacitor; when the illuminating voltage is higher than the switching value during the illuminating period, the polarity is different from the illuminating voltage system. The voltage is held as the non-emissive voltage by the holding capacitor.

The higher the luminescence voltage during luminescence, the more the displacement of the threshold voltage of the driving transistor is performed. According to another aspect of the EL display device of the present disclosure, when the light-emitting voltage is higher than the switching value, the holding capacitor maintains a voltage corresponding to a non-light-emitting voltage having a polarity different from that of the light-emitting voltage. Therefore, in the case where the displacement of the threshold voltage of the driving transistor is excessively performed by the specific pixel, the displacement of the threshold voltage is suppressed for the specific pixel. As a result, the range in which the displacement of the threshold voltage of the driving transistor is suppressed depending on the respective pixels is expanded to the extent of the displacement of the threshold voltage.

In another aspect of the EL display device of the present disclosure, the pixel circuit is configured to set the non-light-emitting voltage to a constant value when the light-emitting voltage during the light-emitting period is higher than the switching value.

According to another aspect of the EL display device of the present disclosure, since the polarity is different from the illuminating voltage system, the non-light-emitting voltage is constant, so that it is possible to simplify the configuration required for the non-light-emitting voltage.

In another aspect of the EL display device of the present disclosure, the pixel circuit is configured to include a detection operation for detecting a threshold voltage of the driving transistor during the non-light-emitting period; and during the light-emitting period, The light-emitting voltage is corrected in advance using the detection result of the last detection operation.

In another aspect of the EL display device of the present disclosure, the non-illuminating step further includes a detecting step of detecting a threshold voltage of the driving transistor; and in the illuminating step, using the detection result of the detecting step last time, in advance Correct the illuminating voltage.

According to another aspect of the technology of the present disclosure, the change in the luminance of the EL element caused by the change in the threshold voltage of the driving transistor is suppressed.

According to the EL display device and the EL display device driving method of the present disclosure, it is possible to suppress the displacement of the threshold voltage of the driving transistor to be different for each pixel.

Β‧‧‧current amplification

T‧‧‧moderation time

Ce‧‧‧pixel capacitor

Cp‧‧‧ parasitic capacitance

Cs‧‧‧Resistance Capacitor

Id‧‧‧汲polar current

L1, L2‧‧‧ curve

La‧‧‧Power cord

Lb‧‧‧ grounding voltage line

Ld‧‧‧ data line

LP‧‧‧Latch pulse signal

Ls‧‧‧ scan line

MP‧‧‧masking pulse signal

Px‧‧ pixels

Ts‧‧‧saturated time

VD‧‧‧ luminous voltage

VDN‧‧‧ non-lighting voltage

VDN1‧‧‧1st non-lighting voltage

VDN2‧‧‧2nd non-lighting voltage

VM‧‧‧Detection voltage

Din‧‧‧Display information

11‧‧‧Organic EL components

PCC‧‧‧ drive circuit

SP1, SP2‧‧‧ start pulse signal

SW1‧‧‧ input switch

SW2‧‧‧ output switch

SWd‧‧‧ display switch

SWm‧‧‧Detection switch

SWs‧‧ ‧ voltage switch for detection

Tr1‧‧‧Sampling transistor

Tr2‧‧‧Switching transistor

Tr3‧‧‧ drive transistor

VEE‧‧‧ analog reference voltage

VgH‧‧‧Select voltage

VgL‧‧‧ non-selective voltage

Vgs‧‧‧ gate-source voltage

VLd‧‧‧ data line potential

Vth‧‧‧ threshold voltage

△Vth‧‧‧ displacement

Clkd‧‧‧ data displacement clock signal

Clks‧‧‧ shows displacement clock signal

Clkr‧‧‧Displacement clock signal for detection

Dout‧‧‧Test data

DVSS‧‧‧ analog power supply voltage

LVDD‧‧‧ logic supply voltage

LVSS‧‧‧Logical Reference Voltage

VLds‧‧‧Saturation voltage

ELVDD‧‧‧ drive voltage

ELVSS‧‧ ‧ reference voltage

SWtrs‧‧‧Transmission switch

WDVSS‧‧ ‧ write voltage

10‧‧‧ display panel

20‧‧‧Select drive

21‧‧‧Shift register circuit

22‧‧‧ position shifter circuit

23‧‧‧ snubber circuit

30‧‧‧Power Driver

40‧‧‧Data Drive

41‧‧‧Shift register circuit

42‧‧‧data register circuit

43‧‧‧ Data Latch Circuit

43a‧‧‧ Data Latch

44‧‧‧Voltage conversion circuit

45‧‧‧ buffer circuit

46‧‧‧ position shifter

50‧‧‧Control Department

51‧‧‧Image Signal Input Department

52‧‧‧Timing controller

53‧‧‧Memory Department

54‧‧‧Image Signal Processing Department

55‧‧‧Display data output department

60‧‧‧Logical power supply

70‧‧‧ analog power supply

Fig. 1 is a view showing the overall configuration of an EL display device of the first embodiment. Block diagram.

Fig. 2 is a block diagram showing the configuration of a control unit and a selection driver included in the EL display device of Fig. 1.

Fig. 3 is a block diagram showing the configuration of a data driver and a pixel circuit provided in the EL display device of Fig. 1.

Fig. 4 is a graph showing the relationship between the light-emitting voltage applied to the data line and the non-light-emitting voltage applied to the data line in the EL display device of Fig. 1.

Fig. 5 is a circuit diagram of a pixel circuit provided in the EL display device of Fig. 1 and is a view showing a state at the time of a write operation for light emission.

Fig. 6 is a circuit diagram of a pixel circuit provided in the EL display device of Fig. 1 and is a view showing a state at the time of light-emitting operation.

Fig. 7 is a circuit diagram of a pixel circuit provided in the EL display device of Fig. 1 and is a view showing a state at the time of a write operation for non-light-emitting.

Fig. 8 is a circuit diagram of a pixel circuit provided in the EL display device of Fig. 1 showing a state in which no light is emitted.

Fig. 9 is a timing chart showing the transition of the voltage applied to the scanning line and the power supply line during the light-emitting period of the EL display device of Fig. 1 and the transition of the control signal input to the data driver.

Fig. 10 is a timing chart showing the transition of the voltage applied to the scanning line and the power supply line during the period in which the EL display device of Fig. 1 is not illuminated, and the transition of the control signal input to the data driver.

Fig. 11 is a graph showing the relationship between the forward voltage applied to the EL element and the drive current flowing to the EL element in the EL display device of the second embodiment.

Fig. 12 is a potential correlation diagram showing the relative relationship between the voltages applied to the scanning lines, the power supply lines, and the data lines of the EL display device of the second embodiment, based on the ground voltage.

Fig. 13 is a graph showing the relationship between the light-emitting voltage applied to the data line and the non-light-emitting voltage applied to the data line in the EL display device of the second embodiment.

Fig. 14 is a circuit diagram of a pixel circuit included in the EL display device of the second embodiment, and is a view showing a state at the time of a write operation for non-light-emitting.

Fig. 15 is a circuit diagram of a pixel circuit included in the EL display device of the second embodiment, showing a state in which no light is emitted.

Fig. 16 is a block diagram showing the configuration of a control unit and a selection driver included in the EL display device of the third embodiment.

Fig. 17 is a block diagram showing the configuration of a data driver and a pixel circuit included in the EL display device of the third embodiment.

Fig. 18 is a timing chart showing the transition of the level of the control signal during the light-emitting period of the EL display device of the third embodiment together with the state of the switch.

Fig. 19 is a timing chart showing the transition of the level of the control signal in the non-light-emitting period of the EL display device of the third embodiment together with the state of the switch.

Fig. 20 is a graph showing the dependence of the driving transistor of the EL display device of the third embodiment on the luminescence voltage of the drain current.

Fig. 21 is a timing chart showing the transition of the level of the control signal of the detection operation of the EL display device of the third embodiment together with the state of the switch. Figure.

Fig. 22 is a graph showing the relationship between the potential of the data line and the relaxation time of the EL display device of the third embodiment.

Fig. 23 is a schematic diagram showing the timing of each operation performed in the first frame of the EL display device of the third embodiment for each of the pixels from the first column to the 540th column.

Fig. 24 is a schematic diagram showing the timing of each operation performed in the second frame of the EL display device of the third embodiment for each of the pixels from the first column to the 540th column.

Fig. 25 is a schematic diagram showing the timing of each operation performed in the 540th frame of the EL display device of the third embodiment for each of the pixels from the first column to the 540th column.

Fig. 26 is a timing chart showing the transition of the level of the control signal during the display of one frame in the EL display device of the third embodiment.

Fig. 27 is a graph showing the relationship between the light-emitting voltage applied to the data line and the non-light-emitting voltage applied to the data line in the EL display device according to the modification.

Fig. 28 is a graph showing the relationship between the light-emitting voltage applied to the data line and the non-light-emitting voltage applied to the data line in the EL display device according to the modification.

Fig. 29 is a circuit diagram showing a pixel circuit of an EL display device according to a modification.

Fig. 30 is a view showing the transition of the detection target of the threshold detection operation in each frame of the EL display device according to the modification.

Fig. 31 is a schematic diagram showing the transition of the detection target of the threshold detection operation in each frame of the EL display device according to the modification.

Fig. 32 is a schematic diagram showing the transition of the detection target of the threshold detection operation of each frame of the EL display device according to the modification.

[Formation of the Invention]

A first embodiment in which the EL display device and the EL display device driving method of the present disclosure are embodied will be described with reference to Figs. 1 to 10 .

[First Embodiment]

The overall configuration of the EL display device will be described with reference to Fig. 1 .

As shown in FIG. 1, the plurality of pixels Px included in the display panel 10 are arranged in an array of m columns x n rows. m is an integer of 1 or more, and n is also an integer of 1 or more. Each of the plurality of pixels Px has a pixel circuit including one organic EL element.

The m scanning lines Ls extending in the column direction and the n data lines Ld extending in the row direction intersect on the plan view of the display surface. Each of the plurality of pixels Px is located near the intersection of the scanning line Ls and the data line Ld. Each of the n pixels Px arranged along the column direction is connected to one scanning line Ls and one power supply line La. Each of the m pixels Px arranged along the row direction is connected to one data line Ld.

Each of the m scanning lines Ls is electrically connected to the selection driver 20. Each of the m power lines La is electrically connected to the power source driver 30. Each of the n data lines Ld is electrically connected to the data driver 40. The driving of each selection driver 20, the driving of the power driver 30, and the capital The drive of the material drive 40 is controlled by the control unit 50.

The control unit 50 has a central processing unit or a memory unit. The microcomputer is the center. The control unit 50 receives the video signal from the outside and uses the video signal to generate the display material Din of each pixel Px. The display material Din of each pixel Px is, for example, gray scale data composed of 8-bit elements. The control unit 50 inputs the display material Din of each pixel Px to the data driver 40.

The selection driver 20 is provided with a shift register or a buffer. The selection driver 20 applies any one of the selection voltage VgH that is higher than the reference voltage level to the non-selection voltage VgL that is lower than the reference voltage level in each of the scanning lines Ls in response to the control signal input from the control unit 50. The selection driver 20 sets the scanning line Ls to which the selection voltage VgH is applied as the selection target. The selection driver 20 sequentially switches the candidate of the selection target from the scanning line Ls of the first column to the scanning line Ls of the mth column of the last column, and repeats the switching of the candidates of the selection target.

The power driver 30 is provided with a shift register or a buffer. The power source driver 30 applies any one of the driving voltage ELVDD having a higher reference level to the reference voltage and the writing voltage WDVSS equal to the reference voltage to each of the power supply lines La in response to a control signal input from the control unit 50. The power source driver 30 sets the scanning line Ls to which the driving voltage ELVDD is applied as a supply target. The power source driver 30 sequentially switches the supply target from the power supply line La of the first column to the power supply line La of the mth column of the last column, and repeats the switching of the supply target. Further, the power source driver 30 is configured to select the driver 20 to be the kth column when the power source driver 30 is supplied to the kth column (k is an integer from 1 to m).

The data driver 40 uses the display data Din to generate light. Voltage VD or non-emissive voltage VDN. When the control unit 50 inputs the display data Din for generating the light-emission voltage VD to the data driver 40, the data driver 40 uses the display data Din to generate the light-emission voltage VD. When the control unit 50 inputs the display material Din for generating the non-light-emitting voltage VDN to the data driver 40, the data driver 40 uses the display material Din to generate the non-light-emitting voltage VDN.

The data driver 40 is connected to each data line Ld during illumination. A luminescence voltage VD is generated. The data driver 40 applies a light-emission voltage VD to each of the n data lines Ld in response to a control signal input from the control unit 50.

The data driver 40 is connected to each data line during non-lighting period. Ld produces a non-emissive voltage VDN. The data driver 40 applies a non-light-emitting voltage VDN to each of the n data lines Ld in response to a control signal input from the control unit 50.

[Configuration of Control Unit 50]

The configuration of the control unit 50 will be described with reference to Fig. 2 . As shown in FIG. 2, the control unit 50 includes a video signal input unit 51, a timing controller 52, a storage unit 53, a video signal processing unit 54, and a display material output unit 55.

The video signal input unit 51 holds the video signal input to the control unit 50, and outputs the held video signal to the storage unit 53. The memory unit 53 stores the video signal output from the video signal input unit 51, and outputs the stored video signal to the video signal processing unit 54. The display data output unit 55 outputs the processing result of the video signal processing unit 54 as the display data Din to the data drive 40.

The memory unit 53 memorizes the light-emitting voltage VD and the non-light-emitting power Information on the relationship between VDN. The video signal processing unit 54 generates a display for generating the non-light-emitting voltage VDN by using the relationship between the display data Din for generating the light-emission voltage VD and the light-emitting voltage VD and the non-light-emitting voltage VDN for each pixel Px in one frame. Information Din.

The timing controller 52 controls the image signal to the memory unit 53 The write timing and the read timing of the video signal to the memory unit 53. The timing controller 52 controls the processing timing of the video signal processing unit 54. The timing controller 52 generates a data displacement clock signal Clkd and a display displacement clock signal Clks. The timing controller 52 outputs the data displacement clock signal Clkd to the data driver 40, and outputs the display displacement clock signal Clks to the selection driver 20 and the power source driver 30.

The video signal processing unit 54 reads out from the storage unit 53. The image signal generates gray scale data for illumination of each pixel Px. The video signal processing unit 54 applies gamma correction, brightness adjustment, and chromaticity adjustment to the gray scale data for light emission of each pixel Px. The video signal processing unit 54 adjusts the gradation data for illumination of each pixel Px by using, for example, a lookup table for performing various adjustments and an image signal input from the video signal processing unit 54. The video signal processing unit 54 outputs the adjusted gray scale data for illumination as the display data Din to the display material output unit 55 during the light emission period. The video signal processing unit 54 generates grayscale data for non-light-emitting pixels of each pixel Px that does not emit light in the EL element, and displays the generated display data Din to the display material output unit 55. .

The data driver 40 is used to display the input during the lighting period. The data Din is displayed, and the illuminating voltage VD is generated from the display data Din. The data driver 40 uses the display material Din input during the non-lighting period to generate a non-light-emitting voltage VDN from the display material Din.

The data shift clock signal Clkd determines the display of each pixel Px The timing at which the data Din is input from the display material output unit 55 to the data driver 40 is shown. The data driver 40 changes the display data Din corresponding to the pixel Px of the first row, the display data Din corresponding to the pixel Px of the second row, and the data corresponding to the nth row every time the data shift clock signal Clkd rises. The order of the display data Din of the pixel Px is input to the display material Din of each pixel Px. The data driver 40 associates the display data Din of each pixel Px with the data line Ld to which the pixel Px is connected in accordance with the clock cycle of the data shift clock signal Clkd.

Displaying the displacement clock signal Clks during the illumination period The switching cycle of the candidate of the selection target and the switching cycle of the candidate of the supply target. Further, the display displacement clock signal Clks is determined not to be in the non-light-emitting period, but also to determine the switching cycle of the candidate to be selected and the switching cycle of the candidate to be supplied. The selection driver 20 selects the scanning lines one by one in the order of the scanning line Ls of the first column, the scanning line Ls of the second column, the scanning line Ls of the second column, and the scanning line Ls of the mth column, each time the selection drive pulse signal Clks rises. Ls. The power driver 30 selects the power line one by one in the order of the power line La of the first column, the power line La of the second column, the power line La of the second column, and the power line La of the mth column, each time the display displacement pulse signal Clks rises. La. It is shown that the clock period for displaying the clock period of the displacement clock signal Clks is longer than the clock period of the data shift clock signal Clkd. For example, the display clock cycle is n times the clock period of the data shift clock signal Clkd.

The timing controller 52 generates a start pulse signal SP1 and an artery The signal SP2 and the latch pulse signal LP. The timing controller 52 inputs the start pulse signal SP1 and the latch pulse signal LP to the data driver 40. The timing controller 52 inputs the start pulse signal SP2 to the selection driver 20 and the power source driver 30.

The start pulse signal SP1 controls the data driver 40 The timing control signal controls the timing at which the display data Din of one column is input from the display material output unit 55 to the data driver 40. Each time the data driver 40 inputs the start pulse signal SP1, only the display data Din corresponding to the pixel Px of the first row of the m column and the display data Din corresponding to the pixel Px of the nth row of the m column are taken into each of the columns. The display data Din of the pixel Px.

The latch pulse signal LP controls the data driver 40 The timing control signal controls the data driver 40 to maintain a sequence of display data Din. The data driver 40 maintains one column of display data from the display data Din corresponding to the pixel Px of the first row of the m column to the display data Din corresponding to the pixel Px of the nth row of the m column, every time the latch pulse signal LP is input. Din.

The start pulse signal SP2 controls where the drive 20 is selected The control signal of the timing is controlled every time the candidate of the selection target is switched m times, and the start timing of the switching of the candidates of the selection target is controlled. The start pulse signal SP2 is a control signal for controlling the processing timing of the power source driver 30, and controls the start timing of the switching of the candidate to be supplied every time the candidate of the supply target is switched m times. The selection driver 20 sequentially switches the scanning line Ls of the first column to the scanning line Ls of the m-th column every time the start pulse signal SP2 is input as a candidate for selection. The power driver 30 is required to input a start pulse signal every time. SP2, as a candidate for supply, sequentially switches from the power supply line La of the first column to the power supply line La of the mth column.

[Structure of Selecting Driver 20]

The configuration of the selection driver 20 will be described with reference to Fig. 2 . Further, the configuration of the candidate for selection of the power source driver 30 is the same as the configuration of the candidate for selection and selection of the selection driver 20. Therefore, the configuration of the selection driver 20 will be described in detail below, and the description of the configuration of the power source driver 30 will be omitted.

As shown in FIG. 2, the control unit 50 inputs the start pulse signal SP2 and the display displacement clock signal Clks to the shift register circuit 21. The shift register circuit 21 generates a parallel signal including m bits of one selected object bit for each input start pulse signal SP2, and outputs the parallel signal as a displacement signal. The shift register circuit 21 pairs each of the display displacement pulse signals Clks so that one of the selection target bits of the displacement signal corresponds from the position corresponding to the pixel Px of the first column to the pixel Px of the mth column. The position is sequentially shifted by one column of pixels Px.

The shift register circuit 21 inputs the displacement signal to the level shifter circuit 22. The level shifter circuit 22 is connected to a voltage regulating circuit of a low withstand voltage circuit and a high withstand voltage circuit, and adjusts the voltage of the displacement signal to the driving level of the buffer circuit 23. The level shifter circuit 22 inputs the displacement signal of the driving level of the buffer circuit 23 to the buffer circuit 23. The buffer circuit 23 adjusts the voltage of the displacement signal to the driving level of the pixel Px.

[Configuration of Data Driver 40]

The configuration of the data drive 40 will be described with reference to Fig. 3.

As shown in FIG. 3, the data driver 40 is provided with a shift register circuit 41. The data register circuit 42, the data latch circuit 43, the voltage conversion circuit 44, and the buffer circuit 45. The shift register circuit 41, the data register circuit 42, and the data latch circuit 43 are formed as low-voltage circuits, and the logic power supply 60 applies a high-level logic supply voltage LVDD and a low-level logic reference voltage LVSS. These circuits. The voltage conversion circuit 44 and the buffer circuit 45 are configured as a high withstand voltage circuit, and the analog power supply 70 applies a high level analog power supply voltage DVSS and a low level reference voltage VEE to these circuits. The analog power supply voltage DVSS is set to a level equal to the write voltage WDVSS and the reference voltage ELVSS.

When the control unit 50 shifts the start pulse signal SP1 and the data The pulse signal Clkd is input to the shift register circuit 41. The shift register circuit 41 generates a parallel signal including n bits of one selected object bit for each input start pulse signal SP1, and outputs the parallel signal as a displacement signal. The shift register circuit 41 shifts the clock signal Clkd every time the input data is shifted, so that a selected object bit of the displacement signal is sequentially shifted and output.

The control unit 50 inputs the display data Din to the data register Circuit 42. The display material Din is, for example, gray scale data composed of 8-bit elements. The data register circuit 42 includes n register memories corresponding to the bits of the shift signal, and one register takes in the display data Din of each pixel Px. The data register circuit 42 inputs the display data Din of each pixel Px to a register selected by a selection target bit each time. The data register circuit 42 selects all the registers by the displacement of one selected object bit, and takes a column of the display data Din into the n registers.

The control unit 50 inputs the latch pulse signal LP to the data lock The circuit 43 is stored. The data latch circuit 43 includes n material latches 43a that are associated with the respective registers of the data register circuit 42. Each of the n data latches 43a is coupled to the data register circuit 42 and electrically connected to mutually different registers. Each of the n data latches 43a holds the display material Din memorized by the register connected to the object, and repeats the hold for each latch pulse signal LP. Each of the n data latches 43a inputs the held display data Din to the voltage conversion circuit 44. The data latch circuit 43 holds the display data Din of one of the columns taken in by the data register circuit 42 every time the latch pulse signal LP is input, and inputs the display data Din of one of the columns to the voltage conversion circuit 44. .

Voltage conversion circuit 44 is provided with a linear voltage digital-analog The n display DACs 44a of the conversion circuit. Each of the n display DACs 44a is connected to the data latch circuit 43 via a different level shifter 46a, and is electrically connected to the data latch 43a different from each other. Each of the n display DACs 44a converts the display data Din held by the data latch 43a of the connection object into an analog voltage. The analog voltage output by the display DAC44a is linear to the input digital data. The analog voltage converted by the display DAC 44a is set to be between the analog supply voltage DVSS and the analog reference voltage VEE applied from the analog power supply 70.

The buffer circuit 45 is provided with n buffers 45a. n buffers Each of 45a is connected to the voltage conversion circuit 44, and is electrically connected to the display DAC 44a different from each other. Further, each of the n buffers 45a is electrically connected to the data lines Ld different from each other. Each of the n buffers 45a amplifies the analog voltage generated by the display DAC 44a of the connection target to the driving level of the pixel circuit. Each of the n buffers 45a is illuminated During this period, a light-emission voltage VD corresponding to the display material Din of each pixel Px is generated. Further, each of the n buffers 45a generates a non-light-emitting voltage VDN corresponding to the display material Din of each pixel Px during the non-light-emitting period.

[Configuration of Drive Circuit PCC]

The configuration of the drive circuit PCC will be described with reference to Fig. 3 .

As shown in FIG. 3, the pixel Px includes an EL element 11 and a driving circuit PCC that causes the EL element 11 to emit light. The drive circuit PCC includes three transistors Tr1 to Tr3 and a holding capacitor Cs. The transistors Tr1 to Tr3 are n-channel type transistors.

In the sampling transistor Tr1, the source is electrically connected to the data line Ld, the drain is electrically connected to the anode of the EL element 11, and the gate is electrically connected to the scanning line Ls. When the selection voltage VgH is applied to the scanning line Ls, the sampling transistor Tr1 is turned on. On the other hand, when the non-selection voltage VgL is applied to the scanning line Ls, the sampling transistor Tr1 is in a non-conduction state.

In the switching transistor Tr2, the source is electrically connected to the gate of the driving transistor Tr3, the drain is electrically connected to the power line La, and the gate is electrically connected to the gate of the sampling transistor Tr1. When the selection voltage VgH is applied to the scanning line Ls, the switching transistor Tr2 is turned on. On the other hand, when the non-selection voltage VgL is applied to the scanning line Ls, the switching transistor Tr2 is turned off.

In the driving transistor Tr3, the source of one of the connection terminals is electrically connected to the anode of the EL element 11, and the gate of one of the power supply terminals is electrically connected to the gate of the switching transistor Tr2, and the gate is connected. The source of the switching transistor Tr2 is electrically connected.

The holding capacitor Cs will drive the gate and source of the transistor Tr3 Electrical connection between them. The holding capacitor Cs may also be a parasitic capacitance formed between the gate and the source of the driving transistor Tr3, and may also connect other capacitive elements in parallel with the parasitic capacitance.

The cathode system of the EL element 11 and an example of a reference voltage line The ground voltage line Lb is electrically connected. The ground voltage line Lb is set to the reference voltage ELVSS, and the reference voltage ELVSS is at a high level to the analog reference voltage VEE and is equal to the level of the analog power supply voltage DVSS. Further, in the pixel Px, the pixel capacitance Ce is included in the EL element 11, and the parasitic capacitance Cp is included in the data line Ld.

[No illuminating voltage VDN]

Referring to Fig. 4, the relationship between the light-emission voltage VD and the non-light-emitting voltage VDN will be described. Fig. 4 is a graph showing the relationship between the corresponding light-emission voltage VD and the non-light-emitting voltage VDN given by the video signal processing unit 54.

As shown in FIG. 4, the non-light-emitting voltage VDN is associated with the light-emission voltage VD. When the reference voltage ELVSS and the write voltage WDVSS are set to 0 V and the polarity of the drive voltage ELVDD is set to be positive, the polarity of the light-emission voltage VD and the polarity of the non-light-emitting voltage VDN are both negative. The non-light-emitting voltage VDN is lower as the corresponding light-emitting voltage VD is given higher.

For example, when the light-emission voltage VD is -10 V, 0 V is given as the non-light-emitting voltage VDN, and when the light-emission voltage VD is -8 V, the non-light-emitting voltage VDN, -2 V is given a correspondence. NK, when the illuminating voltage VD is 0 V, is assigned as a non-light-emitting voltage VDN, -10 V.

In the range in which the light-emitting voltage VD is set, -5V is an intermediate value, and the non-light-emitting voltage VDN is an intermediate value as a reference, and a light-emitting voltage VD Symmetrical reverse voltage. Further, the range in which the light-emission voltage VD is set is appropriately set in accordance with the reference voltage, the write voltage WDVSS, the drive voltage ELVDD, and the driving of the EL element 11, and may be other than 0V to -10V.

Moreover, the control unit 50 is configured to face each pixel in one frame. Px is configured to generate display data Din for generating the light-emission voltage VD and display data Din for generating the non-light-emitting voltage VDN which is the inverted voltage of the light-emitting voltage VD. For example, the video signal processing unit 54 of the control unit 50 includes a difference circuit for generating a difference value between the display data Din (light-emitting gray scale data) of the light-emission voltage VD and the highest-order threshold value of the display data Din. Further, the video signal processing unit 54 of the control unit 50 generates the display data Din for generating the light-emission voltage VD, applies the display data Din to the differential circuit, and generates display data Din for generating the non-light-emitting voltage VDN (not Gray scale data for lighting).

Referring to Figures 5 to 8, the applied illuminating voltage VD will be described. The function of the driving circuit PCC with the non-lighting voltage VDN.

As shown in FIG. 5, when the write voltage WDVSS is applied to the power supply line La and the selection voltage VgH is applied to the scanning line Ls, the sampling transistor Tr1 and the switching transistor Tr2 are turned on. When the sampling transistor Tr1 and the switching transistor Tr2 are in an on state, the driving transistor Tr3 is driven in the saturation region. In this state, when the light-emitting voltage VD is applied to the data line Ld, the write voltage corresponding to the potential difference between the voltage of the power supply line La and the voltage of the data line Ld is held as the gate-source voltage Vgs of the driving transistor Tr3. The capacitor Cs is maintained.

At this time, because the illuminating voltage VD is higher than the reference voltage ELVSS is lower level, so in the EL element 11, the EL element 11 is applied. Reverse voltage. Further, since the light-emission voltage VD is lower than the write voltage WDVSS, the current Ie flowing through the drive transistor Tr3 does not flow to the EL element 11, but is drawn toward the data line Ld.

As shown in Figure 6, the write voltage for illumination is kept charged. When the capacitance Cs is maintained, when the non-selection voltage VgL is applied to the scanning line Ls, the sampling transistor Tr1 and the switching transistor Tr2 are in a non-conduction state. In this state, when the driving voltage ELVDD is applied to the power supply line La, since the driving voltage ELVDD is higher than the reference voltage ELVSS, the driving transistor Tr3 is caused to flow in accordance with the gate-source voltage Vgs. To the EL element 11. At this time, the drain current of the driving transistor Tr3 is in the saturation region thereof, and is varied in accordance with the difference between the gate-source voltage Vgs and the threshold voltage Vth of the driving transistor Tr3. As a result, the drain current flows to the EL element 11 in response to the difference between the write voltage held by the holding capacitor Cs and the threshold voltage Vth of the driving transistor Tr3.

As shown in Figure 7, a write voltage is applied to the power line La. When the selection voltage VgH is applied to the WDVSS and the scanning line Ls, the sampling transistor Tr1 and the switching transistor Tr2 are turned on. When the sampling transistor Tr1 and the switching transistor Tr2 are in an on state, the driving transistor Tr3 is driven in the saturation region. In this state, when the data line Ld is applied with the non-light-emitting voltage VDN, the write voltage corresponding to the potential difference between the voltage of the power supply line La and the voltage of the data line Ld is used as the gate-source voltage Vgs of the driving transistor Tr3. The holding capacitor Cs is held.

At this time, because the non-emissive voltage VDN is higher than the reference voltage ELVSS is lower level, so in the EL element 11, the reverse voltage of the EL element 11 is applied. Also, because the non-emissive voltage VDN is higher than the write voltage Since WDVSS is lower, the current Iue flowing through the driving transistor Tr3 does not flow to the EL element 11, but is pulled in toward the data line Ld.

Here, the plurality of pixels Px included in the EL display device Each of them is repeatedly applied with the illuminating voltage VD during the display of the image. Further, since the application of the illuminating voltage VD having a single polarity is repeated between the gate and the source of the driving transistor Tr3, the displacement of the threshold voltage between the gate and the source is performed in the driving transistor Tr3. Further, since the non-light-emitting voltage VDN also has the same polarity as the light-emission voltage VD, the displacement of the threshold voltage is also performed by the application of the non-light-emitting voltage VDN. At this time, since the non-light-emitting voltage VDN is the inverted voltage of the light-emission voltage VD, the lower the gate-source voltage Vgs of the drive transistor Tr3 is, the higher the light-emitting voltage VD is. Therefore, in each of the plurality of pixels Px, the larger the displacement caused by the application of the illuminating voltage VD, the smaller the displacement caused by the application of the illuminating voltage VDN; conversely, the application of the illuminating voltage VD The smaller the displacement, the greater the displacement caused by the application of the non-illuminating voltage VDN. As a result, in the plurality of pixels Px whose emission voltages VD are different from each other, the displacement of the threshold voltage can be made uniform.

As shown in Figure 8, the write voltage for non-illumination is maintained. When the capacitor Cs is held, when the non-selection voltage VgL is applied to the scanning line Ls, the sampling transistor Tr1 and the switching transistor Tr2 are in a non-conduction state. In this state, when the write voltage WDVSS is continuously applied to the power supply line La, the current does not flow to the drive transistor Tr3 as in the above-described write. Further, since the source of the driving transistor Tr3 after the writing operation is lower than the reference voltage ELVSS, the reverse voltage is continuously applied to the EL element 11.

[The role of EL display device]

The operation of the EL display device during the light-emitting period and the operation of the EL display device during the non-light-emitting period will be described with reference to FIGS. 9 and 10. First, the operation during the light emission period of the EL display device will be described.

As shown in FIG. 9, at timing td1, the control unit 50 inputs the start pulse signal SP1 to the data driver 40. Thereby, the shift register circuit 41 inputs the shift signal into the data register circuit 42, and the data register circuit 42 takes in the display data Din of the first column. Then, the control unit 50 inputs the start pulse signal SP2 to the selection driver 20 and the power source driver 30.

At the timing td2, the control unit 50 applies the selection voltage VgH to the scanning line Ls of the first column, and turns the sampling transistors Tr1 of the first column and the switching transistors Tr2 of the first column into an ON state. Moreover, the control unit 50 inputs the latch pulse signal LP to the data driver 40, whereby each of the material latches 43a holds the display data Din of the first column. The display data Din of the first column held by the n data latches 43a is converted into an analog voltage by the n display DACs 44a via the n level shifters 46a, and is applied to the respective data lines Ld as the light-emission voltage VD. .

On the other hand, the control unit 50 continuously applies the write voltage WDVSS to the power line La of the first column. As a result, the gate-source voltage Vgs of each of the driving transistors Tr3 in the first column is a value corresponding to the difference between the address voltage WDVSS and the light-emission voltage VD, and is held as a write voltage by the holding capacitor Cs. Thereby, the control unit 50 sets the gate-source voltage Vgs in the forward direction in which the driving transistor Tr3 is held for each pixel Px in the first column, and makes each of the driving transistors Tr3 in the first column configurable. After the state of the saturation region is driven, the writing operation for light emission of each pixel Px of the first column is ended.

In addition, during this period, the control unit 50 will start the pulse signal. SP1 is again input to the data drive 40. Thereby, the shift register circuit 41 inputs the shift signal to the data register circuit 42, and the display unit Din of the second column is taken in from the control unit 50.

At timing td3, the control section 50 applies the non-selection voltage VgL. In the scanning line Ls of the first column, each of the sampling transistors Tr1 of the first column and the switching transistors Tr2 of the first column are brought into a non-conduction state. Moreover, the control unit 50 applies the driving voltage ELVDD to the power supply line La of the first column. As a result, each of the driving transistors Tr3 of the first column supplies the drain current of the difference between the writing voltage held by the holding capacitor Cs of the first column and the threshold voltage Vth of the driving transistor Tr3 to which it is connected. To the corresponding EL element 11. Thereby, the control unit 50 starts the light-emitting operation for each pixel Px of the first column.

Further, during this period, the control section 50 will select the voltage VgH The scanning line Ls applied to the second column is applied to the power supply line La of the second column, and the sampling transistors Tr1 of the second column and the switching transistors Tr2 of the second column are turned on. . Further, the control unit 50 further inputs the latch pulse signal LP to the data driver 40, and causes each of the material latches 43a to hold the display data Din of the second column. The display data Din of the second column held by each of the data latches 43a is converted into an analog voltage by the display DAC 44a via the level shifter 46a, and is input to the data line Ld as the light-emission voltage VD. Then, the gate-source voltage Vgs of each of the driving transistors Tr3 in the second column is a value corresponding to the difference between the address voltage WDVSS and the light-emission voltage VD, and is used as the write voltage by the respective holding capacitors of the second column. Cs is maintained. Thereby, the control unit 50 ends the writing operation to each of the pixels Px in the second column.

In the future, the columns of the pixel Px are included in this order. In the light-emitting step of the writing operation and the light-emitting operation for light-emitting, the light-emitting step is repeated sequentially from the first column to the n-th column in the display clock cycle. Thereby, the control unit 50 displays the image represented by the gray scale in a sub-frame.

Next, the operation of the EL display device during the non-lighting period will be described.

As shown in FIG. 10, at timing ta1, the control unit 50 inputs the start pulse signal SP1 to the data driver 40. Thereby, the shift register circuit 41 inputs the shift signal to the data register circuit 42, and the data register circuit 42 takes in the display data Din of the first column. Then, the control unit 50 inputs the start pulse signal SP2 to the selection driver 20 and the power source driver 30.

At the timing ta2, the control unit 50 applies the selection voltage VgH to the scanning line Ls of the first column, and turns the sampling transistors Tr1 of the first column and the switching transistors Tr2 of the first column into an ON state. Moreover, the control unit 50 inputs the latch pulse signal LP to the data driver 40, whereby the material latch 43a holds the display material Din of the first column. The display data Din held by the data latch 43a is converted into an analog voltage by the display DAC 44a via the level shifter 46a, and is applied to the data line Ld as the non-light-emitting voltage VDN.

At this time, the control unit 50 applies the write voltage WDVSS to the power line La of the first column. The gate-source voltage Vgs of each of the driving transistors Tr3 in the first column is a value corresponding to the difference between the write voltage WDVSS and the non-light-emitting voltage VDN, and is held as a write voltage by the holding capacitor Cs. Thereby, the control unit 50 holds the storage capacitor Cs for the gate-source of the inverted voltage corresponding to the previously applied light-emitting voltage VD for each pixel Px of the first column. The inter-electrode voltage Vgs is such that each of the driving transistors Tr3 of the first column is driven in a saturated region, and the writing operation for the non-light-emitting of each pixel Px in the first column is ended.

In addition, during this period, the control unit 50 will start the pulse signal. SP1 is again input to the data drive 40. Thereby, the shift register circuit 41 inputs the shift signal to the data register circuit 42, and the data register circuit 42 takes in the display data Din of the second column.

At timing ta3, the control section 50 applies the non-selection voltage VgL. In the scanning line Ls of the first column, each of the sampling transistors Tr1 of the first column and the switching transistors Tr2 of the first column are brought into a non-conduction state. Moreover, the control unit 50 continuously applies the write voltage WDVSS to the power supply line La of the first column. Thereby, the control unit 50 continuously applies the write voltage held by the storage capacitor Cs of the first column, that is, the gate-source voltage Vgs corresponding to the reverse voltage of the previous light-emitting voltage VD to the first column. Each of the driving transistors Tr3.

Further, during this period, the control section 50 will select the voltage VgH The scanning line Ls applied to the second column is applied to the power supply line La of the second column, and the sampling transistors Tr1 of the second column and the switching transistors Tr2 of the second column are turned on. . Further, the control unit 50 further inputs the latch pulse signal LP to the data driver 40, and causes each of the material latches 43a to hold the display data Din of the second column. The display data Din of the second column held by each of the data latches 43a is converted into an analog voltage by the display DAC 44a via the level shifter 46a, and then output to the data line Ld as the non-light-emitting voltage VDN of each row. Then, the control unit 50 sets the gate-source voltage Vgs of each of the driving transistors Tr3 in the second column to a value corresponding to the difference between the write voltage WDVSS and the non-light-emitting voltage VDN, and serves as a write voltage. The holding capacitors Cs of the second column are held. Thereby, the control unit 50 ends the writing operation for the non-light-emitting of each of the pixels Px of the second column.

In the future, the columns of the pixel Px are included in this order. In the non-light-emitting step of the non-lighting write operation and the non-light-emitting operation, the non-light-emitting period is repeated sequentially from the first column to the nth column in the display clock cycle. Thereby, the image represented by black is displayed in a sub-frame.

According to the first embodiment, the advantages listed below can be obtained.

(1) In each of the plurality of driving transistors Tr3, the higher the gate-source voltage Vgs is when the EL element 11 emits light, the lower the EL element 11 does not emit light. Therefore, the displacement of the threshold voltage of the drive transistor Tr3 is suppressed to vary depending on each pixel Px.

(2) The higher the illuminating voltage VD is, the lower the illuminating voltage VDN is in each of the frames formed by the illuminating period and the non-illuminating period. Therefore, the displacement of the threshold voltage of each of the frames suppressing the driving transistor Tr3 in the shortest period of time during display is different depending on each pixel Px. As a result, in the plurality of pixels Px, the threshold voltage Vth of the driving transistor Tr3 can be made uniform in the shortest period of repetition in display.

(3) The inverted voltage which is symmetrical with the light-emission voltage VD is used as the non-light-emitting voltage VDN. Therefore, the voltage applied between the gate and the source of the driving transistor Tr3 is uniform in the plurality of pixels Px via the one-time light-emitting period and the one-time non-light-emitting period. Therefore, the effect of suppressing the displacement of the threshold voltage of the driving transistor Tr3 differs depending on each pixel Px.

(4) The write voltage for light emission is set by applying the light-emission voltage VD via the sampling transistor Tr1 to the source of the drive transistor Tr3. set. Further, the write voltage for non-light-emitting is also set by applying the non-light-emitting voltage VDN via the sampling transistor Tr1 to the source of the drive transistor Tr3. Further, the setting of the light-emission voltage VD and the setting of the non-light-emitting voltage VDN are realized by the driving of the sampling transistor. Therefore, it is possible to achieve a commonality between the configuration required for the writing operation for light emission and the configuration required for the writing operation for non-lighting.

(5) Conduction and switching transistor Tr2 of sampling transistor Tr1 The conduction is synchronized, and the non-conduction of the sampling transistor Tr1 is synchronized with the non-conduction of the switching transistor Tr2. Therefore, in the writing operation, the light-emitting operation, the writing operation for non-light-emitting, and the non-light-emitting operation for each of the light-emitting, the voltage, the source, and the drain of the driving transistor Tr3 are smoothly changed.

[Second Embodiment]

A second embodiment in which the EL display device and the EL display device driving method of the present disclosure are embodied will be described with reference to FIGS. 11 to 15. In the EL display device and the EL display device driving method of the second embodiment, the control unit 50 is provided with the relationship between the corresponding light-emission voltage VD and the non-light-emitting voltage VDN, and the EL display device and the EL display device of the first embodiment. The driving methods are different. Therefore, the relationship between the illuminating voltage VD and the non-emission voltage VDN will be described in detail below, and the same components as those described in the first embodiment will be denoted by the same reference numerals, and detailed description thereof will be omitted.

First, as one of the characteristics of the EL element 11, the relationship between the forward voltage applied to the EL element 11 and the drive current flowing to the EL element 11 will be described. Also, in Figure 11. Illumination with EL element 11 The current flowing through the operation is the driving current of the EL element 11 applied to the driving voltage of the EL element 11 in the direction in which the driving current flows to the EL element 11.

As shown in Fig. 11, the driving voltage of the EL element 11 is turned on. When the initial light-emission voltage Vels is equal to or lower than the initial light-emission voltage Vels, the drive current of the EL element 11 hardly flows. Moreover, even if the driving current of the EL element 11 flows, the magnitude of the driving current is less than the extent to which the EL element 11 emits light. As a result, when the forward voltage of the EL element 11 starts to be lower than the emission voltage Vels, the EL element 11 does not emit light.

In contrast, the forward voltage of the EL element 11 exceeds the start of transmission. At the time of the photovoltage Vels, the higher the forward voltage, the larger the driving current of the EL element 11. Further, when the forward voltage of the EL element 11 exceeds the initial emission voltage Vels, the magnitude of the driving current of the EL element 11 is such that the EL element 11 emits light, and the higher the forward voltage, the brightness of the light generated by the EL element 11. The higher the height.

In short, if the voltage applied to the EL element 11 is reversed When the voltage is applied, the EL element 11 does not emit light, and even if the voltage applied to the EL element 11 is forward voltage, the EL element 11 does not emit light in the forward voltage at which the emission voltage Vels is started. Further, when the forward voltage of the EL element 11 exceeds the initial emission voltage Vels, the EL element 11 emits light.

Secondly, based on the ground voltage, use the start to emit light. The voltage Vels indicates the correlation between the voltages applied to the scanning line Ls, the power source line La, and the data line Ld. In addition, in the example of the voltage applied to the scanning line Ls, the power source line La, and the data line Ld, the reference voltage ELVSS is set to the ground voltage, and the reference voltage ELVSS is shown in FIG. A configuration of a potential equal to the write voltage WDVSS.

As shown in Fig. 12, the write voltage WDVSS applied to the power supply line La is set to a potential equal to the reference voltage ELVSS applied to the ground voltage line Lb. The illuminating voltage VD applied to the data line Ld is a voltage which varies depending on each gray scale indicated by the gray scale data. In the range of the illuminating voltage VD, the value is set as the middle of the lowest gray scale value VDL closest to the level of the write voltage WDVSS and the highest gray scale value VDH which is the level at which the potential difference between the system and the write voltage WDVSS is the largest. The intermediate value is M. Further, in the range of the light-emission voltage VD, the switching value Vp is set as a value between the highest gray-scale value VDH and the intermediate value M.

The non-light-emitting voltage applied to the data line Ld is composed of the first non-light-emitting voltage VDN1 and the second non-light-emitting voltage VDN2. The first non-light-emitting voltage VDN1 is a reverse voltage of a voltage between the lowest gray-scale value VDL and the switching value Vp among the light-emitting voltages VD. The second non-light-emitting voltage VDN2 is set to a higher value than the reference voltage ELVSS and the write voltage WDVSS.

The polarity of the first non-light-emitting voltage VDN1 based on the write voltage WDVSS is the same as the polarity of the light-emitting voltage VD based on the write voltage WDVSS. The polarity of the second non-light-emitting voltage VDN2 based on the write voltage WDVSS is different from the polarity of the light-emitting voltage VD based on the write voltage WDVSS, and these have opposite polarities. The polarity of the light-emission voltage VD based on the write voltage WDVSS is negative, and the polarity of the first non-light-emitting voltage VDN1 based on the write voltage WDVSS is also negative. On the other hand, the polarity of the second non-light-emitting voltage VDN2 based on the write voltage WDVSS is positive.

In addition, the first one is based on the write voltage WDVSS. The polarity of the photovoltage VDN1 is negative as the polarity of the non-selection voltage VgL based on the write voltage WDVSS. The polarity of the second non-light-emitting voltage VDN2 based on the write voltage WDVSS is positive as the polarity of the selection voltage VgH based on the write voltage WDVSS. Further, the second non-light-emitting voltage VDN2 is lower than the level of the driving voltage ELVDD and the level of the selection voltage VgH, and the polarity of the driving voltage ELVDD based on the second non-light-emitting voltage VDN2 is the second non-light-emitting voltage VDN2. The polarity of the write voltage WDVSS for the reference is different.

Further, the light-emitting voltage VD based on the write voltage WDVSS The polarity is negative as the polarity of the non-selection voltage VgL based on the write voltage WDVSS. The level of the light-emission voltage VD is set between the non-selection voltage VgL and the write voltage WDVSS.

Incidentally, the reference voltage ELVSS can also be compared to the ground voltage. Higher levels can also be lower than the ground voltage. Further, the write voltage WDVSS may be lower than the reference voltage ELVSS.

Referring to Fig. 13, the illuminating voltage VD and the first non-lighting are explained. The relationship between the voltage VDN1 and the relationship between the illuminating voltage VD and the second non-emissive voltage VDN2. Fig. 13 is a view showing the relationship between the corresponding light-emission voltage VD and the first non-light-emitting voltage VDN1 given by the video signal processing unit 54, and the relationship between the corresponding light-emitting voltage VD and the second non-light-emitting voltage VDN2 given by the video signal processing unit 54. Graph.

As shown in Fig. 13, the first non-light-emitting voltage VDN1 is equivalent to A non-emissive voltage when the illuminating voltage VD is the same as or lower than the switching value Vp. That is, the first non-light-emitting voltage VDN1 is equal to or greater than the switching value Vp. The value of the light-emission voltage VD below the low gray-scale value VDL is given a correspondence. For example, when the illuminating voltage VD is 0 V of the lowest gray scale value VDL, -9.2 V is given as the first non-light-emitting voltage VDN1, and the first non-light-emitting voltage is used when the illuminating voltage VD is -5 V of the intermediate value M. VDN1, -4.2V are assigned corresponding. When the illuminating voltage VD is -9.2 V of the switching value Vp, 0 V is given as the first non-light-emitting voltage VDN1. Further, the range in which the light-emission voltage VD is set is appropriately set in accordance with the reference voltage, the write voltage WDVSS, the drive voltage ELVDD, and the driving of the EL element 11, and may be other than 0V to -10V.

Moreover, the control unit 50 is configured to face each pixel in one frame. Px is configured to generate a display data Din for generating the light-emission voltage VD when the light-emitting voltage VD of the value Vp or more and the lowest gray-scale value VDL or less is required to be switched. In addition, when the control unit 50 needs to switch the light-emitting voltage VD equal to or higher than the minimum value of the gray level VDL to the pixel Px of one frame, the control unit 50 generates the inverted voltage for generating the light-emitting voltage VD. 1 is formed by the method of displaying the data Din without the light-emitting voltage VDN1.

The second non-emissive voltage VDN2 is equivalent to the illuminating voltage VD A non-light-emitting voltage when the switching value Vp is higher. In other words, the second non-light-emitting voltage VDN2 is assigned to the value of the light-emission voltage VD that is equal to or higher than the highest gray-scale value VDH and less than the switching value Vp. For example, when the light-emitting voltage VD is -10 V of the highest gray-scale value VDH, 3V is given as the second non-light-emitting voltage VDN2, and when the light-emitting voltage VD is closest to the value of the switching value Vp, this is also the second The illuminating voltages VDN2, 3V are given a correspondence.

Further, the control unit 50 is configured to emit light of the highest grayscale value VDH or more and less than the switching value Vp for each pixel Px in one frame. When VD is pressed, a display data Din for generating the light-emission voltage VD is generated. Further, the control unit 50 generates a second non-lighting for generating a fixed value of 3 V when the illuminating voltage VD of the highest grayscale value VDH or more and less than the switching value Vp is required for each pixel Px in one frame. The voltage VDN2 is formed by the method of displaying the data Din.

For example, the video signal processing unit 54 of the control unit 50 is provided with A difference circuit for generating a difference value between the display data Din (light-emitting gradation data) of the illuminating voltage VD and the highest-order threshold value of the display data Din. Further, the video signal processing unit 54 of the control unit 50 includes a comparison circuit that compares the display data Din for generating the illuminating voltage VD with the switching gradation value corresponding to the grayscale value of the switching value Vp. Further, the video signal processing unit 54 of the control unit 50 compares the display data Din with the switching grayscale value every time the display data Din for generating the light-emission voltage VD is generated. When the display data Din is equal to or lower than the switching grayscale value, the video signal processing unit 54 of the control unit 50 applies the display data Din to the differential circuit, and generates the first one as in the first embodiment. The display data Din of the non-light-emitting voltage VDN1 (gray-level data for non-lighting). On the other hand, when the display data Din is higher than the switching grayscale value, the video signal processing unit 54 of the control unit 50 generates the display data Din (the grayscale data for no light emission) for generating the second non-light-emitting voltage VDN2.

This second non-emissive voltage VDN2 is the starting illuminating voltage The level below the Vels is set as shown below in accordance with the form in which the EL element 11 is driven by the drive circuit PCC during the non-lighting period and the above-described starting light emission voltage Vels.

As shown in Figure 14, a write voltage is applied to the power line La. When the selection voltage VgH is applied to the WDVSS and the scanning line Ls, the sampling transistor Tr1 and the switching transistor Tr2 are turned on. When the sampling transistor Tr1 and the switching transistor Tr2 are in an on state, the driving transistor Tr3 is driven in the saturation region. In this state, when the second non-light-emitting voltage VDN2 is applied to the data line Ld, the write voltage corresponding to the potential difference between the voltage of the power supply line La and the voltage of the data line Ld is used as the gate-source voltage Vgs of the driving transistor Tr3. It is held by the holding capacitor Cs.

At this time, because the second non-lighting voltage VDN2 is better than writing The voltage WDVSS is higher, so current does not flow to the driving transistor Tr3. On the other hand, since the second non-light-emitting voltage VDN2 is higher than the reference voltage ELVSS, the forward voltage of the EL element 11 is applied to the EL element 11.

Here, the second non-light-emitting voltage VDN2 is used for non-lighting. At the time of the write operation, the potential difference equal to or lower than the start of the light-emission voltage Vels is set between the source of the drive transistor Tr3 and the reference voltage ELVSS at the time of the write operation. When the potential difference between the source of the drive transistor Tr3 and the reference voltage ELVSS at the time of the write operation is equal to or lower than the start of the light-emission voltage Vels, the EL element 11 is applied even if the voltage applied to the EL element 11 is the forward voltage. Does not shine.

As shown in Fig. 15, when the write voltage for non-light-emitting is held by the holding capacitor Cs, when the non-selection voltage VgL is applied to the scanning line Ls, the sampling transistor Tr1 and the switching transistor Tr2 are in a non-conduction state. In this state, when the write voltage WDVSS is continuously applied to the power supply line La, the current does not flow to the drive transistor Tr3 as in the above-described write operation. On the other hand, since the source of the driving transistor Tr3 after the writing operation is far away It is higher than the higher level of the reference voltage ELVSS, so the forward voltage is continuously applied to the EL element 11. Further, a current of a degree that the EL element 11 does not emit light flows in the EL element 11, and the holding capacitor Cs is discharged.

[The role of EL display device]

Next, the operation of the EL display device during the non-lighting period will be described.

The control unit 50 first applies the selection voltage VgH to the scanning line Ls of the first column, and turns the sampling transistors Tr1 of the first column and the switching transistors Tr2 of the first column into an on state, and applies a non-light-emitting voltage. On the data line Ld. At this time, the control unit 50 applies the write voltage WDVSS to the power line La of the first column. Then, the gate-source voltage Vgs of each of the driving transistors Tr3 in the first column is a value corresponding to the difference between the write voltage WDVSS and the non-light-emitting voltage VDN, and is held as a write voltage by the holding capacitor Cs.

At this time, when the light-emitting voltage VD of the one-pixel Px is equal to or higher than the switching value Vp and the lowest gray-scale value VDL, the control unit 50 causes the data driver 40 to emit light during the non-light-emitting period following the light-emitting period. The first non-emissive voltage VDN1 of the inversion voltage of the voltage VD. On the other hand, when the light-emitting voltage VD of the light-emitting period of one pixel Px is equal to or higher than the highest gray-scale value VDH and less than the switching value Vp, the control unit 50 causes the data driver 40 to be fixed during the non-light-emitting period following the light-emitting period. The second non-emissive voltage VDN2 of the value.

In this case, the control unit 50 maintains the storage capacitor Cs at a reverse voltage corresponding to the preceding light-emitting voltage VD when the light-emitting voltage VD is equal to or higher than the switching value Vp and the lowest grayscale value VDL. The gate-source voltage Vgs ends the writing operation for the non-light-emitting of each pixel Px of the first column. Moreover, for each pixel Px of the first column, in the light-emitting When the voltage VD is higher than the gray level value VDH and less than the switching value Vp, the control unit 50 maintains the gate capacitance of the second non-light-emitting voltage VDN2 regardless of the value of the previous light-emitting voltage VD. The voltage Vgs is interrupted, and the writing operation for the non-light-emitting of each pixel Px of the first column is ended.

In the future, the columns of pixels Px are included in this order. In the non-light-emitting step of the writing operation for the light emission and the non-light-emitting operation, the non-light-emitting step is repeated sequentially from the first column to the nth column in the display clock cycle. Thereby, the image represented by black is displayed in a sub-frame.

According to the second embodiment, the advantages listed below can be obtained.

(1) When the light-emission voltage VD is higher than the switching value Vp, the holding capacitor Cs holds the second non-light-emitting voltage VDN2 whose polarity is different from the light-emission voltage VD. Therefore, when the displacement of the threshold voltage Vth of the driving transistor Tr3 is excessively performed in the specific pixel Px, the displacement of the threshold voltage Vth is suppressed for the specific pixel Px. As a result, the range in which the effect of suppressing the displacement of the threshold voltage Vth of the drive transistor Tr3 differs depending on the pixel Px is expanded to the extent of the displacement of the threshold voltage Vth.

(2) The drive circuit PCC to which the second non-light-emitting voltage VDN2 is applied discharges the storage capacitor Cs via the EL element 11. Therefore, when the operation of the EL display device is switched to the light-emitting period from the non-light-emitting period, the potential difference held by the holding capacitor Cs is suppressed from rapidly changing.

[Third embodiment]

A third embodiment in which the EL display device and the EL display device driving method of the present disclosure are embodied will be described with reference to FIGS. 16 to 26. Further, an EL display device and a driving method of the EL display device according to the third embodiment The EL display device and the EL display device driving method according to the first embodiment, the EL display device and the EL display device of the second embodiment are driven, and further, the threshold voltage Vth of the driving transistor Tr3 is detected. Detection actions and detection steps. Therefore, the detection operation and the detection procedure will be described in detail below, and the same configurations as those described in the first embodiment are given, and the same configurations as those described in the second embodiment are denoted by the same reference numerals, and the description is omitted. Its detailed description.

[Configuration of Control Unit 50]

As shown in Fig. 16, the timing controller 52 generates a data displacement clock signal Clkd, a display displacement clock signal Clks, and a detection displacement clock signal Clkr. The timing controller 52 outputs the data displacement clock signal Clkd to the data driver 40, outputs the display displacement clock signal Clks to the selection driver 20 and the power source driver 30, and outputs the detection displacement clock signal Clkr to the selection driver 20 and the power source driver 30. .

The detection displacement clock signal Clkr is used for the detection operation, and determines the switching period of the candidate to be selected. The selection driver 20 selects one by one in accordance with the order of the scanning line Ls of the first column, the scanning line Ls of the second column, the scanning line Ls of the second column, and the scanning line Ls of the m-th column, in the order of the detection of the displacement pulse signal Clkr. The candidate for the voltage VgH is selected. The power driver 30 selects the power line one by one in the order of the power line La of the first column, the power line La of the second column, the power line La of the second column, and the power line La of the mth column, each time the power pulse line Clkr of the detection is increased. La. The clock cycle for detecting the clock period of the displacement clock signal Clkr for detection is much shorter than the display period. For example, the clock period for detection is preferably the same as the clock period of the data shift clock signal Clkd.

Moreover, during illumination, the driver 20 is selected for display. The candidate for the clock cycle scan selection target, during the non-lighting period, the selection driver 20 also scans the candidates for the selection target in the display clock cycle. On the other hand, in the detection operation, the selection driver 20 scans the candidate for the selection target by the clock cycle. Further, during the light-emitting period, the power source driver 30 scans the candidate for the supply target in the display clock cycle, and scans the candidate for the supply target in the display clock cycle during the non-light-emitting period. On the other hand, in the detection operation, the power source driver 30 scans the candidates of the supply target in the detection clock cycle.

The detection of the displacement clock signal Clkr is used according to the detection time. The pulse period repeats the high level and low level, including the displacement waiting portion that maintains the low level only during the detection period. The timing sequence at which the displacement waiting portion is output is the opportunity to output the displacement pulse signal Clkr whenever the detection is performed, that is, every time the detection operation is performed.

For example, in this detection action, the displacement time is detected. The signal Clkr repeats the high level and the low level q times (1≦q≦m) according to the clock cycle, and then continues the displacement waiting portion. On the other hand, in the next detection operation, the detection displacement clock signal Clkr repeats the high level and the low level q+1 times (1≦q≦m), and then continues the displacement waiting portion. As a result, in this detection operation, the first scanning line Ls to the qth scanning line Ls are sequentially selected as candidates for selection, and are sequentially switched in accordance with the detection clock cycle. Then, after the detection period has elapsed, the q+1th scanning line Ls to the mth scanning line Ls are candidates for selection, and the detection clock cycle is sequentially switched. Further, in the next detection operation, the first scanning line Ls to the q+1th scanning line Ls are candidates for selection. The detection clock cycle is sequentially switched. Then, after the detection period has elapsed, the q+2th scanning line Ls to the mth scanning line Ls are candidates for selection, and the detection clock cycles are sequentially switched.

The timing controller 52 generates a start pulse signal SP1 and an artery The punch signal SP2, the latch pulse signal LP, and the mask pulse signal MP. The timing controller 52 inputs the start pulse signal SP1 and the latch pulse signal LP to the data driver 40. The timing controller 52 inputs the start pulse signal SP2 and the mask pulse signal MP to the selection driver 20, the power source driver 30, and the video signal processing unit 54.

The start pulse signal SP2 controls where the drive 20 is selected The timing control signal is used to switch the displacement clock signal used for switching the candidate of the selection target to the display clock period and the detection clock period. The start pulse signal SP2 is a control signal for controlling the processing timing of the power source driver 30, and switches the displacement clock signal used for switching the candidate to be supplied to the display clock cycle and the detection clock cycle. The timing controller 52 switches the displacement clock signal used for the switching of the candidate to be selected from the display clock cycle to the detection clock cycle every time the input start pulse signal SP2 is set only for the number of times. The timing controller 52 switches the displacement clock signal used for the switching of the candidate to be supplied from the display clock cycle to the detection clock cycle every time the input start pulse signal SP2 is set only for the number of times.

Further, in the third embodiment, the number of settings is set to 3 The timing controller 52 changes the displacement clock signal from the display clock period to the detection clock period every time the start pulse signal SP2 is input three times. Moreover, for example, according to the input of the 3nth start pulse signal SP2 The m scanning lines Ls are candidates for selection, and the display operation and the light-emitting operation for light-emitting are performed after the display clock cycles are sequentially switched. Then, based on the input of the 3n+1th start pulse signal SP2, the m scanning lines Ls are candidates for selection, and after the display clock cycles are sequentially switched, the writing operation and the non-lighting operation for non-lighting are performed. . Then, based on the input of the 3n+2th start pulse signal SP2, the m scanning lines Ls are candidates for selection, and the detection operation is performed after the detection clock cycles are sequentially switched.

The masking pulse signal MP is used to control the selection of the driver 20 The timing control signal controls the output of the displacement signal generated by the selection driver 20. When the mask pulse signal MP is at the high level, the driver 20 is selected, and the selection voltage VgH is applied to any one of the scanning lines Ls based on the displacement signal generated by the selection driver 20. On the other hand, when the mask pulse signal MP is at the low level, the driver 20 is selected, and the non-selection voltage VgL is applied to all of the scanning lines Ls regardless of the displacement signal generated by the selection driver 20.

The masking pulse signal MP is usually set to a high level, each When the output start pulse signal SP2 is set only for a number of times, it is switched from a high level to a low level, and includes a mask release portion that maintains a high level only during detection. The output timing of the mask release portion is synchronized with the output of the displacement waiting portion, and is displaced every time the detection operation is performed.

For example, in this detection action, the displacement is detected. The clock signal Clkr repeats the high level and the low level q times (1≦q≦m), and then outputs the mask release portion. On the other hand, in the next detection action, the displacement clock signal Clkr is detected, and the high level and the low level q+1 are repeated. Times (1≦q≦m), then, the mask release section is output. In this detection operation, first, the first scanning line Ls to the qth scanning line Ls are selected as candidates for selection, and the detection clock cycles are sequentially switched. Moreover, during this period, the selection voltage VgH is prohibited from being applied to the scanning line Ls. Next, during the detection period of the switching stop of the selection target candidate, the selection voltage VgH is applied to the scanning line Ls of the qth column which is the candidate at that time. On the other hand, in the next detection operation, first, from the first scanning line Ls to the q+1th scanning line Ls, as candidates for selection, the detection clock cycles are sequentially switched. Moreover, during this period, the selection voltage VgH is prohibited from being applied to the scanning line Ls. Next, during the detection period of the switching stop of the selection target candidate, the selection voltage VgH is applied to the scanning line Ls of the q+1th column which is the candidate at that time.

The memory unit 53 is provided with each of a plurality of pixels Px The memory area corresponding to m columns x n rows. The memory unit 53 takes in the detection data Dout from the data driver 40. The detection data Dout is information on the threshold voltage Vth of each pixel Px, and is, for example, 8-bit data. The memory unit 53 stores the detection data Dout of each pixel Px in a memory area to which the corresponding pixel Px is assigned. The memory unit 53 stores the current data in a memory area to which the pixel Px is assigned, and updates the detection data Dout.

The video signal processing unit 54 reads the detection data Dout of each pixel Px stored in the storage unit 53. The video signal processing unit 54 performs addition and subtraction of the detection data Dout for each pixel Px for the light-emitting gray scale data of each pixel Px, and outputs it as display data Din for each pixel Px. The video signal processing unit 54 generates the grayscale data for non-light emission of each pixel Px by using the display data Din subjected to addition and subtraction.

[Structure of Selecting Driver 20]

The configuration of the selection driver 20 will be described with reference to Fig. 16. Further, the configuration of the candidate for selection of the power source driver 30 is the same as the configuration of the candidate for selection and selection of the selection driver 20. Therefore, the configuration of the selection driver 20 will be described in detail below, and the description of the configuration of the power source driver 30 will be omitted.

As shown in Fig. 16, the control unit 50 inputs the detection displacement clock signal Clkr to the shift register circuit 21. The shift register circuit 21 sequentially shifts one of the selection target bits of the displacement signal from the first column to the mth column column by column every time the detection displacement pulse signal Clkr is input.

The control unit 50 inputs the mask pulse signal MP to the shift register circuit 21. When the mask pulse signal MP is at a high level, the shift register circuit 21 outputs a shift signal. On the other hand, when the mask pulse signal MP is at a low level, the shift register circuit 21 outputs a shift signal which does not include the selection target bit. On the other hand, when the displacement clock signal is used to display the displacement clock signal Clks, the shift register circuit 21 outputs a displacement signal including the selected target bit based on the mask pulse signal MP being at a high level. On the other hand, when the displacement clock signal is used to detect the displacement clock signal Clkr, the shift register circuit 21 is outside the detection period, and according to the mask pulse signal MP, the position is low, and the displacement without the selection target bit is output. signal.

The control of the output of the displacement signal is performed by, for example, connecting m AND circuits corresponding to the bits of the displacement signal to the input terminal of the shift register circuit 21, and then each of the m AND circuits The input of the masking pulse signal MP is implemented.

[Configuration of Data Driver 40]

The configuration of the data drive 40 will be described with reference to Fig. 17.

As shown in Fig. 17, the data latch circuit 43 is provided with n data latches 43a, n input switches SW1 connected to the input terminals of each of the n data latches 43a, and n data locks. The n output switches SW2 are connected to the output of each of the registers 43a. Further, the data latch circuit 43 includes a transfer switch SWtrs connected to the output switch SW2 of the first row and the control unit 50.

The input switch SW1 is driven by a control signal from the control unit 50, and the input terminal of the data latch 43a of the p-th row is associated with the register of the p-th row of the data register circuit 42 and the p-th row. The detection ADC 44b and the output terminal of the data latch 43a of the p+1th row are connected.

When the input terminal of the data latch 43a is connected to the data register circuit 42, the material latch 43a holds the display data Din memorized by the data register circuit 42 at the timing synchronized with the latch pulse signal LP.

When the input terminal of the data latch 43a is connected to the detection ADC 44b, the material latch 43a holds the data output from the detection ADC 44b as the detection data Dout at the timing synchronized with the latch pulse signal LP.

When the input terminal of the data latch 43a of the pth row is connected to the output terminal of the data latch 43a of the p+1th row, the data latch 43a of the pth row is synchronized with the latch pulse signal LP. Timing, the detection data Dout held by the data latch 43a of the p+1th row is held. In addition, the data latch 43a of the nth row of the last row is connected to the logic power source 60, and The data latch 43a of the nth row applies the logic reference voltage LVSS.

The output switch SW2 is based on a control letter from the control unit 50. The signal is driven, and the input terminal of the data latch 43a of the p+1th row is connected to any one of the display DAC 44a of the voltage conversion circuit 44 and the input terminal of the data latch 43a of the p-th row.

At the input of the data latch 43a and the voltage conversion circuit When the display of 44 is connected by the DAC 44a, the display data Din held by the data latch 43a is input to the display DAC 44a at the timing synchronized with the latch pulse signal LP.

At the output of the data latch 43a of the p+1th row and the pth When the input terminal of the data latch 43a is connected, the detected data Dout held by the data latch 43a of the p+1th row is at the timing synchronized with the latch pulse signal LP, and is latched by the data of the pth row. The device 43a is held.

The transmission switch SWtrs is controlled according to the control unit 50 The signal is driven to switch the connection and disconnection of the data latch 43a of the first row from the control unit 50. When the data latch 43a of the first row is connected to the control unit 50, the detection data Dout held by the material latch 43a of the first row is output to the control unit 50.

The voltage conversion circuit 44 includes n display DACs 44a and systems The n detection ADCs 44b of the analog-to-digital conversion circuit. Each of the n detection ADCs 44b converts the analog voltage input from the buffer circuit 45 connected to the detection ADC 44b into, for example, 8-bit detection data Dout, and outputs the detection data Dout to the detection ADC 44b. The connected data latch 43a. The analog voltage input to the ADC44b for detection is linear in the digital data output. In the display with DAC44a The bit length of the digital data at the time of voltage conversion with the detection ADC 44b is set to be, for example, the same bit length of 8 bits.

The buffer circuit 45 includes a buffer 45a for each data line Ld, and each The buffer 45b of the data line Ld and the display switch SWd for switching the data line Ld to the buffer 45a and the data lines Ld for cutting. Further, the buffer circuit 45 includes a detection switch SWm for switching between the data line Ld and the buffer 45b and each of the data lines Ld, and a data line Ld for connecting and disconnecting the data line Ld and the analog power source 70. Detection voltage switch SWs.

The display switch SWd is controlled according to the control unit 50. The signal is driven to connect the buffer 45a and the data line Ld, and the light-emitting voltage VD and the non-light-emitting voltage VDN are applied from the buffer 45a to the data line Ld. The buffer 45b takes in the voltage of the data line Ld, amplifies the taken-in voltage to the driving level of the detecting ADC 44b, and outputs it to the detecting ADC 44b. The detection switch SWm is driven by a control signal from the control unit 50, and connects the buffer 45b and the data line Ld, and takes the voltage of the data line Ld into the buffer 45b. The detection voltage switch SWs controls the application of the detection voltage VM from the analog power source 70 to the data line Ld.

The input of each of the n data latches 43a is in the hair The optical period and the non-lighting period are connected to the corresponding register in the data register circuit 42. Each of the n data latches 43a holds gray scale data stored in the corresponding scratchpad and synchronizes the hold with the latch pulse signal LP. Each of the n data latches 43a outputs the display material Din held by the material latch 43a to the voltage conversion circuit 44. Thereby, the data latch circuit 43 maintains the capital every time the latch pulse signal LP is input. The material register circuit 42 takes in a display data Din of one of the columns, and outputs the display data Din of one of the held columns to the voltage conversion circuit 44.

The input of each of the n data latches 43a is inspected The measurement operation is connected to the detection ADC 44b corresponding to the display DAC/ADC 44. Each of the n data latches 43a holds the data output from the corresponding detection ADC 44b as the detection data Dout, and synchronizes the hold with the latch pulse signal LP.

Input of the data latch 43a of the pth row (1≦p≦n) It is connected to the output of the data latch 43a of the p+1th line in the detection operation. Each of the data latches 43a of the p-th row holds the data held by the data latch 43a of the p+1th row as the detection data Dout, and synchronizes the hold with the latch pulse signal LP.

The output of the data latch 43a of the first row is detected The control unit 50 is connected to the control unit 50, and outputs the detection data Dout held by the data latch 43a of the first row. Thereby, the data latch 43a of the first row sequentially holds all the data held by the data latch 43a of the p+1th row from the data latch 43a of the second row, and sequentially proceeds to the control section 50. Output the retained data.

[The role of EL display device]

The operation of the EL display device during the light-emitting period and the operation of the EL display device including the detection operation during the non-light-emitting period will be described with reference to FIGS. 18 to 25. First, the operation during the light emission period of the EL display device will be described.

[lighting period]

Referring to Fig. 18, the transition of the driving states of the selection driver 20, the power source driver 30, and the data driver 40 during the light emission period will be described. Glowing In the same manner as in the first embodiment and the second embodiment, the writing operation and the light-emitting operation for light emission are sequentially performed.

As shown in Fig. 18, during illumination, the control unit 50 will check The measurement switch SWm, the detection voltage switch SWs, and the transfer switch SWtrs are kept off. Moreover, the control unit 50 holds the output switch SW2 while the data latch 43a is connected to the display DAC 44a, and holds the input switch SW1 in a state where the material latch 43a is connected to the data register circuit 42. Further, the control unit 50 controls the input of the start pulse signal SP1, the input of the start pulse signal SP2, and the input of the latch pulse signal LP, as in the light-emitting period of the first embodiment.

That is, at the timing tk1, the control unit 50 sets the display switch SWd is switched on, and the shift register circuit 41, the data register circuit 42, the data latch 43a, the display DAC 44a, the buffer 45a, and the data line Ld are connected in series.

At timing tk2, the control unit 50 sets the start pulse signal SP1. The data driver 40 is input to the data register circuit 42 to take in the display data Din of the first column. Then, the control unit 50 inputs the start pulse signal SP2 to the selection driver 20 and the power source driver 30.

At timing tk3, the control unit 50 is for the scan line Ls of the first column. The selection voltage VgH is applied, and the write voltage WDVSS is applied to the power line La of the first column. At this time, the control unit 50 inputs the latch pulse signal LP to the data driver 40, and causes the material latch 43a to simultaneously hold the display data Din of the first column. The display data Din of the first column held by the data latch 43a is input to the data line Ld as the light-emission voltage VD which is the analog voltage. Thereby, the control unit 50 ends the writing for light emission of the pixel Px of the first column. Into the operation. At this time, the control unit 50 further inputs the start pulse signal SP1 to the data driver 40, and causes the data register circuit 42 to take in the display data Din of the second column.

Further, the control unit 50 will assign the pixel Px of the first column. The difference between the corresponding detection data Dout and the threshold voltage Vth serving as the reference is treated as a correction value. Further, the control unit 50 performs addition and subtraction of the correction value on the adjusted gray scale data for illumination, and uses the calculation result as the light emission voltage VD applied to each of the data lines Ld.

At timing tk4, the control unit 50 is directed to the scan line Ls of the first column. The non-selection voltage VgL is applied, and the driving voltage ELVDD is applied to the power line La of the first column. Then, each of the drive transistors Tr3 of the first column is caused by the difference between the write voltage held by the storage capacitor Cs of the first column and the threshold voltage Vth of the drive transistor Tr3 to which it is connected. The drain current is supplied to the corresponding EL element 11. At this time, in the light-emission voltage VD applied to each data line Ld, since the fluctuation amount of the threshold voltage Vth is corrected, the drain current supplied to the EL element 11 is also corrected by the fluctuation of the threshold voltage Vth. the amount. Thereby, the control unit 50 ends the light-emitting period for the pixel Px of the first column.

Further, at this time, the control unit 50 applies the selection voltage VgH to the scanning line Ls of the second column, and applies the writing voltage WDVSS to the power line La of the second column. Further, the control unit 50 further inputs the latch pulse signal LP to the data driver 40, and causes each of the material latches 43a to hold the display data Din of the second column. The display data Din of the second column held by the data latch 43a is input to the data line Ld as the light-emission voltage VD which is the analog voltage. Thereby, the control unit 50 ends the writing operation for the light emission of the pixel Px of the second column. Work. Thereafter, the writing operation and the light-emitting operation for light emission are sequentially performed for each column, and the light-emitting period is repeated from the first column to the nth column in accordance with the display clock cycle.

[No light period]

Referring to Figs. 19 to 22, the transition of the driving state of the selection driver 20, the power source driver 30, and the data driver 40 during the period in which the EL display device is not illuminated will be described. During the non-lighting period, the writing operation, the non-lighting operation, and the detecting operation for non-lighting are sequentially performed. In addition, FIG. 19 shows changes in the driving states of the selection driver 20, the power source driver 30, and the data driver 40 for the writing operation and the non-lighting operation for non-light-emitting, and FIG. 21 shows the selection driver 20 for detecting the operation, The change in the driving state of the power driver 30 and the data driver 40.

As shown in FIG. 19, while the writing operation and the non-lighting operation for non-lighting are performed, the control unit 50 keeps the detection switch SWm, the detection voltage switch SWs, and the transmission switch SWtrs off during the subsequent light emission period. Moreover, the control unit 50 holds the output switch SW2 while the data latch 43a is connected to the display DAC 44a, and holds the input switch SW1 in a state where the material latch 43a is connected to the data register circuit 42. Further, the control unit 50 keeps the display switch SWd open, and continues the shift register circuit 41, the data register circuit 42, the data latch 43a, the display DAC 44a, the buffer 45a, and the data line Ld. Pick up. Further, the control unit 50 inputs the start pulse signal SP1, the start pulse signal SP2, and the latch pulse signal LP in the same manner as the write operation and the non-light-emitting operation for non-light-emitting in the first embodiment.

That is, at the timing tj1, the control unit 50 will start the pulse signal. SP1 is input to the data driver 40, and causes the data register circuit 42 to take in the display data Din of the first column. Then, the control unit 50 inputs the start pulse signal SP2 to the selection driver 20 and the power source driver 30.

At the timing tj2, the control unit 50 is directed to the scanning line Ls of the first column. The selection voltage VgH is applied, and the write voltage WDVSS is applied to the power line La of the first column. At this time, the control unit 50 inputs the latch pulse signal LP to the data driver 40, and causes the material latch 43a to simultaneously hold the display data Din of the first column. The display data Din of the first column held by the data latch 43a is input to the data line Ld as the non-light-emitting voltage VDN which is the analog voltage. Thereby, the control unit 50 terminates the gate-source voltage Vgs which is kept lower as the pixel Px of the first column and the pixel Px having the higher front surface light-emitting voltage VD, and ends the pixel Px for the first column. A write operation that does not emit light. At this time, the control unit 50 further inputs the start pulse signal SP1 to the data driver 40, and causes the data register circuit 42 to take in the display data Din of the second column.

Further, the control unit 50 will assign the pixel Px of the first column. The difference between the corresponding detection data Dout and the threshold voltage Vth serving as the reference is treated as a correction value. Further, the control unit 50 applies the non-light-emitting voltage VDN to which the correction value has been added to each of the data lines Ld.

At timing tj3, the control unit 50 is for the scan line Ls of the first column. The non-selection voltage VgL is applied, and the write voltage WDVSS is continuously applied to the power supply line La of the first column. Thereby, the control unit 50 continues to apply the write voltage held by the storage capacitor Cs of the first column to the drive transistor Tr3 of the first column, that is, the gate which is lower as the pixel having the higher front emission voltage VD is lower - Source-to-source voltage Vgs. Thereby, the control unit 50 ends the pixel Px of the first column. No light operation.

Further, at this time, the control unit 50 is for the scan line of the second column. The selection voltage VgH is applied to Ls, and the write voltage WDVSS is applied to the power supply line La of the second column. Further, the control unit 50 further inputs the latch pulse signal LP to the data driver 40, and causes each of the material latches 43a to hold the display data Din of the second column. The display data Din of the second column held by the data latch 43a is input to the data line Ld as the non-light-emitting voltage VDN which is the analog voltage. Thereby, the control unit 50 ends the writing operation for the non-light-emitting of the pixel Px of the second column. Thereafter, the writing operation and the non-lighting operation for non-lighting are sequentially performed for each column, and the writing operation and the non-lighting operation for non-lighting are repeated from the first column to the nth column in accordance with the display clock cycle.

Next, the selection driver 20 and the electric power in the detection operation will be described. The transition of the drive state of the source driver 30 and the data driver 40. First, the dependence of the driving transistor Tr3 on the illuminating voltage VD of the drain current will be described with reference to Fig. 20. Further, in Fig. 20, the dependence of the two drive transistors Tr3 having the threshold voltages Vth of the drive transistor Tr3 different from each other is exemplified.

The curve L1 indicated by the solid line in Fig. 20 indicates the dependence of the driving transistor Tr3 on the illuminating voltage VD of the drain current Id, and indicates the threshold voltage Vth of the driving transistor Tr3 and the current amplification at the driving circuit PCC. The dependence of the rate β on the initial value. When the start value of the threshold voltage Vth is Vth ₀ , the drain current Id flowing in the drive circuit PCC in the initial state is expressed by the following mathematical expression (1). Further, V ₀ is a write voltage WDVSS.

Id=β(V ₀ -Vd-Vth ₀ ) ² (1)

The curve L2 indicated by a broken line in Fig. 20 indicates the dependence of the driving transistor Tr3 on the illuminating voltage VD of the drain current Id, and indicates that the drain current Id of the driving transistor Tr3 changes from the initial state with time. Time. When the threshold voltage Vth is Vth ₁ (= Vth0 + ΔVth), the drain current Id flowing in the drive circuit PCC in this state is expressed by the following mathematical expression (2).

Id=β(V ₀ -Vd-Vth ₁ ) ² (2)

As shown in Fig. 20 and the above mathematical expressions (1) and (2), the curve L2 indicates the shape of the curve L1 which is only shifted by the displacement amount ΔVth, and these curves L1 and before and after the fluctuation of the threshold voltage Vth The shape of the curve L2 is almost constant. This implies that the variation of the current amplification factor β is negligible compared to the variation of the threshold voltage Vth, and the drive transistor Tr3 is corrected by correcting the emission voltage VD by using the displacement amount ΔVth of the drive transistor Tr3. The drain current Id. In the EL display device of the second embodiment, the threshold voltage Vth of the drive transistor Tr3 is detected and the illuminating voltage VD applied to the drive circuit PCC is corrected.

Referring to Fig. 21, the transition of the driving state of the selection driver 20, the power driver 30, and the data driver 40 in the detection operation will be described. In the detection operation, the voltage holding operation, the voltage saturation operation, the voltage measurement operation, and the voltage output operation are sequentially performed. In addition, since the detection operation of the threshold voltage Vth is equal to each other in the columns in which the pixels Px are arranged, the case where the column to be detected is the qth column will be exemplified below.

As shown in the lower side of FIG. 21, during the detection operation of the pixel Px in the qth column, the control unit 50 continues to apply the power line La of the qth column. Add write voltage WDVSS. Moreover, the control unit 50 keeps the display switch SWd closed, and continuously disconnects the drive circuit PCC of the qth column from the shift register circuit 41 and the data register circuit 42. Further, the control unit 50 continuously connects the output switch SW2 to the adjacent material latch 43a.

At timing t1, the control unit 50 will input the switch SW1 and check The ADC44b is connected and the transfer switch SWtrs is kept off. In this state, the control unit 50 applies the selection voltage VgH to the scanning line Ls of the qth column, and sets the switching transistor Tr2 of the qth column and the sampling transistor Tr1 of the qth column to the on state, and sets the qth column. The driving transistor Tr3 is changed to a state of being driven in a saturation region. Moreover, the control unit 50 switches the detection voltage switch SWs to ON, and simultaneously applies the detection voltage VM to each of the data lines Ld from the analog power supply 70.

At this time, to be higher than the assumed threshold voltage Vth The voltage is applied as a gate-source voltage Vgs, and the detection voltage VM is preset. That is, in order to make the difference between the write voltage WDVSS and the detection voltage VM larger than the threshold voltage Vth assumed, the control unit 50 applies the detection voltage VM between the gate and the source of the drive transistor Tr3. Further, the potential of each of the data lines Ld to which the detection voltage VM is applied is lower than the write voltage WDVSS, and is lower than the cathode of the EL element 11.

When the detection voltage VM is applied to each data line Ld, the corresponding The current of each pixel Px between the detection voltage VM and the write voltage WDVSS flows to the analog power source 70 via the drive transistor Tr3 of the qth column and the sampling transistor Tr1 of the qth column. Accordingly, the gate-source voltage Vgs of the driving transistor Tr3 is maintained while the holding capacitance Cs of the qth column is maintained, whereby the voltage holding operation is completed. In addition, because the potential of the anode of the EL element 11 is The potential of the cathode of the EL element 11 is lower than that of the EL element 11, so that the EL element 11 does not emit light.

At timing t2, the control unit 50 is paired with the scan line Ls of the qth column. While the application of the selection voltage VgH is maintained, the detection voltage switch SWs is switched to off only while the detection switch SWm is turned off. Thereby, the portion of each of the data lines Ld that is closer to the data driver 40 than the portion to which the sampling transistor Tr1 is connected is switched to a high impedance state.

At this time, the holding capacitor Cs of the qth column is maintained by the qth column. Since the gate-source voltage Vgs of the transistor Tr3 is driven, in the driving transistor Tr3 of the qth column, the potential of the source of the driving transistor Tr3 of the qth column is close to the driving transistor Tr3 of the qth column. In the way of the potential of the bungee, the bungee current flows. Then, the relaxation time t from the time elapsed from the timing t2 advances, and the holding capacitance Cs of the qth column discharges the electric charge, and the voltage between the both ends of the holding capacitance Cs of the qth column, that is, the qth column The gate-source voltage Vgs of the driving transistor Tr3 is lowered to a threshold voltage Vth at which the drain current becomes non-flowing.

As a result, the holding capacitor Cs of the qth column remains equal to the qth The voltage of the threshold voltage Vth of the driving transistor Tr3 is listed, and the voltage saturation operation ends. Further, the control unit 50 holds the detection switch SWm for applying the detection voltage VM to each of the data lines Ld to be turned off after the timing t2.

At timing t3, the control unit 50 is paired with the scan line Ls of the qth column. The application of the selection voltage VgH is maintained, and only the detection switch SWm is switched to be turned on. Thereby, the data line Ld is connected to the detection ADC 44b, and is high. The potential of the data line Ld of the impedance state is taken in the detection ADC 44b.

At this time, the holding capacitor Cs of the qth column remains equal to the qth The voltage of the threshold voltage Vth of the drive transistor Tr3 is listed. Therefore, the gate-source voltage Vgs of the drive transistor Tr3 in the qth column, that is, the drive power corresponding to the qth column, is detected from the potential difference between the potential taken in by the detection ADC 44b and the write voltage WDVSS. The voltage of the threshold voltage Vth of the crystal Tr3. The potential of the data line Ld taken in by the detection ADC 44b is converted into the detection data Dout of the coefficient bit data by the detection ADC 44b, and then output to the data latch 43a via the level shifter 46b. Then, the material latch 43a holds the detection data Dout, whereby the voltage measurement operation ends.

At timing t4, the control unit 50 is paired with the scan line Ls of the qth column. The non-selection voltage VgL is applied, and the switching transistor Tr2 of the qth column and the sampling transistor Tr1 of the qth column are switched to a non-conduction state. In this state, the control unit 50 switches the detection switch SWm to off, and switches the transmission switch SWtrs to ON. Further, the control unit 50 connects the input switch SW1 to the adjacent material latch 43a, and connects the respective material latches 43a in series.

At this time, the control unit 50 inputs the latch pulse signal LP. To the data driver 40, the detected data Dout held by each of the material latches 43a is sequentially transferred in synchronization with the timing of the latch pulse signal LP. Thereby, the control unit 50 sequentially transmits the data on the threshold voltage Vth of each of the drive transistors Tr3 of the qth column to the data driver 40. Further, in Fig. 21, in order to facilitate the explanation of the transition of the driving state, the number of repetitions of the latch pulse signal LP is indicated.

At timing t5, the control unit 50 is paired with the scan line Ls of the qth column. The application of the non-selection voltage VgL is maintained, and the transfer switch SWtrs is switched to off. Further, the control unit 50 connects the input terminal of the material latch 43a to the register of the data register circuit 42. Thereby, the voltage output operation is completed, and the detection operation of the drive transistor Tr3 of the qth column is completed.

Referring to Fig. 22, the transition of the data line potential VLd of the potential of the data line Ld during the period from the timing t2 to the timing t3 will be described.

As shown in Fig. 22, when the relaxation time t elapses from the time t2 elapses, the data line potential VLd is discharged from the detection voltage V with the charge of the storage capacitor Cs connected to the data line Ld. Near the write voltage WDVSS. Then, when the relaxation time t is advanced to the saturation time ts, the data line potential VLd is saturated at the saturation voltage VLds, and the drain current becomes non-flow. At this time, the difference between the write voltage WDVSS and the saturation voltage VLds is set as the threshold voltage Vth. Further, the saturation time ts is, for example, from 3 nsec to 10 nsec, and the period from the timing t2 to the timing t3 is set to be equal to or higher than the saturation time ts.

[Detection action timing]

Referring to Fig. 23 to Fig. 25, the timing of the detection operation included in the non-lighting period will be described. In the following, in order to facilitate the use of the number of columns and the number of frames arranged in the pixel Px, the timing of the detection operation will be described, and the configuration in which the pixel Px is located at 540 columns × 960 rows and the frame rate is 60 fps will be exemplified. Fig. 23 is a timing chart showing the detection operation of the first frame during the non-light-emitting period, Fig. 24 is a timing chart showing the detection operation of the second frame during the non-light-emitting period, and Fig. 25 is a view showing the 540th frame of the non-light-emitting period. The timing of the detection action during the period. Further, the number of columns arranged in the pixel Px may be the number of columns other than 540. In like When the number of columns in the arrangement of the prime Px is m columns, the timing of the detection operation of the mth frame corresponds to the content shown in FIG.

As shown in Fig. 23, at the timing Tf1a, the pixel in the first column The write operation for Px illumination begins. When the pixel for writing in the first column is completed, the light-emitting operation starts in the pixel Px in the first column, and the writing operation for light-emitting starts in the pixel Px in the second column. In this manner, from the pixel Px of the first column to the pixel Px of the 540th column, the writing operation for light emission is sequentially repeated in accordance with the clock cycle for display, and the light is sequentially emitted from the column in which the writing operation for light emission ends. operating.

At the timing Tf1b, the pixel Px of the 540th column is used for illumination. The write operation is started, and the write operation for the pixel Px in the first column is not illuminated. When the pixel operation Px in the first column is completed, the non-light-emitting operation starts in the pixel Px in the first column, and the non-light-emitting operation starts in the pixel Px in the second column. In this manner, from the pixel Px of the first column to the pixel Px of the 540th column, the writing operation for non-lighting is sequentially repeated in accordance with the clock cycle for display, and the column operation is completed from the end of the writing operation for non-lighting. Start not to illuminate.

At the timing Tf1c, the pixel Px at the 540th column is not illuminated. Then, from the pixel Px of the first column to the pixel Px of the 540th column, the candidates of the selection target are sequentially scanned in accordance with the clock cycle for detection. At this time, first, the pixel Px of the first column is set to the detection target to which the threshold voltage Vth is detected, and the detection operation of the pixel Px of the first column is performed. Then, the detection data Dout of the drive transistor Tr3 of the first column is stored in the memory unit 53.

When the pixel Px detection operation in the first column ends, from the second column The pixel Px to the pixel Px of the 540th column sequentially scan the candidates of the selection target in accordance with the clock cycle for detection. During this scanning, the non-selection voltage VgL is applied to all of the scanning lines Ls, and all of the pixels Px are kept in a state where the EL elements 11 are not illuminated.

In the timing Tf2a, to the pixel Px of the 540th column scan selection pair When the image is candidate, the writing operation for the light emission of the pixel Px of the first column is resumed.

As shown in Fig. 24, at the timing Tf2a, the writing operation for light-emitting of the pixel Px in the first column is started. When the pixel for writing in the first column is completed, the light-emitting operation starts in the pixel Px in the first column, and the writing operation for light-emitting starts in the pixel Px in the second column. In this manner, from the pixel Px of the first column to the pixel Px of the 540th column, the writing operation for light emission is sequentially repeated in accordance with the clock cycle for display, and the light is sequentially emitted from the column in which the writing operation for light emission ends. operating.

At the timing Tf2b, the pixel Px of the 540th column is used for illumination. The write operation is started, and the write operation for the pixel Px in the first column is not illuminated. When the pixel operation Px in the first column is completed, the non-light-emitting operation starts in the pixel Px in the first column, and the non-light-emitting operation starts in the pixel Px in the second column. In this manner, from the pixel Px of the first column to the pixel Px of the 540th column, the writing operation for non-lighting is sequentially repeated in accordance with the clock cycle for display, and the column operation is completed from the end of the writing operation for non-lighting. Start not to illuminate.

At the timing Tf2c, the pixel Px at the 540th column is not illuminated. Then, from the pixel Px of the first column to the pixel Px of the 540th column, the candidates of the selection target are sequentially scanned in accordance with the clock cycle for detection. currently First, the pixel Px of the second column is set to the detection target to which the threshold voltage Vth is detected, and the pixel Px of the second column is shifted in accordance with the displacement of the selection target bit of the detection clock cycle. Here, when the candidate pixel is selected as the pixel Px of the first column, the non-selection voltage VgL is applied to the scanning line Ls. Then, when the candidate pixel candidate selects the pixel Px of the second column, the pixel Px of the second column is detected.

Thereby, the detection of the driving transistor Tr3 of the second column The material Dout is memorized in the memory unit 53 of the control unit 50. Then, when the detection operation of the pixel Px in the second column is completed, the candidate for the selection target is sequentially scanned from the pixel Px of the third column to the pixel Px of the 540th column in accordance with the detection clock cycle. During this scanning, the non-selection voltage VgL is applied to all of the scanning lines Ls, and all of the pixels Px are kept in a state where the EL elements 11 are not illuminated.

At the timing Tf3a, when the pixel Px of the 540th column scans the candidate of the selection target, the writing operation for the light emission of the pixel Px of the first column is resumed.

As shown in Fig. 25, at the timing Tfma, the writing operation for light-emitting of the pixel Px in the first column is started. When the pixel for writing in the first column is completed, the light-emitting operation starts in the pixel Px in the first column, and the writing operation for light-emitting starts in the pixel Px in the second column. In this manner, from the pixel Px of the first column to the pixel Px of the 540th column, the writing operation for light emission is sequentially repeated in accordance with the clock cycle for display, and the light is sequentially emitted from the column in which the writing operation for light emission ends. operating.

At the timing Tfmb, the pixel Px in the 540th column performs a writing operation for light emission, and the pixel Px in the first column does not emit light for writing operation. Start. When the pixel operation Px in the first column is completed, the non-light-emitting operation starts in the pixel Px in the first column, and the non-light-emitting operation starts in the pixel Px in the second column. In this manner, from the pixel Px of the first column to the pixel Px of the 540th column, the writing operation for non-lighting is sequentially repeated in accordance with the clock cycle for display, and the column is terminated by the writing operation for non-lighting. The sequence starts without lighting operation.

At the timing Tfmc, the pixel Px in the 540th column is not sent. In the optical operation, the pixels of the first column Px to the pixels Px of the 540th column are sequentially scanned for the candidates of the selection target in accordance with the clock cycle for detection. At this time, first, the pixel Px of the 540th column is set to the detection target to which the threshold voltage Vth is detected, and the pixel Px of the 539th column is performed in accordance with the displacement of the selection target bit of the detection clock cycle. Here, when the candidate to be selected is from the pixel Px of the first column to the pixel Px of the 539th column, the non-selection voltage VgL is applied to the scanning line Ls. Then, when the pixel Px of the 540th column is selected as the candidate of the selection target, the detection operation is performed on the pixel Px of the 540th column. Thereby, the detection data Dout of the drive transistor Tr3 of the 540th column is stored in the memory unit 53 of the control unit 50. At the timing Tfmd, the detection operation of the pixel Px of the 540th column is completed, and the writing operation for the light emission is started again for the pixel Px of the first column.

In this way, each frame is displayed, to the 540th column. The pixel Px performs a non-light-emitting operation, and then performs a detection operation on the pixel Px of a specific column. The target value of the threshold voltage Vth is sequentially shifted from the pixel Px of the first column to the respective columns in the scanning direction. In other words, in the kth frame (k is an integer of 1 or more), when the pixel Px of the qth column (1≦q≦539) is detected, the q+1th column is in the k+1th frame. Pixel Px Perform the detection action. When the detection target advances to the pixel Px of the last column, the detection object returns to the pixel Px of the first column.

At this time, the test capital obtained when the object is detected in the qth column The material Dout is stored in the memory unit 53 of the control unit 50, and is stored in the corresponding memory region of the pixel Px stored in the qth column, and is updated. Then, when the display data Din is generated in the k+1th frame, the control unit 50 uses the latest detection data Dout as the detection data Dout of the qth column. Further, the control unit 50 reuses the detection data Dout used in the kth frame as the detection data Dout other than the qth column. Thereby, the test data Dout of each column is updated 540 times per repeated frame display.

Refer to Figure 26 for a detailed description of the period in which a frame is displayed. The change of the control signal between the two. Further, since the transition of the control signal during the display of one frame is the same for each detection target, the transition of the control signal when the pixel Px of the qth column of the detection target in the kth frame is exemplified will be described below.

The selection driver 20 is adapted to the start pulse signal SP2. The input generates a displacement signal in accordance with the clock period for display, and sequentially applies the selection voltage VgH to each of the scanning lines Ls according to the timing of the displacement signal. At this time, the selection driver 20 applies the selection voltage VgH in accordance with the display clock period from the scanning line Ls of the first column to the scanning line Ls of the 540th column.

The power driver 30 is adapted to the start pulse signal SP2 The input generates a displacement signal according to the clock cycle for display, and selects candidates for the supply target in sequence according to the timing of the displacement signal. At this time, the power source driver 30 sequentially selects the power source line La from the first column to the 540th column, and applies the write voltage WDVSS in accordance with the display clock cycle.

Then, in the q-th column (q is an integer from 1 to 540) When the selection voltage VgH is applied to the trace line Ls, and the write voltage WDVSS is applied to the power supply line La of the qth column, the light-emission voltage VD according to the display data Din is applied to the data line Ld. Moreover, the non-selection voltage VgL is sequentially applied to the scanning line Ls from the column to which the selection voltage VgH is applied, and the driving voltage ELVDD is sequentially applied to the power source line La from the column to which the writing voltage WDVSS is applied. Then, when the non-selection voltage VgL is applied to the scanning line Ls of the qth column, and the driving voltage ELVDD is applied to the power supply line La of the qth column, the drain current according to the display data Din is supplied to the EL element 11.

When the illumination operation proceeds to the pixel Px of the 540th column, the selection drive The actuator 20 starts scanning of the application of the selection voltage VgH in response to the input of the start pulse signal SP2. When the application of the driving voltage ELVDD is performed to the pixel Px of the 540th column, the power driver 30 starts the scanning of the application of the write voltage WDVSS in response to the input of the start pulse signal SP2.

Then, applying a selection voltage to the scan line Ls of the qth column VgH, and when the write voltage WDVSS is applied to the power supply line La of the qth column, the non-light-emitting voltage VDN according to the display data Din is applied to the data line Ld. Thereby, the gate-source voltage Vgs which is reversed in the driving transistor Tr3 is applied to the driving transistor Tr3.

When the non-lighting operation proceeds to the pixel Px of the 540th column, the start is started. The input of the pulse signal SP2 reaches the set number of times, and the displacement clock signal used for scanning the scanning line Ls is switched from the display clock cycle to the detection clock cycle. Then, the selection driver 20 shifts the candidate of the selection target according to the clock cycle for detection, and the power driver 30 follows the detection. Use the clock cycle to shift the candidate of the supply object. During this period, since the masking pulse signal MP is at a low level, the selection driver 20 does not apply the selection voltage VgH to the candidate of the selection target. Further, during this period, the power source driver 30 continuously applies the write voltage WDVSS to the candidate of the supply target.

Masking pulse letter when selecting the candidate displacement to the qth column The number MP is switched to the high level, and the selection driver 20 applies the selection voltage VgH to the scanning line Ls of the qth column. Then, the control unit 50 detects the threshold voltage Vth of the pixel Px of the qth column.

The control unit 50 acquires detection data for the pixel Px of the qth column. At Dout, the masking pulse signal MP is switched to a lower level. Then, the selection driver 20 shifts the candidate of the selection target to the 540th column in accordance with the detection clock cycle, and the power source driver 30 shifts the candidate of the supply target to the 540th column in accordance with the detection clock cycle. During this period, since the masking pulse signal MP is at a low level, the selection driver 20 does not apply the selection voltage VgH to the candidate of the selection target. Further, during this period, the power source driver 30 continuously applies the write voltage WDVSS to the candidate of the supply target.

Masking pulse when selecting the candidate displacement to the 540th column The signal MP is then switched to a high level. Then, from the scanning line Ls of the first column to the scanning line Ls of the 540th column, the writing operation and the light-emitting operation for light emission are started again.

According to the third embodiment, the advantages listed below can be obtained.

(1) The threshold voltage Vth of the driving transistor Tr3 is detected, and the display data Din is corrected based on the threshold voltage Vth. Therefore, the deterioration of the image quality caused by the fluctuation of the threshold voltage Vth is suppressed.

(2) because the detection is performed during the display of a frame Therefore, even when the fluctuation of the threshold voltage Vth becomes large in a short period of time, the deterioration of the displayed image quality is suppressed.

(3) The detection target of the threshold voltage Vth is one detection operation, and is one pixel Px to which one scanning line Ls is connected. Therefore, the time required for one detection operation is shorter than the configuration of all the pixels Px of the detection voltage Vth of the detection operation at one time. As a result, when the detection operation is incorporated in one non-light-emitting period, the deterioration of the image quality due to the lengthening of the non-light-emitting period is suppressed.

(4) Especially, because in order to make the display of motion pictures become Since the detection operation is performed during the non-lighting period in which the sharp insertion is performed, the influence of the detection operation on the display performance of the image is effectively suppressed.

(5) The switching of the candidate to be selected is performed in the detection operation in the same manner as the writing operation for lighting, the lighting operation, the writing operation for non-lighting, and the non-lighting operation. Therefore, the selection driver 20 also functions to change the configuration of the detection object every time one frame is displayed.

(6) In the detection operation, the switching period of the candidate of the detection object It is a detection clock cycle that is shorter than the clock cycle. Therefore, for example, the switching period of the candidate to be detected is shorter than the configuration of the display clock cycle, and the time required for the detection operation is shortened.

(7) Detection of threshold voltage Vth for each frame displayed The object is shifted column by column from the pixel Px of the first column in the scanning direction. Therefore, compared with the configuration in which the detection target voltage Vth is intermittently set in the scanning direction, the correction of the display data Din according to the threshold voltage Vth is extremely fine in the scanning direction.

[Modification]

The above embodiments can be implemented as described below.

[No illuminating voltage VDN]

The relationship between the corresponding light-emission voltage VD and the non-light-emitting voltage VDN given to the control unit 50 can be changed as follows.

As shown by the broken line LC1 of Fig. 27, the level of the non-light-emitting voltage VDN may be two levels different from each other. Further, when the light-emission voltage VD is equal to or higher than the switching value Vp, among the two levels different from each other, the non-light-emitting voltage VDN of the high level is given. That is, in the light-emitting voltage VD corresponding to the gray-scale value lower than the gray-scale value corresponding to the switching value Vp, for the light-emitting voltage VD, among the two levels different from each other, the high-level non-light-emitting voltage VDN is Give the correspondence. That is, in the two levels different from each other in the light-emitting voltage VD corresponding to the gray-scale value lower than the gray-scale value corresponding to the switching value Vp, the non-light-emitting voltage VDN which is larger than the potential difference of the write voltage WDVSS Is given a correspondence. Further, among the two levels different from the gradation voltage VD corresponding to the gray scale value corresponding to the gray scale value corresponding to the switching value Vp, the non-light-emitting voltage VDN close to the write voltage WDVSS is given. Even in the correspondence relationship between the illuminating voltage VD and the non-emission voltage VDN, the higher the illuminating voltage VD is, the lower the illuminating voltage VDN is in the vicinity of the switching value Vp.

At this time, as shown by the broken line LC2 of Fig. 27, among the two levels different from each other, the high-level non-light-emitting voltage VDN may be the same level as the second non-light-emitting voltage VDN2 of the second embodiment. That is, when the level of the non-light-emitting voltage VDN is two levels different from each other, at least one of the levels is a writing operation for non-lighting, or may be driving. The gate-source between the transistors Tr3 becomes a reverse level. Further, all of the levels of the non-light-emitting voltage VDN may be reversed between the gate and the source of the driving transistor Tr3 in the writing operation for non-light-emitting.

In addition, as shown in the dot line LC3 of Figure 27, no The level of the photovoltage VDN may be three levels that are different from each other, or four levels that are different from each other. In short, the correspondence relationship between the light-emitting voltage VD and the non-light-emitting voltage VDN may be a configuration in which the higher the light-emitting voltage VD is, the lower the non-light-emitting voltage VDN is.

As shown by the curve LC4 of Fig. 28, at the illuminating voltage VD For all ranges, the non-emissive voltage VDN may also vary continuously. In other words, in the range of the entire illuminating voltage VD, the higher the illuminating voltage VD is, the lower the non-illuminating voltage VDN is.

At this time, as shown by the dot chain line LC5 in Fig. 28, the pair is right. The non-light-emitting voltage VDN which is the same as the second non-light-emitting voltage VDN2 of the second embodiment may be assigned to the light-emitting voltage VD of the highest gray scale value.

In addition, as shown by the dotted line LC6 in Fig. 28, it is also possible to The change in the non-emission voltage VDN of the change in the emission voltage VD is different depending on the respective emission voltages VD. Further, it may include a change in the relative light-emission voltage VD or a change in the non-light-emitting voltage VDN. Further, as indicated by the solid line LC7, the non-light-emitting voltage VDN (for example, -5 V) when the light-emitting voltage VD is low may be such that the light-emitting voltage VD and the non-light-emitting voltage are higher than the minimum value of the light-emitting voltage VD (for example, -10 V). The VDN is assigned a correspondence. In short, as a correspondence between the illuminating voltage VD and the non-emissive voltage VDN The configuration may be such that the higher the illuminating voltage VD is, the lower the illuminating voltage VDN is.

‧Can also emit light voltage VD and be assigned to the light-emitting voltage VD The corresponding non-light-emitting voltage VDN is applied to the data line Ld in a frame different from each other. In short, the state in which the lower the illuminating voltage VD is, the lower the illuminating voltage VDN is, the most important. When the illuminating voltage VD is high, the frame to which the non-light-emitting voltage VDN is applied to the data line Ld may be a frame before a predetermined number of times, or may be a frame of a predetermined number of times.

For example, the control unit 50 memorizes the illumination period of the plurality of copies. The average value of the gray scale data is used for the illumination, and the average value of the gray scale data for illumination is updated according to the plurality of illumination periods. Then, the control unit 50 uses the latest value of the average value of the gray scale data for light emission during the plurality of light emission periods, and generates the same gray scale data for non-light emission during the subsequent non-light emission period. That is, the non-light-emitting voltage VDN is the same value used for a plurality of non-light-emitting periods, and may be updated during a plurality of non-light-emitting periods. Even in such a configuration, the state in which the illuminating voltage VD is lower when the illuminating voltage VD is higher is included.

[Drive Circuit PCC]

‧ As shown in Fig. 29, the three transistors Tr1 to Tr3 included in the drive circuit PCC are not limited to n-type transistors, and may be p-type transistors. At this time, the anode of the EL element 11 is electrically connected to the power supply line La of one example of the reference voltage line, the source Ns of the driving transistor Tr3 is electrically connected to the cathode of the EL element 11, and the drain of the transistor Tr3 is Nd. It is electrically connected to the ground voltage line Lb. Even in such a configuration, (1) to (5) according to the first embodiment, (1), (2), and (1) of the third embodiment can be obtained. The advantage to (7).

‧Drive transistor Tr3 has gate, source and drain, only To connect either the source and the drain, the other of the source and the drain is the power supply. Further, the drive circuit PCC includes a reference voltage line having a reference voltage, a drive transistor Tr3, an EL element 11 connected to the ground voltage line Lb and the connection terminal, and a storage capacitor for connecting the gate and the source. At least one of the sampling transistor Tr1 and the switching transistor Tr2 may be omitted in the driving circuit PCC.

For example, in an EL display device, the sampling transistor can also be omitted. The Tr1 and the switching transistor Tr2 electrically connect the scan line Ls to the gate of the driving transistor Tr3, and electrically connect the data line Ld to the source of the driving transistor Tr3. In short, the drive circuit PCC and the EL display device maintain a voltage corresponding to the light-emission voltage VD in the storage capacitor Cs during the light-emitting period, and cause a current corresponding to the light-emission voltage VD to flow to the EL element 11 via the drive transistor Tr3. Further, the EL display device maintains a voltage corresponding to the non-light-emitting voltage VDN while the storage capacitor Cs is not emitting light, and sets the voltage of the power supply terminal so that the current that has passed through the driving transistor Tr3 does not flow to the EL element 11, as long as it has The higher the illuminating voltage VD is, the lower the state in which the illuminating voltage VDN is not lowered.

[Detection action]

‧ The scan lines of the m columns are divided into a plurality of scan line groups composed of 10 scan lines adjacent to each other, and the detection target of the threshold voltage Vth of each frame is set as each scan line group.

As shown in Fig. 30, in the detection operation in the first frame, the pixel Px in the first column is set as the detection target from the first scanning line group. At the 2nd In the detection operation of the frame, the pixel Px in the eleventh column is set as the detection target from the second scanning line group. In this manner, the displacement of the target is detected every 10 columns from the pixel Px of the first column to the pixel Px of the 531st column for each frame displayed.

As shown in Figure 31, in the 55th frame, from the 1st scan line The group P2 of the second column is set as the detection target. In the 56th frame, from the second scanning line group, the pixel Px of the 12th column is set as the detection target. In this manner, for every frame displayed, the target system displacement is detected every 10 columns from the pixel Px of the second column to the pixel Px of the 532th column.

As shown in Figure 32, in the 487th frame, from the first scan In the line group, the pixel Px of the 10th column is set as the detection target. In the detection operation of the 488th frame, the pixel Px of the 20th column is set as the detection target from the second scanning line group. In this manner, for every frame displayed, from the pixel Px of the tenth column to the pixel Px of the 540th column, the displacement of the object is detected every tenth column. Thereby, the test data Dout of each column is updated once every time the frame is displayed m times.

‧ In addition, the scan line in column m can also be divided into In the case of a plurality of scanning line groups composed of the scanning lines of the adjacent ten columns, the correction of the display data Din based on the detection data Dout is performed as follows.

That is, the memory unit 53 of the control unit 50 has m/10 columns × n rows. The memory area corresponds to each of the ten pixels Px arranged along the row direction. For example, the memory unit 53 associates the pixel Px in the first row of the first scanning line group with the memory region in the first row and the first row, and sets the pixel Px in the second row of the second scanning line group. 2nd The memory area of the second row of the column is assigned. Further, the memory unit 53 associates the pixel Px of the 959th line of the 54th scanning line group with the memory area of the 54th line and the 959th line, and sets the pixel Px of the 960th line of the 54th scanning line group with The memory area of the 54th line and the 960th line is assigned.

The video signal processing unit 54 of the control unit 50 generates a display. In the case of the data Din, the gray scale data of each pixel Px and the detection data Dout corresponding to the pixel Px are read from the memory unit 53. Further, the video signal processing unit 54 performs addition and subtraction of the corresponding detection data Dout given to the pixel Px for the gray scale data of each pixel Px, and generates display data Din for each pixel Px.

‧The test that can be obtained during the display of this frame The data Dout is processed as the detection data Dout of all the columns during the next display of the frame.

‧The detection object can also be set to the same column in each frame. Further, the object to be detected may be set to be irregular in each frame. Further, in the case where the detection target is set to be irregular according to each frame, for example, the control unit 50 uses a random function that generates a random number in each frame from 1 to m. Further, as long as the timing of outputting the displacement waiting portion based on the detection displacement clock signal Clkr is synchronized with the timing of outputting the mask release portion based on the mask pulse signal MP, and these timings are delayed only from the start pulse signal SP2 in response to the generated random number The composition of time.

‧ The detection target can be set to two or more in each frame. At this time, the displacement clock signal Clkr for detection outputs two displacement waiting portions at timings different from each other, and the masking pulse signal MP also outputs two mask releasing portions at timings different from each other. Moreover, output 2 bits The timing of each of the shift waiting sections is synchronized with the timing of outputting each of the two mask releasing sections.

‧ For example, when the EL display device is activated, EL display The display device performs a detection operation for each of the drive circuits PCC in all or a part of the columns except for the period from the time of the pause to the restoration.

‧Can also use the test power applied in one detection action The pressure VM is configured to be different from each other according to each data line Ld. At this time, in the detection operation, each of the plurality of data lines Ld may be connected to the analog power source 70 via wirings different from each other. Alternatively, the detection voltage VM system may be used as the digital data, and supplied from the data driver 40 to the data line Ld.

‧The detection voltage can also be applied in one detection operation The data line Ld of the VM is a part of the entire data line Ld. At this time, in one detection operation, only the data line Ld which is one of the application targets of the detection voltage VM is connected to the analog power source 70 via the detection voltage switch SWs.

‧ In the above embodiment, as the driving transistor Tr3 The characteristic is that the threshold voltage Vth is detected, and the illuminating voltage VD is corrected based on the detected threshold voltage Vth. The present invention is not limited thereto, and the current amplification factor β may be detected as the characteristic of the driving transistor Tr3, and the illuminating voltage VD may be corrected based on the detected current amplification factor β. Further, as the characteristics of the driving transistor Tr3, both the threshold voltage Vth and the current amplification factor β can be detected. In short, the detection target to be detected is a parameter that affects the driving current supplied to the EL element 11 in the element characteristics of the driving transistor Tr3.

‧When the illuminating voltage VD is corrected, in addition to driving the crystallization In addition to the element characteristics of the body Tr3, the light-emitting characteristics of the EL element 11 such as the light-emitting luminance are also used.

‧ The light-emitting element may be an organic EL element or an inorganic EL element.

10‧‧‧ display panel

11‧‧‧Organic EL components

30‧‧‧Power Driver

40‧‧‧Data Drive

41‧‧‧Shift register circuit

42‧‧‧data register circuit

43‧‧‧ Data Latch Circuit

43a‧‧‧ Data Latch

44‧‧‧Voltage conversion circuit

44a‧‧‧Display DAC

45‧‧‧ buffer circuit

45a‧‧‧buffer

46a‧‧‧ Position Displacement

60‧‧‧Logical power supply

70‧‧‧ analog power supply

Ce‧‧‧pixel capacitor

Cp‧‧‧ parasitic capacitance

Cs‧‧‧Resistance Capacitor

Din‧‧‧Display information

La‧‧‧Power cord

Lb‧‧‧ grounding voltage line

Ld‧‧‧ data line

LP‧‧‧Latch pulse signal

Ls‧‧‧ scan line

PCC‧‧‧ drive circuit

Px‧‧ pixels

SP1‧‧‧ start pulse signal

Tr1‧‧‧Sampling transistor

Tr2‧‧‧Switching transistor

Tr3‧‧‧ drive transistor

VD‧‧‧ luminous voltage

VDN‧‧‧ non-lighting voltage

VEE‧‧‧ analog reference voltage

VgH‧‧‧Select voltage

VgL‧‧‧ non-selective voltage

LVDD‧‧‧ logic supply voltage

LVSS‧‧‧Logical Reference Voltage

ELVDD‧‧‧ drive voltage

ELVSS‧‧ ‧ reference voltage

WDVSS‧‧ ‧ write voltage

Claims (8)

An EL display device comprising a plurality of pixel circuits; the pixel circuit comprising: a driving transistor having a gate, a source and a drain, wherein the source and the drain are connected to each other at the source And the other side of the drain is a power supply end; the EL element is electrically connected to the connection end; and the holding capacitor is electrically connected to the gate and the source; the EL display device is in the following manner In the illuminating period, the holding capacitor maintains a voltage corresponding to the illuminating voltage, and a current corresponding to the illuminating voltage flows to the EL element via the driving transistor; during the non-lighting period, the holding capacitor remains equivalent The voltage of the voltage is not emitted, and the voltage of the power supply terminal is set such that the current that has passed through the driving transistor does not flow to the EL element; and the higher the light-emitting voltage is, the lower the non-light-emitting voltage is. An EL display device according to claim 1, wherein the frame formed by the light-emitting period and the non-light-emitting period is repeated; and the higher the light-emitting voltage is, the lower the non-light-emitting voltage is. An EL display device according to claim 1 or 2, wherein the non-light-emitting voltage is an inverted value which is a reference value in a set range of the light-emitting voltage and which is symmetrical with the light-emitting voltage. The EL display device according to any one of claims 1 to 3, wherein the pixel circuit is configured in such a manner that the polarity and the luminescence are the same when the illuminating voltage during the illuminating period is the same as or lower than the switching value The voltage is the same, and the higher the illuminating voltage is, the lower the voltage is set as the non-emissive voltage, which is held by the holding capacitor; when the illuminating voltage is higher than the switching value during the illuminating period, the polarity and the illuminating voltage are A different voltage is used as the non-emissive voltage and is held by the holding capacitor. The EL display device according to claim 4, wherein the pixel circuit is configured to set the non-light-emitting voltage to a constant value when the light-emitting voltage during the light-emitting period is higher than a switching value. The EL display device according to any one of claims 1 to 5, wherein the non-light-emitting period includes a detection operation for detecting a threshold voltage of the driving transistor; during the light-emitting period, The light-emitting voltage is corrected in advance using the detection result of the last detection operation. A driving method of an EL display device is a driving method of an EL display device having a plurality of pixel circuits, the pixel circuit comprising: a driving transistor having a gate, a source, and a drain, the source and the drain Either the connection end, the other end of the source and the drain is a power supply end; the EL element is electrically connected to the connection end; The holding capacitor is electrically connected to the gate and the source; the driving method of the EL display device includes: a light emitting step of maintaining a voltage corresponding to the light emitting voltage at the holding capacitor, so as to be dependent on the light emitting voltage a current flowing through the driving transistor to the EL element; and a non-light emitting step, wherein the holding capacitor maintains a voltage corresponding to a non-light-emitting voltage set to a state lower than a state in which the light-emitting voltage is higher, and The voltage at the power supply terminal has been set in such a manner that the current of the drive transistor does not flow to the EL element. The driving method of the EL display device of claim 7, wherein the non-lighting step further comprises a detecting step of detecting a threshold voltage of the driving transistor; and in the illuminating step, using the detection result of the last detecting step, The illuminating voltage is corrected in advance.