WO2015190258A1

WO2015190258A1 - Current driving device and driving method for current driving device

Info

Publication number: WO2015190258A1
Application number: PCT/JP2015/064659
Authority: WO
Inventors: 小林　賢次; 小倉　潤
Original assignee: 凸版印刷株式会社
Priority date: 2014-06-11
Filing date: 2015-05-21
Publication date: 2015-12-17

Abstract

The present invention is equipped with: a measurement unit which, for all of a plurality of data lines (Ld), sets a voltage exceeding the threshold voltage value of all of a plurality of driving transistors (T1), and then switches all of the data lines to a high-impedance state, thereby causing the voltages of all of the data lines to converge to a convergence voltage for each of the data lines, after which multiple references voltages and the convergence voltage are compared successively for each of a plurality of element circuits; and a setting unit, which sets a maximum reference value so as to be greater than the maximum value among all of the convergence voltages in at least one measurement prior to the present measurement, and such that the maximum reference value is smaller as the maximum convergence voltage value is smaller. Thus, it is possible to reduce the time required to obtain the characteristic values of driving transistors.

Description

Current driving device and driving method of current driving device

The present invention relates to a current driving device including a driving transistor for passing a current to a current driving element, and a driving method of the current driving device.

An EL display device, which is an example of an electroluminescence (EL) device, includes a plurality of EL elements positioned in a matrix and a plurality of thin film transistors for each EL element. The element is driven line-sequentially. For example, the EL device described in Patent Document 1 switches a selection transistor to an on state by scanning a scanning line, and applies a voltage based on display data between the gate and the source of the driving transistor. Then, the drain-source current based on the gate-source voltage of the driving transistor flows through the EL element, whereby the luminance gradation in the EL element is controlled for each scan of the scanning line.

On the other hand, the characteristic values such as the threshold voltage and current amplification factor of the driving transistor vary depending on the accumulated driving time of the driving transistor, so that the gate-source voltage applied to the driving transistor is the same. Even so, the drive current supplied from the drive transistor changes over time. Therefore, in order to correct the change in luminance of the EL element due to the change in the characteristic value of the driving transistor, for example, an EL device as described in Patent Document 2 periodically sets the characteristic value of the driving transistor. Is getting into.

JP-A-8-330600 JP 2010-128397 A

On the other hand, since the light emission of the EL element is stopped in the above-described measurement of the characteristic value, it is desired to reduce the time required for measuring such a characteristic value.
An object of the present invention is to provide a current driving device and a driving method of the current driving device that can shorten the time required for measuring the characteristic value of the driving transistor.

An EL device that solves the above problem is a pixel group including a plurality of element circuits, and each element circuit drives a current drive element, a data line, and a current based on a voltage set in the data line to the current drive. And a driving transistor having a current path for passing the element, and the data line includes the element circuit group configured to be electrically connectable to the current path. The current driver is a measurement unit configured to measure a convergence voltage for each element circuit, and the measurement unit is configured to measure the threshold value of the drive transistor for each of the plurality of element circuits. After setting one voltage that exceeds the voltage and is reverse-biased to the current drive element to the data line, the data line is switched to a high impedance state, whereby the voltage of the data line Is converged to a convergence voltage, and then, a plurality of reference voltages having different magnitudes and the convergence voltage are sequentially compared, and the plurality of reference voltages used for each element circuit are: The measurement unit in common with a plurality of the reference voltages used in other element circuits is provided. The EL device is a setting unit that sets a reference maximum value, which is the maximum value of all the reference voltages in the current measurement, and includes all the settings in at least one measurement before the current measurement. A setting unit configured to set the reference maximum value such that the reference maximum value is smaller as the maximum value is smaller than the maximum value in the convergence voltage and the maximum value is smaller;

A driving method of a current driving device that solves the above problem is an element circuit group including a plurality of element circuits, and the element circuit is based on a current driving element, a data line, and a voltage set for the data line. A drive transistor having a current path for passing a current to the current drive element, the data line is configured to be electrically connectable to the current path, and the driving method is performed for each of the plurality of element circuits. After setting one voltage on the data line that exceeds the threshold voltage of the driving transistor and that is a reverse bias to the current driving element, the data line is switched to a high impedance state, thereby And a step of converging the voltage of the data line to a convergence voltage, and a plurality of reference circuits having different sizes for each of the plurality of element circuits. A step of performing successive comparison between a voltage and the convergence voltage, thereby measuring the convergence voltage for each element circuit, wherein a plurality of the reference voltages used in each element circuit are used in other element circuits And a step common to a plurality of the reference voltages. The maximum value among all the reference voltages in the current measurement is the reference maximum value, which is larger than the maximum value among all the convergence voltages in at least one measurement before the current measurement. And a step of setting the reference maximum value such that the reference maximum value is smaller as the maximum value is smaller.

According to the above configuration, the maximum value among all the reference voltages in the current measurement is set based on the maximum value in the convergence voltage in at least one measurement prior to the current measurement. The maximum value of all reference voltages in the current measurement is smaller as the maximum value of the convergence voltage in at least one measurement prior to the current measurement is smaller. Is shorter as the convergence voltage in at least one measurement prior to the current measurement is smaller. As a result, it is possible to shorten the time required to acquire the characteristic value of the drive transistor, compared to a configuration in which the maximum value among all reference voltages in the measurement is a constant value for each measurement.

In the current driver, the setting unit is configured to increase the reference maximum so that the reference maximum value is smaller as the maximum value is larger than the maximum value of all the converged voltages in the previous measurement and the maximum value is smaller. A value may be set.

For example, when the temperature of the driving transistor in the previous measurement is significantly lower than the temperature of the driving transistor in the previous measurement, the maximum value of the convergence voltage in the previous measurement is slightly decreased from the maximum value of the convergence voltage in the previous measurement. Sometimes you do. Thus, even if the maximum value of the convergence voltage in the element circuit group does not increase monotonously for each measurement opportunity, the current drive device having the above configuration has the maximum value of the previous convergence voltage. Based on this, the reference maximum value in the current measurement is set. Therefore, it is possible to prevent the convergence voltage from being accurately measured when the maximum value of the reference voltage in the current measurement falls below the convergence voltage.

In the current driver, the setting unit is configured to increase the reference maximum value so that the reference maximum value is smaller as the maximum value is larger than the maximum value of all the convergence voltages in the previous measurement and the maximum value is smaller. May be set.

For example, when the driving transistor repeats flowing current through the current driving element, the threshold voltage of the driving transistor tends to increase monotonously. In this regard, in the current driving device having the above configuration, the reference maximum value in the current measurement is set based on the maximum value of the convergence voltage in the previous measurement. Therefore, since the population for determining the maximum value of the convergence voltage in the measurement before the current measurement is limited to the convergence voltage in the previous measurement, the maximum convergence voltage in the measurement before the current measurement is determined. The structure for determining the value can be simplified.

The current driving device sets a gradation voltage based on a driving amount of the current driving element to the data line after the measurement unit performs the current measurement, and then sets the current based on the gradation voltage to the current line. A drive unit for causing the drive transistor to flow is further provided. The setting unit may set a driving period in which the driving unit passes the current to the current driving element as a longer period as the reference maximum value in the current measurement is smaller.

The current driving device sets a gradation voltage based on a driving amount of the current driving element to the data line before the measurement unit performs the current measurement, and then sets the current based on the gradation voltage. A driving unit for causing the driving transistor to flow is further provided. The setting unit may set a driving period in which the driving unit passes the current to the current driving element as a longer period as the reference maximum value in the current measurement is smaller.

According to each of the current driving devices described above, the shorter the time required for measuring the convergence voltage, the longer the time for driving the current driving element, so the time required for measuring the convergence voltage and the time for driving the current driving element are It is possible to lengthen the drive time of the current drive element while suppressing the total sum from changing greatly.
In the EL device, the measurement unit may use, as the reference voltage, a voltage that is increased from a predetermined minimum value by a certain value in the successive comparison.

According to the current driver, since the reference voltage that is sequentially compared with the convergence voltage is increased from the predetermined minimum value by a certain value, the time required for the current measurement is reduced by the smaller reference maximum value in the current measurement. It will definitely be shorter.

In the current driving device, the setting unit obtains a value obtained by adding a constant value to a maximum value among all the convergence voltages in at least one measurement before the current measurement, and the reference maximum in the current measurement. It may be set to a value.

According to the current drive device, a voltage that is larger than the convergence voltage in the measurement prior to the current measurement by a certain value is set as the reference maximum value in the current measurement. Therefore, even if the convergence voltage increases from the measurement prior to the current measurement, if the range in which the convergence voltage increases is within a certain value, the reference maximum value in the current measurement is less than the convergence voltage. Therefore, it is possible to prevent the convergence voltage from being accurately measured.

According to the current driving device and the driving method of the current driving device of the present invention, it is possible to shorten the time required to acquire the characteristic value of the driving transistor.

It is a block diagram which shows the whole structure of the EL display apparatus in one Embodiment. It is a circuit diagram which shows the structure of the pixel circuit in one Embodiment with the block circuit diagram of a peripheral circuit. FIG. 3 is a circuit diagram showing voltage levels of a selection line, a power supply line, and a data line in a write operation according to an embodiment together with a circuit diagram of a pixel circuit. FIG. 3 is a circuit diagram illustrating voltage levels of a selection line, a power supply line, and a data line in a light emitting operation according to an embodiment together with a circuit diagram of a pixel circuit. FIG. 5 is a circuit diagram showing voltage levels of a selection line, a power supply line, and a data line in a measurement operation of an embodiment together with a circuit diagram of a pixel circuit. FIG. 3 is a block circuit diagram showing a configuration of a selection driver together with a pixel circuit in one embodiment. It is a block circuit diagram which shows the structure of the power supply driver in one Embodiment with a pixel circuit. 4 is a graph showing a relationship between a gate-source voltage and a drain-source current in a driving transistor according to an embodiment. It is a graph which shows the relationship between the elapsed time after the data line in one Embodiment was set to the high impedance state, and the voltage level of the source in a drive transistor. It is a block circuit diagram which shows the structure of the data driver in one Embodiment. It is a block circuit diagram which shows the structure of the system controller in one Embodiment. It is a timing chart which shows transition of the voltage level of the mask pulse signal which the timing controller outputs the selection start pulse signal in one embodiment, and the timing controller outputs. 6 is a timing chart showing transitions of voltage levels of signals output from a selection driver, a power supply driver, and a data driver in each of a light emission period and a non-light emission period in an EL display device according to an embodiment. It is a timing chart which shows transition of the voltage level of each signal which a selection driver, a power supply driver, and a data driver output in a measurement period in an EL display device of one embodiment. It is a time chart which shows transition of the writing operation which a pixel row performs in the 1st frame which the EL display device of one embodiment sets, display operation, and measurement operation. It is a time chart which shows transition of writing operation which a pixel row performs in the 2nd frame which EL display device of one embodiment sets, display operation, and measurement operation. It is a time chart which shows transition of a writing operation which a pixel row performs in a 540th frame which an EL display device of one embodiment sets, a display operation, and a measurement operation. 6 is a timing chart showing a transition of voltage levels in each selection line and a transition of voltage levels in each power supply line together with a start pulse signal and a mask pulse signal in one frame period set by the EL display device of one embodiment. . It is a block diagram which shows the pixel row by which the measurement period in the 1st frame to the 54th frame which the EL display apparatus of a modification is set is set. It is a block diagram which shows the pixel row by which the measurement period is set from the 55th frame to the 108th frame which the EL display apparatus of a modification is set. It is a block diagram which shows the pixel row by which the measurement period is set from the 487th frame to the 540th frame which the EL display apparatus of a modification sets.

An embodiment of an EL display device that is an example of an EL device and a driving method of an EL display device that is an example of a driving method of the EL device will be described with reference to FIGS.

[Configuration of EL Display Device]
As shown in FIG. 1, the EL display device includes a panel 10 including a plurality of pixels PX, a selection driver 20, a power supply driver 30, a data driver 40, and a system controller 50. The plurality of pixels PX are arranged in a matrix of m rows × n columns. m is an integer of 1 or more, and n is also an integer of 1 or more. Each pixel PX is an example of an element circuit.

Each of the m selection lines Ls extending in the row direction intersects each of the n columns of data lines Ld extending in the column direction in a three-dimensional manner in a plan view with respect to the panel 10. Each of the plurality of pixels PX is disposed in the vicinity of a portion where the selection line Ls and the data line Ld intersect three-dimensionally.

Each of the n columns of pixels PX arranged in the i-th row (i is an integer of 1 to m) is electrically connected to the i-th selection line Ls and the i-th power line La. Each of the m rows of pixels PX arranged in the j-th column (j is an integer of 1 to n) is electrically connected to the j-th data line Ld. A plurality of pixels PX electrically connected to one common selection line Ls is one pixel row as an example of an element circuit group, and each pixel line PX is electrically connected to one common data line Ld. A plurality of pixels PX connected to is one pixel column.

Each of the m selection lines Ls is electrically connected to the selection driver 20 in parallel. Each of the m rows of power supply lines La is electrically connected to the power supply driver 30 in parallel. Each of the n columns of data lines Ld is electrically connected to the data driver 40 in parallel.

The system controller 50 controls driving of the selection driver 20, driving of the power supply driver 30, and driving of the data driver 40 by outputting a plurality of control signals. The system controller 50 is configured with a central processing unit and a microcomputer having a storage unit as a center. The system controller 50 has a function of receiving an input signal SIG from the outside to the EL display device and extracting a gradation component included in the input signal SIG from the input signal SIG. The system controller 50 has a function of converting the extracted gradation component into a gradation value Din for controlling the luminance for each pixel PX.

The system controller 50 outputs the gradation value Din for each pixel PX to the data driver 40. The gradation value Din for each pixel PX is output in the order of row numbers for each row, and in the data for one row, the columns are output in the order of column numbers. The gradation value Din for each pixel PX is, for example, a digital value having 8 bits as a bit length.

The system controller 50 may extract a timing signal such as a system clock for driving the panel 10 from the input signal SIG, or may generate a separate timing signal when the input signal SIG does not include a timing signal component. Good. When the input signal SIG includes a timing signal component that defines the display timing of an image, for example, a composite video signal such as a television broadcast signal, the system controller 50 performs a timing in addition to a function of extracting a gradation component. It has a function of extracting signal components.

The system controller 50 generates a selection control signal SCON1 for controlling the driving of the selection driver 20 based on the timing signal, and inputs the selection control signal SCON1 to the selection driver 20. The system controller 50 generates a power control signal SCON 2 for controlling the driving of the power driver 30 based on the timing signal, and inputs the power control signal SCON 2 to the power driver 30. The system controller 50 generates a data control signal SCON3 for controlling the driving of the data driver 40 based on the timing signal, and inputs the data control signal SCON3 to the data driver 40.

[Configuration of Pixel PX]
As shown in FIG. 2, the pixel circuit PCC constituting the pixel PX includes three n-channel transistors, which are examples of thin film transistors, and one storage capacitor Cs. The three n-channel transistors may be, for example, thin film transistors having an amorphous silicon film as a semiconductor film, or thin film transistors having a polysilicon film as a semiconductor film.

The gate of the driving transistor T1 is electrically connected to the node N1. The source which is the first terminal of the driving transistor T1 is electrically connected to the anode of the EL element OEL which is an example of the current driving element through the node N2, and the drain which is the second terminal of the driving transistor T1 is connected to the power supply line through the node N3. It is electrically connected to La. The drive transistor T1 is a transistor capable of controlling a current in a saturation region, and has a function of causing a current based on the gate-source voltage Vgs of the drive transistor T1 to flow as a drain-source current Ids.

The anode of the EL element OEL is electrically connected to the node N2 in the pixel circuit PCC, and a reference level ELVSS such as a ground level is set as the voltage level of the cathode of the EL element OEL. Note that the EL element OEL includes a pixel capacitance, and the data line Ld includes a parasitic capacitance.

Among the two electrodes of the storage capacitor Cs, the first electrode is electrically connected to the node N1, and among the two electrodes of the storage capacitor Cs, the second electrode is electrically connected to the node N2. The storage capacitor Cs may be a parasitic capacitor formed between the gate of the driving transistor T1 and the source of the driving transistor T1, or may be a capacitive element provided separately between the node N1 and the node N2. Or a combination thereof. The holding capacitor Cs has a function of holding the gate-source voltage Vgs of the driving transistor T1.

The gate of the holding transistor T2 is electrically connected to the selection line Ls through the node N4. The drain of the holding transistor T2 is electrically connected to the power supply line La through the node N3, and the source of the holding transistor T2 is electrically connected to the node N1. The holding transistor T2 controls conduction between the drain of the driving transistor T1 and the gate of the driving transistor T1 based on the voltage level set on the selection line Ls.

For example, when the voltage level of the selection signal Vsel input to the selection line Ls is the high level H, the holding transistor T2 makes the drain of the driving transistor T1 and the gate of the driving transistor T1 conductive, thereby driving the driving transistor T1. Is diode-connected. On the other hand, when the voltage level of the selection signal Vsel input to the selection line Ls is the low level L, the holding transistor T2 electrically insulates the drain of the driving transistor T1 from the gate of the driving transistor T1. This causes the drive transistor T1 to release the diode connection.

The gate of the selection transistor T3 is electrically connected to the selection line Ls. The source of the selection transistor T3 is electrically connected to the data line Ld, and the drain of the selection transistor T3 is electrically connected to the node N2. The selection transistor T3 controls conduction between the source of the driving transistor T1 and the data line Ld based on the voltage level of the selection line Ls.

For example, when the voltage level of the selection signal Vsel input to the selection line Ls is the high level H, the selection transistor T3 makes the source of the driving transistor T1 and the data line Ld conductive, and the first of the storage capacitor Cs. A voltage corresponding to the difference between the voltage level at the electrode and the voltage level of the data signal Vd input to the data line Ld is held in the holding capacitor Cs. On the other hand, when the voltage level of the selection signal Vsel input to the selection line Ls is the low level L, the selection transistor T3 electrically insulates the source of the driving transistor T1 from the data line Ld.

[Operation of Pixel PX]
In the light emission period set in the pixel PX, the writing operation in which the gradation value level Vdata based on the gradation value Din is set in the data line Ld and the light emitting operation after the writing operation are performed in m rows × n columns. This is a period in which the pixel circuit PCC performs each pixel row in the order of row numbers.

In the non-light emission period set in the pixel PX, the writing operation in which the gradation value level Vdata corresponding to the lowest gradation value is set in the data line Ld and the non-light emission operation after the writing operation are performed in m rows. This is a period in which the pixel circuits PCC of xn columns perform one pixel row at a time in the row number order.

During the measurement period set for the pixel PX, the writing operation in which the measurement level VM is set to the data line Ld and the measurement operation after the writing operation are performed by the pixel circuit PCC of m rows × n columns. This is the period for line by line.

[Write operation during light emission period]
As shown in FIG. 3, in the writing operation in the light emission period, the selection driver 20 sets the selection signal Vsel to the high level H, and sets the holding transistor T2 and the selection transistor T3 to the on state. The power supply driver 30 sets the write level WDVSS, which is a voltage level substantially equal to the reference level ELVSS, to the power supply signal Va. The data driver 40 sets the gradation value level Vdata generated from the gradation value Din to the data signal Vd. The holding transistor T2 and the selection transistor T3 write a voltage corresponding to the difference between the gradation value level Vdata and the writing level WDVSS in the holding capacitor Cs.

The voltage level set in the data signal Vd in the writing operation in the light emission period is a gradation value level Vdata corresponding to the gradation value Din, and is a voltage level lower than the reference level ELVSS and the writing level WDVSS. is there.

When such a data signal Vd is input to the data line Ld, the source of the drive transistor T1 is set to a voltage level lower than the reference level ELVSS. The gate of the diode-connected driving transistor T1 is set to a voltage level equal to the drain of the driving transistor T1. As a result, a forward bias is set to the drain-source voltage Vds of the driving transistor T1, and a drain-source current Ids based on the drain-source voltage Vds flows.

At this time, since the drive transistor T1 is diode-connected, the drain-source voltage Vds of the drive transistor T1 is substantially equal to the gate-source voltage Vgs. Then, a gate-source voltage Vgs that is forward biased between the gate and source of the driving transistor T1 and reversely biased with respect to the EL element OEL is written into the storage capacitor Cs.

[Write operation during non-emission period]
The write operation in the non-light emission period differs from the write operation in the light emission period in the voltage level set on the data line Ld. The voltage level set in the data signal Vd in the writing operation in the non-light emitting period is a gradation value level Vdata corresponding to the lowest gradation, and is a voltage level substantially equal to the reference level ELVSS and the writing level WDVSS. is there.

When such a data signal Vd is input to the data line Ld, the source of the drive transistor T1 is set to a voltage level substantially equal to the reference level ELVSS. Since the gate of the diode-connected driving transistor T1 is set to a voltage level equal to that of the drain of the driving transistor T1, a zero bias that is substantially 0 V is set to the drain-source voltage Vds of the driving transistor T1. The drain-source current Ids does not flow.

At this time, since the drive transistor T1 is diode-connected, the drain-source voltage Vds of the drive transistor T1 is substantially equal to the gate-source voltage Vgs. Then, the gate-source voltage Vgs that is almost zero bias between the gate and the source of the driving transistor T1 is written in the storage capacitor Cs.

[Write operation during measurement period]
In the writing operation in the measurement period, the voltage level set to the data line Ld is different from that in the light emission period. The voltage level set for the data signal Vd in the write operation during the measurement period is the measurement level VM, which is lower than the reference level ELVSS and the write level WDVSS, and the write level WDVSS and the measurement level VM. Is a voltage level exceeding the threshold value of the driving transistor T1.

When such a data signal Vd is input to the data line Ld, the source of the drive transistor T1 is set to a voltage level lower than the reference level ELVSS. The gate of the diode-connected driving transistor T1 is set to a voltage level equal to that of the drain of the driving transistor T1, and a forward bias is set to the drain-source voltage Vds of the driving transistor T1, so that the drain-source voltage is set. A drain-source current Ids based on Vds flows.

At this time, since the drive transistor T1 is diode-connected, the drain-source voltage Vds of the drive transistor T1 is substantially equal to the gate-source voltage Vgs. The gate-source voltage Vgs that is forward biased between the gate and source of the driving transistor T1 and reversely biased with respect to the EL element OEL exceeds the threshold voltage Vth of the driving transistor T1. And is written to the storage capacitor Cs.

[Light emission operation]
As shown in FIG. 4, in the light emission operation in the light emission period, the selection driver 20 sets the selection signal Vsel to the low level L, and sets the holding transistor T2 and the selection transistor T3 to the off state. The power supply driver 30 sets the light emission level ELVDD, which is a voltage level higher than the write level WDVSS, such that the drive transistor T1 is driven in the saturation region, as the power supply signal Va. The driving transistor T1 allows a drain-source current Ids to flow based on the gate-source voltage Vgs held by the holding capacitor Cs.

At this time, the drain-source current Ids in the driving transistor T1 has a magnitude based on the difference between the gate-source voltage Vgs and the threshold voltage Vth in the driving transistor T1, and the gate-source voltage Vgs. And the difference from the threshold voltage Vth. Since the gate-source voltage Vgs held in the holding capacitor Cs in the write operation during the light emission period exceeds the threshold voltage Vth of the drive transistor T1, the drain-source voltage is connected to the current path of the drive transistor T1. The current Ids flows and the EL element OEL emits light.

[Non-light emission operation]
In the non-light emission operation in the non-light emission period, the selection driver 20 sets the selection signal Vsel to the low level L and sets the holding transistor T2 and the selection transistor T3 to the off state, as in the light emission operation. The power supply driver 30 sets the light emission level ELVDD, which is a voltage level higher than the write level WDVSS, such that the drive transistor T1 is driven in the saturation region, as the power supply signal Va.

At this time, although the drain of the driving transistor T1 is set to a higher voltage level than the source of the driving transistor T1, according to the writing operation in the non-light emitting period, the gate-source voltage held in the holding capacitor Cs. Vgs is approximately 0V. Therefore, the drain-source current Ids does not flow in the current path of the driving transistor T1, and the EL element OEL does not emit light.

[Measurement operation]
As shown in FIG. 5, in the measurement operation in the measurement period, the selection driver 20 sets the selection signal Vsel to the high level H, and sets the holding transistor T2 and the selection transistor T3 to the on state. The power supply driver 30 sets the write level WDVSS to the power supply signal Va, and the data driver 40 disconnects the connection between the output circuit of the data signal Vd and the data line Ld, thereby causing the data line Ld to be in the high impedance state HZ. Set. The data driver 40 maintains the high impedance state HZ of the data line Ld until the elapsed time, which is the time elapsed since the setting of the high impedance state HZ, reaches a predetermined relaxation time ts.

At this time, the voltage level of the source in the driving transistor T1 gradually approaches the voltage level of the drain of the driving transistor T1 as the elapsed time increases. In addition, the drain-source current Ids of the driving transistor T1 also gradually decreases, and accordingly, the charge accumulated in the storage capacitor Cs is gradually discharged. When the charge accumulated in the storage capacitor Cs is gradually discharged, the voltage between both electrodes of the storage capacitor Cs, that is, the gate-source voltage Vgs of the drive transistor T1 gradually decreases. As a result, the voltage level of the source of the driving transistor T1 gradually increases as the elapsed time passes. The rise in the voltage level of the source of the driving transistor T1 continues to a voltage level at which the drain-source current Ids of the driving transistor T1 almost does not flow. When the drain-source current Ids stops flowing, the discharge of the storage capacitor Cs also stops. .

Thereby, in principle, the gate-source voltage Vgs of the driving transistor T1 converges to the threshold voltage Vth in the driving transistor T1. However, in practice, the discharge period of the storage capacitor Cs cannot be set to infinity, and the sub-threshold current flows even if the discharge period of the storage capacitor Cs continues indefinitely. Information on the threshold voltage Vth is lost. Therefore, a predetermined discharge period is defined as the predetermined relaxation time ts, and the convergence level Vs, which is the voltage level when the relaxation time ts has elapsed, is held on the data line Ld as a voltage level based on the threshold voltage Vth. Let The difference between the reference voltage level and the convergence level Vs is the convergence voltage, and the convergence voltage increases as the threshold voltage Vth increases.

During this period, the source voltage level in the drive transistor T1 is lower than the write level WDVSS and the reference level ELVSS, and therefore the drain-source current Ids does not flow through the EL element OEL.

[Configuration of Selected Driver 20]
As shown in FIG. 6, the shift register circuit 21 included in the selection driver 20 generates a parallel signal having a bit length of m bits from the selection start pulse signal SP that is one of the selection control signals SCON1. When the drive shift clock Clks is input to the shift register circuit 21 as a shift clock signal, the shift register circuit 21 shifts the selection start pulse signal SP bit by bit for each period of the drive shift clock Clks. When the measurement shift clock Clkr is input as a shift clock signal, the shift register circuit 21 shifts the selection start pulse signal SP by one bit for each period of the measurement shift clock Clkr.

The m-bit parallel signal generated by the shift register circuit 21 is a signal for selecting one selection line Ls from the m selection lines Ls one by one in the order of row numbers. The shift register circuit 21 synchronizes the generation of a parallel signal for selecting one selection line Ls with the cycle of the shift clock signal.

The drive shift clock Clks is a shift clock signal for setting the write operation of the gradation value level Vdata in order of the row numbers one row at a time. The measurement shift clock Clkr is used as one selection line Ls among the plurality of selection lines Ls while the shift register circuit 21 shifts the selection start pulse signal SP from the first bit to the m-th bit using the measurement shift clock Clkr. Is a shift clock signal for setting the write operation of the measurement level VM. The period of the measurement shift clock Clkr is sufficiently shorter than the period of the drive shift clock Clks.

The shift register circuit 21 initializes the shift of the selection start pulse signal SP when the clear signal RST is input to the shift register circuit 21. The shift register circuit 21 starts the selection of the selection line Ls from the first row again when the selection start pulse signal SP is input again after the clear signal RST is input.

The shift register circuit 21 outputs a parallel signal generated by shifting the selection start pulse signal SP only when the selection mask pulse signal MP1 is logically at a high level. When the selection mask pulse signal MP1 is logically at a low level, the shift register circuit 21 outputs a parallel signal in which no selection line Ls is selected regardless of the parallel signal generated by shifting the selection start pulse signal SP. To do.

For example, when the shift clock signal is the drive shift clock Clks and the selection mask pulse signal MP1 is logically at the high level, the shift register circuit 21 selects any one selection line among all the selection lines Ls. The generation of the parallel signal for selecting Ls is synchronized with the drive shift clock Clks.

For example, when the shift clock signal is the measurement shift clock Clkr and the selection mask pulse signal MP1 is logically at the low level, the shift register circuit 21 continues to output a parallel signal in which no selection line Ls is selected. . When the shift by the cycle of the measurement shift clock Clkr is advanced q times (1 ≦ q ≦ m) and the voltage level of the selection mask pulse signal MP1 is switched to the high level, the shift register circuit 21 A parallel signal for selecting the selection line Ls is output. Next, when the voltage level of the selection mask pulse signal MP1 is switched to the low level, the shift register circuit 21 again outputs a parallel signal in which no selection line Ls is selected.

When the selection mask pulse signal MP1 is input, the shift register circuit 21 can select the selection lines Ls row by row in the order of the row numbers in the cycle of the drive shift clock Clks, or the specific row up to the q-th row. It is also possible not to select the selection line Ls. Note that the parallel signal output control by the input of the selection mask pulse signal MP1 is realized, for example, by providing an AND circuit to which the selection mask pulse signal MP1 is input at an output stage for each bit of the shift register circuit 21. .

The output buffer 22 included in the selection driver 20 converts the voltage level of the parallel signal output from the shift register circuit 21 into a voltage level driven by the holding transistor T2 and the selection transistor T3. The output buffer 22 is connected to the m selection lines Ls, and associates the m selection lines Ls one by one with the bit number of the parallel signal.

For example, when the q-th bit is selected in the parallel signal output from the shift register circuit 21, the output buffer 22 converts the voltage level of the q-th bit into a high level H in the pixel circuit PCC, and the q-th bit. The voltage level of bits other than the number bit is converted to a low level L in the pixel circuit PCC. Then, the output buffer 22 sets the high level H to the selection signal Vsel of the q-th selection line Ls, and sets the low level L to the selection signal Vsel of the selection lines Ls other than the q-th row.

[Configuration of Power Supply Driver 30]
As shown in FIG. 7, the shift register 31 included in the power supply driver 30 has a bit length of m bits from the selection start pulse signal SP that is one of the power supply control signals SCON <b> 2, similarly to the shift register circuit 21 included in the selection driver 20. A parallel signal is generated.

The m-bit parallel signal generated by the shift register 31 is a signal for selecting one power supply line La from the m power supply lines La in order of the row numbers one by one. The shift register 31 generates a parallel signal for selecting one power supply line La according to the cycle of the shift clock.

The shift register 31 initializes the shift of the selection start pulse signal SP when the clear signal RST is input to the shift register 31. The shift register 31 starts the selection of the power supply line La from the first row again when the selection start pulse signal SP is input again after the clear signal RST is input.

The shift register 31 outputs the parallel signal generated by shifting the selection start pulse signal SP only when the power supply mask pulse signal MP2 is logically at a high level. On the other hand, when the power supply mask pulse signal MP2 is logically at a low level, the shift register 31 selects all the power supply lines La regardless of the parallel signal generated by shifting the selection start pulse signal SP. Output parallel signals.

For example, when the shift clock signal is the drive shift clock Clks and the power mask pulse signal MP2 is logically at a high level, the shift register 31 uses a parallel signal for selecting any one power line La. The generation is synchronized with the period of the drive shift clock Clks.

For example, when the shift clock signal is the drive shift clock Clks and the power mask pulse signal MP2 is logically at a low level, the shift register 31 selects all the bit values in the parallel signal for the power line La. Switch to high level for.

For example, when the shift clock signal is the measurement shift clock Clkr and the power mask pulse signal MP2 is logically at a low level, the shift register 31 outputs a parallel signal for selecting all the power lines La.

When the power mask pulse signal MP2 is input, the shift register 31 selects the power line La one row at a time in accordance with the cycle of the drive shift clock Clks, or in the cycle of the measurement shift clock Clkr, It is also possible to select the line La at a time. The control of the output of the parallel signal by the input of the power supply mask pulse signal MP2 is realized, for example, by providing an AND circuit to which the power supply mask pulse signal MP2 is input in an output stage for each bit of the shift register 31. .

The output buffer 32 provided in the power supply driver 30 converts the voltage level of the parallel signal output from the shift register 31 into either the write level WDVSS or the light emission level ELVDD. The output buffer 32 is connected to m rows of power supply lines La, and associates m rows of power supply lines La one by one with the bit number of the parallel signal.

For example, when the q-th bit is selected in the parallel signal output from the shift register 31, the output buffer 32 converts the voltage level of the q-th bit into the write level WDVSS, and a voltage other than the q-th bit. The level is converted to the light emission level ELVDD. Then, the output buffer 32 receives the power signal Va in which the write level WDVSS is set for the q-th power line La, and the light emission level ELVDD is set for the power lines La other than the q-th line. The power supply signal Va is input.

[Threshold voltage Vth and relaxation time ts]
A characteristic curve L1 in FIG. 8 shows the characteristic of the driving transistor T1 in the initial state, which is a state before the characteristic value changes with time. In FIG. 8, a characteristic curve L2 shows the state of the driving transistor T1 in a shifted state where the characteristic value is shifted with time. 8 indicates the drain-source current Ids of the drive transistor T1 when the power supply signal Va is set to the write level WDVSS. The horizontal axis of FIG. 8 is a voltage corresponding to the gate-source voltage Vgs and is the difference between the gate level V0 corresponding to the write level WDVSS and the gradation value level Vdata set to the data signal Vd. A drive voltage (= V0−Vd) is shown.

The threshold voltage Vth [V] of the driving transistor T1 in the initial state is set to the initial value Vth _0, and the current amplification factor [A / V ² ] of the driving transistor T1 in the initial state is set to the current amplification factor β. Further, the threshold voltage Vth in the shift state is set to a shift value Vth ₁ (= initial value Vth ₀ + shift amount ΔVth).

At this time, the drain-source current Ids in the initial state is expressed by the following formula (1), and the drain-source current Ids in the shifted state is expressed by the following formula (2).
Ids = β (V0−Vd−Vth ₀ ) ² (1)
Ids = β (V0−Vd−Vth ₁ ) ² (2)

As shown in FIG. 8 and equations (1) and (2), the characteristic curve L2 has a shape in which the drive voltage in the characteristic curve L1 is translated by the shift amount ΔVth, and before and after the shift of the threshold voltage Vth. The shape of the characteristic curve L1 is substantially the same as the shape of the characteristic curve L2. The fact that the shape of the characteristic curve L1 and the shape of the characteristic curve L2 are almost the same indicate that the change over time of the current amplification factor β is a threshold value, as shown in equations (1) and (2). It shows that the voltage Vth is sufficiently smaller than the change with time. Therefore, the shift amount ΔVth which is the difference between the initial value Vth ₀ and the shift value Vth ₁ is added to the gradation value level Vdata, whereby the drain-source current Ids in the shift state is corrected. That is, by adding a threshold correction amount k corresponding to the shift amount ΔVth to the reference gradation value Db generated from the input signal SIG described above, the threshold over time of the change in the luminance of the EL element OEL. Changes due to the shift of the value voltage Vth are corrected.

The relaxation time ts in the measurement operation will be described with reference to FIG. FIG. 9 shows the relationship between the voltage level VNs of the data line Ld in the measurement operation, that is, the voltage level based on the voltage level of the source in the driving transistor T1 and the elapsed time t.

As shown in FIG. 9, when the elapsed time t advances in the measurement operation, the voltage level VNs of the data line Ld approaches the write level WDVSS from the measurement level VM according to the discharge in the storage capacitor Cs. When the elapsed time t reaches the relaxation time ts, the voltage level VNs of the data line Ld converges to the convergence level Vs based on the threshold voltage Vth, and the drain-source current Ids hardly flows.

At this time, the convergence level Vs, which is the voltage level of the data line Ld when the relaxation time ts has elapsed, is a voltage level reflecting the shift amount ΔVth, and is a characteristic value based on the threshold voltage Vth at that time. is there. The threshold voltage Vth of the drive transistor T1 is estimated as a voltage based on the difference between the convergence level Vs and the write level WDVSS. Then, the convergence level Vs held in the data line Ld is taken into the data driver 40, and a convergence voltage that is a difference between the convergence level Vs and a reference voltage level, for example, an analog reference voltage DVSS is obtained. It is converted into measurement data Dout which is a digital value. In the conversion from the convergence level Vs to the measurement data Dout, the reference voltage level is set so that the measurement data Dout increases as the threshold voltage Vth increases.

[Configuration of Data Driver 40]
As shown in FIG. 10, the data driver 40 constituting the measurement unit and the setting unit includes a shift register 41, a data register 42, a data latch circuit 43, a DAC 44, a buffer 45, a level shifter 46, and an up counter 47. ing.

The shift register 41, the data register 42, the data latch circuit 43, and the up-counter 47 are configured as a low withstand voltage circuit. These circuits include a logic high voltage LVDD that is logically high from the logic power supply 60, and , A logic low voltage LVSS of a logical low level is applied.

The DAC 44 and the buffer 45 are configured as high withstand voltage circuits, and a high level analog reference voltage DVSS and a low level analog power supply voltage VEE are applied to these circuits from the analog power supply 70. Analog reference voltage DVSS is set to a voltage level substantially equal to write level WDVSS and reference level ELVSS.

The shift register 41 generates a parallel signal having a bit length of n bits from the data start pulse signal SP1. When the data shift clock Clkd is input as a shift clock signal, the shift register 41 shifts the data start pulse signal SP1 bit by bit according to the cycle of the data shift clock Clkd.

The n-bit parallel signal generated by the shift register 41 is a signal for selecting one data line Ld from the n columns of data lines Ld one column at a time in the column number order. The shift register 41 synchronizes the generation of the parallel signal for selecting the data line Ld with the cycle of the data shift clock Clkd.

The data shift clock Clkd is a shift clock signal that assigns the gradation value Din to all of the pixels PX for one row in a period in which one selection line Ls is selected in the write operation. The period of the data shift clock Clkd is sufficiently shorter than the period of the drive shift clock Clks, and is, for example, 1 / n of the drive shift clock Clks and substantially the same as the period of the measurement shift clock Clkr.

The data shift clock Clkd is a clock signal that increases the count value of the up counter 47 in the measurement operation. The number N of transmissions of the data shift clock Clkd in the measurement operation is the maximum count value counted by the up counter 47. The count value counted by the up counter 47 is a digital value for stepping down the reference level, which is a voltage level for measuring the convergence voltage, by one stage for each count value.

For example, when the count value counted by the up counter 47 is “1”, the voltage level based on the digital value “1” is a voltage level lower than the analog reference voltage DVSS by 1 × resolution Vcnt [V]. Generated as a level. When the count value counted by the up counter 47 is “4”, the voltage level based on the digital value “4” is a voltage level lower than the analog reference voltage DVSS by 4 × resolution Vcnt [V]. Generated as a level. Each time the count value of the up counter 47 changes, a new reference level to be compared with the convergence level Vs is generated. The difference between the reference level and the reference voltage level is the reference voltage. The reference voltage level is the same as the reference voltage level in the convergence voltage, and the reference voltage increases as the count value increases. The reference voltage level is set.

The data register 42 includes n columns × k registers, and includes k registers for each bit of the parallel signal output from the shift register 41. For example, when the maximum gradation value in the gradation value Din is 255, the gradation value Din is an 8-bit digital value, and the data register 42 includes n columns × 8 registers. For the parallel signal output from the shift register 41, k registers are selected from the n columns × k registers in the order of the column numbers one column at a time. The data register 42 stores the gradation value Din in the selected k registers, and shifts the k registers as the storage destination one column at a time in the order of the column number according to the cycle of the data shift clock Clkd.

The data latch circuit 43 includes an n-column data latch 43a, an n-column AND circuit 43b, and an n-column flip-flop 43c. The data latch circuit 43 includes an n-column input switch SW1, an n-column output switch SW2, an n-column measurement switch SW3, and one transfer switch SWtrs.

The output terminal of the up counter 47 is connected in parallel to each input terminal of the n-row input switch SW1. The up counter 47 counts up in synchronization with the data shift clock Clkd in the measurement operation, and inputs the count value, which is the number N of transmissions of the data shift clock Clkd, as a digital value to each of the n columns of input switches SW1.

The input switch SW1 in the j-th column (1 ≦ j ≦ n) is connected to the input terminal of the data latch 43a in the j-th column. The input switch SW1 in the p-th column (1 ≦ p ≦ n−1) is driven based on the data control signal SCON3 input from the system controller 50, and the input terminal of the data latch 43a in the p-th column is connected to the data register. 42 is connected to any one of the output terminal of the register in the p-th column, the output terminal of the up-counter 47, and the output terminal of the data latch 43a in the p + 1-th column.

The output switch SW2 in the j-th column is connected to the output terminal of the data latch 43a in the j-th column. The output switch SW2 in the (p + 1) th column is driven based on the data control signal SCON3 input from the system controller 50, and the output terminal of the data latch 43a in the (p + 1) th column is connected to the input terminal of the level shifter 46 in the (p + 1) th column. Connect to one of the input terminals of the input switch SW1 in the column. The output switch SW2 in the first column is driven based on a control signal from the system controller 50. The output terminal of the data latch 43a in the first column is the input terminal of the level shifter 46 in the first column and the input of the transfer switch SWtrs. Connect to one of the terminals.

The measurement switch SW3 in the j-th column is driven based on the data control signal SCON3 input from the system controller 50, and an output terminal that is a Q terminal of the flip-flop 43c in the j-th column and a logical product circuit in the j-th column The connection and disconnection with the input terminal 43b are switched.

The transfer switch SWtrs is driven based on the data control signal SCON3 input from the system controller 50, and switches connection and disconnection between the output terminal of the output switch SW2 in the first column and the system controller 50.

The input terminal of the data latch 43a in the j-th column (1 ≦ j ≦ n) is connected to the register in the j-th column of the data register 42 in the write operation, light emission operation, and non-light emission operation described above. When the data latch 43a in the j-th column and the register in the j-th column are connected, every time the output levels of the AND circuits 43b in the n-th column all become logically high, the data in the j-th column The latch 43a holds the gradation value Din stored in the register in the jth column. The data latch 43a in the j-th column outputs the gradation value Din held in the data latch 43a in the j-th column to the DAC 44. The n-column data latch 43a holds the gradation value Din for one row stored in the data register 42 every time the output levels of the n-column AND circuits 43b logically become high. . The n-column data latches 43a output the held gradation values Din for one row to the n-column DACs 44 all at once.

On the other hand, each input terminal of the n-row data latch 43a is connected in parallel to the output terminal of the up counter 47 in the above-described measurement operation. When the input terminal of each of the n columns of data latches 43a and the output terminal of the up counter 47 are connected, the data shift clock Clkd and the latch pulse signal LP are synchronized, and the data shift clock Clkd and the latch pulse signal LP are synchronized. Are input to the data driver 40. The j-th column data latch 43a holds the count value of the up-counter 47 each time the output level of the j-th AND circuit 43b becomes a logical high level.

For example, between the two data latches 43a, when the output level of the AND circuit 43b to which the data latches 43a are connected simultaneously becomes a logical high level, each of the two data latches 43a holds the same count value. To do. On the other hand, when the output level of the AND circuit 43b connected to the two data latches 43a becomes logically high at different timings, each of the two data latches 43a Holds the count value.

Further, the input terminal of the data latch 43a in the p-th column is connected to the output terminal of the data latch 43a in the p + 1-th column in the measurement operation described above. When the input terminal of the data latch 43a in the p-th column and the output terminal of the data latch 43a in the p + 1-th column are connected, every time the output level of the AND circuit 43b in the p-th column becomes logically high. The data latch 43a in the p-th column holds the data held in the data latch 43a in the p + 1-th column as measurement data Dout.

At this time, the data latch 43a in the nth column, which is the last column, is connected to the logic power supply 60, and the logic low voltage LVSS is applied to the data latch 43a in the nth column. The output terminal of the data latch 43a in the first column is connected to the system controller 50 and outputs the measurement data Dout held in the data latch 43a in the first column to the system controller 50. The data latches 43a in the first column are held in the data latches 43a from the second column to the nth column each time the output level of the AND circuit 43b in the first column becomes a logical high level. Measurement data Dout is held from the data latch 43a in the second column in the order of the column numbers, and the held measurement data Dout is output to the system controller 50.

Between the output switch SW2 in the j-th column and the DAC 44 in the j-th column, a j-th level shifter 46 that is a voltage adjusting circuit from the low withstand voltage circuit to the high withstand voltage circuit is provided. The level shifter 46 in the j-th column converts the digital value that is the output value of the data latch 43a in the j-th column into the drive level of the DAC 44 in the j-th column.

Each of the n columns of DACs 44 is a linear voltage digital-analog conversion circuit in which an analog value output from the DAC 44 has linearity with respect to a digital value input to the DAC 44. Each of the n columns of DACs 44 sets the bit length of the digital value, which is the input range at the time of voltage conversion, to 8 bits, which is equal to the bit length that is the range of the gradation value Din.

When the input terminal of the jth DAC 44 and the output terminal of the jth data latch 43a are connected via the level shifter 46, the jth DAC 44 is held in the jth data latch 43a. The converted digital value is converted into an analog value and input to the non-inverting input terminal of the buffer 45.

For example, in the write operation during the light emission period and the write operation during the non-light emission period, the data latch 43a in the j-th column holds the gradation value Din, which is an example of the drive amount. At this time, the DAC 44 in the j-th column converts the gradation value Din, which is a digital value, into an analog value to generate a gradation value level Vdata based on the gradation value Din, and applies it to the non-inverting input terminal of the buffer 45. input.

On the other hand, in the measurement operation in the measurement period, the data latch 43a in the j-th column holds the count value of the up counter 47. At this time, the DAC 44 in the j-th column converts the count value, which is a digital value, into a reference level, which is an analog value, and inputs it to the non-inverting input terminal of the buffer 45.

The non-inverting input terminal of the buffer 45 in the j-th column is connected to the output terminal of the DAC 44 in the j-th column. The inverting input terminal of the buffer 45 in the j-th column is connected to a portion between the display switch SWd and the pixel circuit PCC in the j-th column on the data line Ld. The output terminal of the buffer 45 in the j-th column is connected to the data line Ld via the display switch SWd in the j-th column.

The buffer 45 in the j-th column expresses an output function that suppresses the output impedance of the data driver 40 when the display switch SWd is in the on state, and converts the analog value input from the DAC 44 in the j-th column to the gradation value level. Output as Vdata.

For example, in the writing operation in the light emission period and the writing operation in the non-light emission period, the display switch SWd is in the on state, and the DAC 44 in the j-th column sets the analog value that is the converted value of the gradation value Din to j Input to the buffer 45 in the column. Then, the buffer 45 in the jth column inputs the gradation value level Vdata, which is the conversion result of the gradation value Din in the jth column, to the data line Ld in the jth column.

On the other hand, in the measurement operation during the measurement period, the display switch SWd is in the off state, and the buffer 45 in the j-th column outputs the result of comparison between the input level of the non-inverting input terminal and the input level of the inverting input terminal. Functions as a comparator. Then, the buffer 45 in the j-th column compares the reference level that is the output level of the DAC 44 with the convergence level Vs that is the voltage level of the data line Ld in the j-th column, that is, compares the reference voltage with the convergence voltage. Then, the result of the comparison is output.

At this time, when the input level of the non-inverting input terminal is higher than the input level of the inverting input terminal, the voltage level output from the buffer 45 is a high level substantially equal to the analog power supply voltage VEE. On the other hand, when the input level of the non-inverting input terminal is lower than the input level of the inverting input terminal, the voltage level output from the buffer 45 is lower than the analog power supply voltage VEE.

For example, when the DAC 44 in the j-th column outputs a reference level, the buffer 45 in the j-th column compares the reference level at that time with the convergence level Vs of the data line Ld, and outputs the comparison result. At this time, since the reference level output from the DAC 44 in the j-th column is a voltage level that drops every time the up-counter 47 counts up, while the reference level is higher than the convergence level Vs, the j-th column The voltage level output from the eye buffer 45 remains high. When the reference level is lower than the convergence level Vs, the voltage level output from the buffer 45 in the j-th column is switched from the high level to the low level.

The output terminal of the buffer 45 in the jth column is connected in parallel to the input terminal of the display switch SWd in the jth column and the input terminal of the level shifter 48 in the jth column. The display switch SWd in the j-th column is driven based on the data control signal SCON3 input from the system controller 50, and the connection destination of the output terminal of the buffer 45 in the j-th column is connected to the j-th data line Ld. Switch to the level shifter 48 in the jth column.

When the display switch SWd in the j-th column connects the output terminal of the buffer 45 in the j-th column and the data line Ld in the j-th column, the j-th column buffer 45 is connected in a negative feedback manner and has a gradation value level. Vdata is generated. In contrast, when the display switch SWd in the j-th column disconnects the buffer 45 and the data line Ld in the j-th column, the voltage level of the data line Ld is set to the inverting input terminal of the buffer 45.

An output terminal of the measurement voltage switch SWs is connected to the output side of the display switch SWd in the j-th column and between the connection destination of the inverting input terminal of the buffer 45 in the j-th column and the pixel circuit PCC. Yes. The measurement voltage switch SWs is driven based on the data control signal SCON3 input from the system controller 50 to the measurement voltage switch SWs, and switches between connection and disconnection of the data line Ld and the analog power supply 70. When the measurement voltage switch SWs connects the data line Ld and the analog power supply 70 and the display switch SWd is in the off state, the voltage level of the data line Ld is set to the measurement level VM.

Between the output terminal of the buffer 45 and the input terminal of the flip-flop 43c, a level shifter 48 which is a voltage adjusting circuit from the high withstand voltage circuit to the low withstand voltage circuit is provided. The level shifter 48 converts the comparison result output from the buffer 45 into the drive level of the flip-flop 43c.

The n-row flip-flops 43c are D-type flip-flops, and the latch pulse signal LP is input from the system controller 50 to the clock terminals of the flip-flops 43c. The input terminal which is the D terminal of the n-row flip-flop 43c is connected to the output terminal of the level shifter 48, and the output terminal which is the Q terminal of the n-row flip-flop 43c is connected to the input terminal of the measurement switch SW3. Yes. The flip-flops 43c in the n column hold the input level from the level shifter 48 as the output level every time the latch pulse signal LP that is a clock signal rises.

The AND circuit 43b in the j-th column includes a first input terminal to which the latch pulse signal LP is input and a second input terminal connected to the output terminal of the measurement switch SW3 in the j-th column. The output terminal of the AND circuit 43b in the jth column is connected to the input terminal of the data latch 43a, and the output level of the AND circuit 43b in the jth column is used as a control level for causing the data latch 43a to hold data. .

When the measurement switch SW3 in the j-th column is in an off state, the second input terminal in the AND circuit 43b in the j-th column is set to a high level, and the j-th column logic is input every time the latch pulse signal LP is input. The product circuit 43b logically outputs a high level.

For example, when the measurement switch SW3 in the j-th column is in the OFF state and the latch pulse signal LP is input to the AND circuit 43b, the j-th AND circuit 43b performs the j-th column data latch. The gradation value Din is held in 43 a and the data latch 43 a in the j-th column outputs the held gradation value Din to the DAC 44. Further, for example, when the measurement switch SW3 in the p-th column is in an off state and the latch pulse signal LP is input to the AND circuit 43b, the AND circuit 43b in the p-th column The data held in the latch 43a is held in the data latch 43a in the p-th column.

When the measurement switch SW3 in the j-th column is on and the output level of the flip-flop 43c in the j-th column is high, the AND circuit in the j-th column is input for each input of the latch pulse signal LP. 43b logically outputs a high level.

For example, when the measurement switch SW3 in the j-th column is in an on state and the reference level is higher than the convergence level Vs, the AND circuit 43b in the j-th column receives every input of the latch pulse signal LP. The count value is held in the data latch 43a. At this time, the voltage level output from the DAC 44 in the j-th column drops every time the up-counter 47 counts up. Therefore, the data latch 43a is input every time the latch pulse signal LP is input until the reference level falls below the convergence level Vs. Continue to update the count value.

When the measurement switch SW3 in the j-th column is in an ON state and the output level of the flip-flop 43c in the j-th column is at a low level, the AND circuit in the j-th column is input every time the latch pulse signal LP is input. 43b logically outputs a low level.

For example, when the measurement switch SW3 in the j-th column is on and the reference level is lower than the convergence level Vs, the j-th AND circuit 43b receives the latch pulse signal LP. Regardless, the count value is not held in the data latch 43a.

After all, since the reference level output from the DAC 44 in the j-th column drops every time the up counter 47 counts up, the data latch 43a keeps the count held by the data latch 43a until the reference level falls below the convergence level Vs. Continue to update the value. When the reference level falls below the convergence level Vs, the data latch 43a stops holding the count value for each latch pulse signal LP. As a result, the count value finally held by the data latch 43a in one measurement period has a difference from the convergence level Vs in the measurement period within the resolution Vcnt, and generates a reference level exceeding the convergence level Vs. It is a value for. In addition, the count value that is finally held by the data latch 43a in one measurement period corresponds to a value that generates a reference level closest to the convergence level Vs among all reference levels. The data latch 43a in the j-th column holds such a count value as the convergence voltage measurement data Dout in the j-th column.

It should be noted that the gradation value Din and the count value are digital values held in the data latch 43a common to these, and are digital values having an input range equal to each other. The least significant bit of the gradation value Din is the least significant bit of the count value, and the most significant bit of the gradation value Din is the most significant bit of the count value. For example, the gradation value level Vdata when the gradation value Din is “1” and the reference level when the count value is “1” are equal to each other, and the gradation value Din is “2”. The gradation value level Vdata at a certain time and the reference level when the count value is “2” are also equal to each other.

[Configuration of system controller 50]
The configuration of the system controller 50 will be described with reference to FIG.
As shown in FIG. 11, the system controller 50 includes an input signal processing unit 51, a timing controller 52, a correction processing unit 53, a data processing unit 54, a monitoring unit 55, and a period determination unit 56.

The input signal processing unit 51 generates a gradation component Dsig that is a gradation component for each pixel circuit PCC from the video signal that is the input signal SIG, and inputs the gradation component Dsig to the correction processing unit 53. The input signal processing unit 51 generates a reference clock for controlling the driving timing for each pixel circuit PCC from the input signal SIG and inputs the reference clock to the timing controller 52.

The timing controller 52 generates a selection start pulse signal SP, a selection mask pulse signal MP1, a power supply mask pulse signal MP2, a data start pulse signal SP1, and a latch pulse signal LP based on the reference clock input from the input signal processing unit 51. . The timing controller 52 inputs the selection start pulse signal SP and the selection mask pulse signal MP1 to the selection driver 20 and inputs the selection start pulse signal SP and the power supply mask pulse signal MP2 to the power supply driver 30. The timing controller 52 inputs the data start pulse signal SP1 and the latch pulse signal LP to the data driver 40.

The timing controller 52 generates a drive shift clock Clks, a measurement shift clock Clkr, and a data shift clock Clkd. The timing controller 52 inputs the drive shift clock Clks to the selection driver 20 and the power supply driver 30, inputs the measurement shift clock Clkr to the selection driver 20 and the power supply driver 30, and uses the data shift clock Clkd as the data driver. To enter.

The timing controller 52 outputs the data start pulse signal SP1, the data shift clock Clkd, and the latch pulse signal LP to the data driver 40 when the correction processing unit 53 outputs the gradation value Din for one row to the data driver 40. input. The timing controller 52 inputs the data shift clock Clkd and the latch pulse signal LP to the data driver 40 when the data driver 40 generates the measurement data Dout. The timing controller 52 inputs the latch pulse signal LP to the data driver 40 when the correction processing unit 53 inputs the measurement data Dout for one row from the data driver 40.
The correction processing unit 53 includes a reference gradation generation unit 53A, a correction amount addition unit 53B that is an adder, and a correction amount calculation unit 53C.

The reference gradation generation unit 53A includes a lookup table for performing various adjustments on the gradation component Dsig input to the correction processing unit 53, and performs gamma correction on the gradation component Dsig for each pixel PX. Various adjustments such as initial brightness adjustment and chromaticity adjustment are performed. The reference gradation generation unit 53A inputs the reference gradation value Db for each pixel PX, which is the adjusted gradation, to the correction amount addition unit 53B.

The correction amount adding unit 53B adds the threshold correction amount k for the pixel PX located in the i row and j column to the reference gradation value Db generated for the pixel PX located in the i row and j column. The correction amount adding unit 53B outputs a new gradation value as a result of the addition as the gradation value Din for the pixel PX located in the i row and j column. The gradation value Din is a new gradation value that takes into account the threshold voltage Vth for each pixel PX as a gradation value, and is a gradation value for each pixel PX.

The correction amount calculation unit 53C extracts the measurement data Dout of the pixel PX located in i rows and j columns from the measurement data Dout of the plurality of pixels PX, and the i-th row is extracted from the measurement data Dout extracted by the correction amount calculation unit 53C. A threshold value correction amount k for the pixel PX located in the j column is calculated. When the reference gradation value Db generated for the pixel PX located in the i row and j column is input to the correction amount adding unit 53B, the correction amount calculating unit 53C performs the correction for the pixel PX located in the i row and j column. The threshold value correction amount k is input to the correction amount adding unit 53B.

Note that when the voltage for each bit indicated by the measurement data Dout when measuring the convergence voltage and the voltage for each bit indicated by the gradation value Din when generating the gradation value level Vdata are equal to each other, the correction amount calculation unit 53C Handles the measurement data Dout extracted by the correction amount calculation unit 53C as the threshold correction amount k. On the other hand, when the voltage for each bit indicated by the measurement data Dout as the convergence voltage and the voltage for each bit indicated by the gradation value Din as the gradation value level Vdata are different from each other, the correction amount calculation unit 53C The measurement data Dout extracted by the correction amount calculation unit 53C is converted into a threshold correction amount k so that the two voltage levels are matched.

The data processing unit 54 includes a storage area of m rows × n columns, which is a storage area for each pixel PX. Each time a new measurement operation is performed in one pixel row, n columns of measurement data Dout obtained by the measurement operation are input from the data driver 40 to the data processing unit 54. The data processing unit 54 stores the n columns of measurement data Dout input from the data driver 40 in a storage area in association with the pixel PX on which the current measurement operation is performed. For example, when the pixel row on which the current measurement operation is performed is the first row, the data processing unit 54 stores the measurement data Dout in each of the n columns of storage areas associated with the pixels PX in the first row. Remember.

The data processing unit 54 updates the measurement data Dout associated with the i-th row every time the measurement data Dout of the pixel PX located in the i-th row is input. The data processing unit 54 outputs the measurement data Dout to the monitoring unit 55 for each pixel row from the storage area of m rows × n columns.

The monitoring unit 55 includes m storage areas that are storage areas for each pixel row. The monitoring unit 55 extracts the largest measurement data Dout from the measurement data Dout in the i-th pixel row, and handles the measurement data Dout extracted by the monitoring unit 55 as the current maximum value data Dmax in the i-th row.

For example, when the measurement data Dout of the first row and the first column is the largest among the measurement data Dout of the first pixel row, the monitoring unit 55 uses the measurement data Dout of the first row and the first column as one row by the current measurement. The maximum eye value data Dmax is handled. When the measurement data Dout of the second row and the fourth column is the largest among the measurement data Dout of the second pixel row, the monitoring unit 55 uses the measurement data Dout of the second row and the fourth column as two rows by the current measurement. The maximum eye value data Dmax is handled.

The monitoring unit 55 compares the maximum value data Dmax of the i-th row from the current measurement with the maximum value data Dmax of the i-th row from the previous measurement. Then, when the maximum value data Dmax of the i-th row by the current measurement is equal to or less than the maximum value data Dmax of the i-th row by the previous measurement, the maximum value data Dmax of the i-th row by the previous measurement is changed to the i-th row. The monitoring unit 55 stores the new maximum value data Dmax. On the other hand, when the maximum value data Dmax of the i-th row by the current measurement is larger than the maximum value data Dmax of the i-th row by the previous measurement, the maximum value data Dmax of the i-th row by the current measurement is changed to the i-th row. The monitoring unit 55 stores the new maximum value data Dmax.

For example, when the maximum value data Dmax in the first row by the current measurement is obtained from the pixel PX in the first row and the first column, the measurement data Dout obtained from the pixel PX in the first row and the first column is up to the previous time. Is compared with the maximum value data Dmax in the first row. When the maximum value data Dmax on the first line obtained by the current measurement is larger than the maximum value data Dmax on the first line obtained by the previous measurement, the maximum value data Dmax on the first line obtained by the current measurement is the first line. Is stored as new maximum value data Dmax.

The monitoring unit 55 grasps the pixel row for which the next measurement period is set, and extracts the maximum value data Dmax associated with the pixel row from the storage area. When the next measurement period is set, the monitoring unit 55 inputs the maximum value data Dmax extracted from the storage area to the period determination unit 56.

For example, when the pixel row for which the next measurement period is set is the first pixel row, the monitoring unit 55 extracts the maximum value data Dmax in the first row. When the measurement period is set in the first pixel row, the monitoring unit 55 inputs the maximum value data Dmax in the first row to the period determining unit 56 which is an example of a setting unit.

The period determination unit 56 determines the number N of transmissions of the data shift clock Clkd based on the maximum value data Dmax input from the monitoring unit 55. The number N of transmissions determined by the period determination unit 56 is a value having linearity with respect to the maximum value data Dmax, and increases as the maximum value data Dmax input from the monitoring unit 55 increases. The number N of transmissions determined by the period determination unit 56 is a value that determines the maximum value of the count value in the up-counter 47 for each measurement period, and is a parameter that determines the voltage level that is the lowest among the reference levels described above. is there.

Here, the maximum value data Dmax input from the monitoring unit 55 is a count for generating a reference level whose difference from the convergence level Vs by the previous measurement is within the resolution Vcnt and exceeding the convergence level Vs. Value. Further, the maximum value data Dmax input from the monitoring unit 55 is a count value for generating a reference level closest to the minimum value of the convergence level Vs obtained by the previous measurement among all reference levels.
The number N of transmissions determined by the period determination unit 56 is a digital value for changing the reference level every time the data shift clock Clkd is transmitted. Then, based on the maximum value data Dmax input from the monitoring unit 55 so that the reference level that changes by one step every time the data shift clock Clkd is sent passes through the minimum value of the convergence level Vs measured up to this time. The period determination unit 56 determines the number N of transmissions this time. Further, it is estimated that the threshold voltage Vth changes by an estimated value between the previous measurement period and the current measurement period, and the period is determined so that the current count value is higher than the previous value by the estimated value. The unit 56 determines the number N of transmissions this time.

For example, the period determining unit 56 presets an estimated value of the shift amount ΔVth between the previous measurement period and the current measurement period. The estimated value of the shift amount ΔVth may be a constant value based on, for example, a cumulative driving amount in the driving transistor T1 until the current measurement period, or may be a fluctuation value. In addition, the period determination unit 56 presets the association between the maximum value data Dmax and the number of transmissions N. At this time, the period determination unit 56 sets the association between the maximum value data Dmax and the number N of transmissions so that the reference level based on the current number N of transmissions passes the convergence level Vs up to the previous time.

Then, the period determining unit 56 adds the estimated value of the shift amount ΔVth to the maximum value data Dmax input from the monitoring unit 55, and uses the result of the addition as the estimated value of the current maximum value data Dmax. Next, the period determination unit 56 applies the estimated value of the current maximum value data Dmax to the relationship between the maximum value data Dmax and the number of transmissions N, and transmits the number of transmissions N corresponding to the estimated value of the current maximum value data Dmax. To decide. As a result, the period determining unit 56 determines the number N of transmissions so that the step-by-step reference level passes through the previous convergence level Vs.

If the number of times of transmission N is determined in this way, the reference level in the current measurement period is stepped down to a range in which the minimum value of the convergence level Vs from the previous measurement can be measured, and the convergence level Vs. It is difficult to step down to a voltage level that is not necessary for the measurement. The period determination unit 56 inputs the current number of transmissions N thus determined to the timing controller 52. Each time the data shift clock Clkd is transmitted from the timing controller 52, the above-described reference level decreases stepwise, and the above-described reference level is maintained until the number of times the data shift clock Clkd is transmitted reaches the number N of transmissions. It keeps falling.

The period determination unit 56 further determines the extension period te of this time from the number N of transmissions determined this time. The extension period te determined by the period determination unit 56 is a shorter period as the number of transmissions N is larger, and is a value having linearity with respect to the number of transmissions N. The extension period te determined by the period determination unit 56 is a period for extending the setting of the light emission period, and the closer the convergence voltage in the measurement period is to the analog reference voltage DVSS, that is, the threshold voltage Vth is smaller. In addition, the shorter the period required for measuring the convergence voltage, the longer.

As shown in FIG. 12, the timing controller 52 generates the selection start pulse signal SP when setting the light emission period based on the reference clock input from the input signal processing unit 51. The timing controller 52 inputs the selection start pulse signal SP generated by the timing controller 52 to the selection driver 20 and the power supply driver 30 as the light emission period start signal SPa, and emits light to the selection driver 20 and the power supply driver 30. Start the period. The timing controller 52 counts the time that has elapsed since the input of the selection start pulse signal SP generated at the start of the light emission period.

The timing controller 52 generates a selection start pulse signal SP when setting a non-light emission period following the light emission period, and uses the generated selection start pulse signal SP as a non-light emission period start signal SPb. Input to the driver 30. At this time, the timing controller 52 delays the output of the selection start pulse signal SP by the extension period te after the elapse of the reference period tb, which is the reference time during which the light emission period and the non-light emission period are performed. That is, the timing controller 52 sets the period during which the light emission period is performed as the corrected light emission period tp that is longer than the reference period tb by the extension period te.

Note that the reference period tb in the timing controller 52 is set so that, for example, the number of drive shift clocks Clks sent in the reference period tb is equal to the number of selection lines Ls. Further, when the light emission period and the non-light emission period are set, the timing controller 52 inputs the drive shift clock Clks to the selection driver 20 and the power supply driver 30.

The timing controller 52 generates a selection start pulse signal SP when setting a measurement period subsequent to the non-light emission period, and uses the selection start pulse signal SP generated by the timing controller 52 as the measurement period start signal SPc. , Input to the power supply driver 30. At this time, the timing controller 52 inputs the measurement period start signal SPc and the measurement shift clock Clkr when the reference period tb has elapsed from the non-light emission period start signal SPb.

Here, the timing controller 52 changes the period in which the voltage level of the selection mask pulse signal MP1 is logically low for each row number in which the measurement period is set. That is, the timing controller 52 sets the voltage level of the selection mask pulse signal MP1 to the low level for the first non-selection period tma, and then sets the voltage level of the selection mask pulse signal MP1 to the high level for the measurement selection period tmb. Then, the low level is set again for the second non-selection period tmc to the voltage level of the selection mask pulse signal MP1.

For example, when the setting target of the measurement period is the q-th row, the period required to send the measurement shift clock Clkr q times is the first non-selection period tma, and the measurement shift clock Clkr is sent mq times. The period required for is the second non-selection period tmc. The period required for setting the measurement level VM to the voltage level of the data line Ld and converging the voltage level of the data line Ld by the relaxation time ts is the measurement selection period tmb, which is set in advance. It is a period of a certain length.

When the selection mask pulse signal MP1 is input to the selection driver 20 and the power supply driver 30 together with the measurement shift clock Clkr, the selection of the selection line Ls is skipped from the first line to the qth line, and the selection of the power supply line La is selected. Is also skipped from line 1 to line q. Note that the timing controller 52 changes the pixel row to be set for the measurement period one row at a time in the row number order along the column direction at every opportunity for setting the measurement period.

The timing controller 52 sets a period during which the voltage level of the power supply mask pulse signal MP2 is logically low. At this time, the timing controller 52 continues to set the voltage level of the power supply mask pulse signal MP2 to a logical low level throughout the first non-selection period tma, the measurement selection period tmb, and the measurement selection period tmb.

Further, the timing controller 52 generates a data shift clock Clkd for generating a reference level and a latch pulse signal LP, and inputs them according to the number N of transmissions input from the period determining unit 56. Then, the timing controller 52 sends out the data shift clock Clkd and the latch pulse signal LP as many times as N.

The timing controller 52 outputs the light emission period start signal SPa, the non-light emission period start signal SPb, and the measurement period start signal SPc in this order, and every time the selection start pulse signal SP is generated three times, the cycle of the shift clock signal is changed. The drive shift clock cycle is changed to the measurement shift clock cycle. By such a change in the cycle of the shift clock signal, the selection line Ls and the power supply line La are selected row by row in order of the drive shift clock cycle, and selection for m rows is repeated twice. Each time selection for m rows is repeated twice, a measurement period is set for the selection line Ls of the qth row.

[Light emission period and non-light emission period]
With reference to FIG. 13, the transition of the voltage level of each signal input to the selection line Ls, the power supply line La, the data line Ld, and the data driver 40 in the light emission period and the non-light emission period will be described. The light emission operation and the non-light emission operation are the same in other transitions while the voltage level of the data signal Vd input to the data line Ld is different from each other.

As shown in the lower side of FIG. 13, in the light emission period and the non-light emission period, the measurement switch SW3, the measurement voltage switch SWs, and the transfer switch SWtrs are continuously set to the off state. Further, the output switch SW2 continues to be set to a DAC connection state for connecting the j-th column data latch 43a and the j-th column DAC 44, and the input switch SW1 is connected to the j-th column data latch 43a and the j-th column. The data register connection state for connecting the second data register 42 continues to be set.

First, at the timing td1, the display switch SWd is turned on, and the buffer 45 starts to function as an amplifier connected with negative feedback. The shift register 41, the data register 42, the data latch 43a, the level shifter 46, the DAC 44, the buffer 45, and the data line Ld are connected in series.

Next, the data start pulse signal SP 1 is input to the data driver 40, and the shift signal is input from the shift register 41 to the data register 42. As a result, the gradation value Din in the first row is taken into the data register 42 from the system controller 50.

At timing td2, the voltage level of the selection line Ls in the first row is set to the high level H, and the write level WDVSS is set as the power supply signal Va of the power supply line La in the first row. As a result, the selection transistor T3 in the first row and the holding transistor T2 in the first row shift from the off state to the on state, and the driving transistor T1 in the first row can be driven in the saturation region.

At this time, the latch pulse signal LP is input to the data driver 40, and the gradation value Din of the first row is held in the n-column data latch 43a all at once. The gradation value Din of the first row held in the n-column data latch 43a is converted into an analog value through the n-column level shifter 46 and the n-column DAC 44, and the converted analog value is converted into the gradation value level Vdata. To the data line Ld. The gate-source voltage Vgs of the driving transistor T1 in the first row is held in the holding capacitor Cs as a voltage corresponding to the difference between the write level WDVSS and the gradation value level Vdata.

This completes the writing operation in the pixel PX in the first row. The gradation value level Vdata set for the data line Ld in the first row and j column is obtained from the pixel PX in the first row and j column with respect to the reference gradation value Db in the first row and j column. The correction by the threshold value correction amount k is added.

During this time, the data start pulse signal SP1 is output to the data driver 40 again, and the shift signal is input from the shift register 41 to the data register 42. As a result, the gradation value Din in the second row is taken from the system controller 50 into the data register 42.

At timing td3, the voltage level of the selection line Ls in the first row is set to the low level L, and the voltage level of the power supply line La in the first row is set to the light emission level ELVDD. As a result, the selection transistor T3 in the first row and the holding transistor T2 in the first row transition from the on state to the off state. Then, the driving transistor T1 in the first row generates the drain-source current Ids corresponding to the difference between the voltage held in the holding capacitor Cs in the first row and the threshold voltage Vth of the driving transistor T1 in the EL element OEL. Shed.

At this time, the gradation value level Vdata set as the data signal Vd of the data line Ld is a voltage level in which the variation of the threshold voltage Vth in the drive transistor T1 is corrected. Therefore, the drain-source current Ids flowing through the EL element OEL is also corrected for the variation of the threshold voltage Vth. As a result, the pixels PX in the first row perform a light emission operation.

At this time, the voltage level of the selection line Ls in the second row is set to the high level H, and the voltage level of the power supply line La in the second row is set to the write level WDVSS. The selection transistor T3 and the holding transistor T2 in the second row are turned on. Further, the latch pulse signal LP is output again to the data driver 40, whereby the gradation value Din of the second row is held in the n-th column data latch 43a. The gradation value Din of the second row held in the n-column data latch 43a is converted into an analog signal voltage through the level shifter 46 and the DAC 44, and is set as the gradation value level Vdata of the n-column to the data line Ld. .

The gate-source voltage Vgs of the driving transistor T1 in the second row is held in the holding capacitor Cs as a voltage corresponding to the difference between the write level WDVSS and the gradation value level Vdata. As a result, the driving transistors T1 in the second row can be driven in the saturation region, and the writing operation in the light emission period in the pixels PX in the second row is completed. The gradation value level Vdata set for the data line Ld in the second row and j column is a threshold value correction obtained from the pixel PX in the second row and j column with respect to the reference gradation value Db in the second row and j column. The correction by the amount k is taken into account.

Such a writing operation and a light emitting operation are performed in the order of row numbers one row at a time, and these operations are performed from the first row to the nth row by a drive shift clock cycle. As a result, an image is displayed as one frame. In the non-light emission operation, the gradation value level Vdata in the writing operation and the light emission operation is changed to a voltage level corresponding to the lowest gradation value.

[Measurement period]
With reference to FIG. 14, the transition of the voltage level of each signal input to the selection line Ls, the power supply line La, the data line Ld, and the data driver 40 in the measurement period will be described.

As shown in the lower side of FIG. 14, the voltage level of the power line La in the q-th row is set to the write level WDVSS during the writing operation and the measurement operation in the q-th pixel PX. to continue. Further, the display switch SWd continues to be set in the OFF state, and the data line Ld continues to be disconnected from the shift register 41 and the data register 42 in the data driver 40. The non-inverting input terminal of the buffer 45 continues to be set to the output level of the DAC 44, and the inverting input terminal of the buffer 45 continues to be set to the voltage level of the data line Ld. It continues to function as a comparator that compares the voltage level of the data line Ld, that is, compares the reference voltage and the convergence voltage.

First, at the timing t1, the transfer switch SWtrs is set to an off state. From this state, the voltage level of the selection line Ls in the q-th row is set to the high level H, and the holding transistor T2 in the q-th row and the selection transistor T3 in the q-th row are turned on. Then, the measurement voltage switch SWs is turned on, and the data signal Vd of each of the n columns of data lines Ld is set to the measurement level VM.

The input terminal of the input switch SW1 is a counter connection connected to the output terminal of the up counter 47. The output switch SW2 connects the data latch 43a and the level shifter 46.

At this time, the measurement level VM is set so that the gate-source voltage Vgs of the drive transistor T1 is larger than the threshold voltage Vth. When such a measurement level VM is set as the voltage level of each of the n columns of data lines Ld, the drain-source current Ids based on the difference between the measurement level VM and the write level WDVSS becomes the q-th drive transistor T1. And the q-th row selection transistor T3. Accordingly, the holding capacitor Cs in the q-th row holds a voltage exceeding the threshold voltage Vth as the gate-source voltage Vgs of the driving transistor T1. Thereby, the pixel PX in the q-th row finishes the writing operation in the measurement period.

At timing t2, the voltage level of the selection line Ls in the q-th row continues to be set to the high level H, while the measurement voltage switch SWs is switched to the off state. As a result, each of the n columns of data lines Ld is set to a high impedance state.

At this time, since the gate-source voltage Vgs in the driving transistor T1 in the q-th row is held in the storage capacitor Cs, the source level in the driving transistor T1 in the q-th row is the drain level of the driving transistor T1 in the i-th row. So that the drain-source current Ids flows in the driving transistor T1 in the q-th row.

Then, as time elapses from the timing t2, the charge accumulated in the storage capacitor Cs in the q-th row is discharged, and the gate-source voltage Vgs in the driving transistor T1 in the q-th row is the drain-source current. It decreases until Ids almost stops flowing. As a result, when the relaxation time ts has elapsed from the timing t2, the voltage level of the data line Ld converges to the convergence level Vs, and the convergence level Vs is taken into the inverting input terminal of the buffer 45.

On the other hand, the period determining unit 56 refers to the maximum value data Dmax of the pixel row in which the current measurement period is set, from the maximum value data Dmax stored in the monitoring unit 55, and the data shift clock Clkd, And the number N of times of sending the latch pulse signal LP is determined. As described above, if the number of transmissions N is determined by the period determination unit 56, the reference level in the current measurement period is stepped down to a range in which the convergence level Vs in the previous measurement period can be measured, and It is difficult to step down to a voltage level that is unnecessary for the measurement of the convergence level Vs. In other words, the reference maximum value in the current measurement period increases to a level at which the convergence voltage can be measured in the previous measurement period, but it is difficult to increase the reference maximum value in a size unnecessary for the measurement of the convergence voltage.

Further, the period determining unit 56 determines the extension period te of this time from the determined number N of transmissions. As described above, the extension period te determined by the period determination unit 56 is a period for extending the setting of the light emission period, and has a small threshold voltage Vth and a period required for measuring the convergence level Vs. The shorter, the longer.

At timing t3, the voltage level of the selection line Ls in the q-th row is set to the low level L, and the holding transistor T2 in the q-th row and the selection transistor T3 in the q-th row are switched to the off state. Further, the measurement switch SW3 is turned on.

At this time, the data shift clock Clkd is input to the up counter 47, and the latch pulse signal LP is input to the data latch 43a and the AND circuit 43b. The count value, which is the output value of the up counter 47, is input to the level shifter 46 through the input switch SW1 and the data latch 43a. The level shifter 46 amplifies the voltage level of the count value in the same manner as the amplification with respect to the gradation value Din. Similarly to the generation of the gradation value level Vdata, the DAC 44 converts the digital value amplified by the level shifter 46 into an analog value, and inputs the reference level as a conversion result to the non-inverting input terminal of the buffer 45.

Here, when the reference level output from the DAC 44 is higher than the convergence level Vs, the voltage level output from the buffer 45 is high. On the other hand, when the reference level output from the DAC 44 is lower than the convergence level Vs, the voltage level output from the buffer 45 is low. As a result, when the reference level output by the DAC 44 is between the write level WDVSS and the convergence level Vs, the output level of the buffer 45 is high. On the other hand, when the reference level output from the DAC 44 is lower than the convergence level Vs, the output level of the buffer 45 is low.

The result of the comparison between the reference level and the convergence level Vs is held in the flip-flop 43c for each input of the latch pulse signal LP and input to the AND circuit 43b. When the output level of the AND circuit 43b in the j-th column is logically high, that is, the reference level output from the DAC 44 in the j-th column is between the write level WDVSS and the convergence level Vs. At this time, the data latch 43a in the j-th column updates the count value of the up counter 47. On the other hand, when the reference level output from the DAC 44 in the j-th column is lower than the convergence level Vs, the data latch 43a in the j-th column does not update the count value of the up counter 47.

As a result, when the reference level is higher than the convergence level Vs and closest to the convergence level Vs, the data latch 43a in the j-th column finally holds the count value for generating such a reference level. The count value finally held by the data latch 43a in the j-th column is handled as the measurement data Dout in the j-th column during this measurement period.

For example, when the reference level when the count value is “3” is higher than the convergence level Vs of the first column and closest to the convergence level Vs of the first column, this reference level is generated. The data latch 43a in the first column finally holds “3” that is the count value to be stored. On the other hand, when the reference level when the count value is “5” is higher than the convergence level Vs of the second column and is closest to the convergence level Vs of the second column, this reference. The data latch 43a in the second column finally holds “5” which is a count value for generating the level. The data latch 43a in the first column stores “3” as the measurement data Dout in the first column in this measurement period, and the data latch 43a in the second column stores the measurement data Dout in the second column in this measurement period. Is stored as “5”.

The count value for setting such a reference level, that is, the number of transmissions N, is the number of times that it is sufficient if the reference level that falls stepwise falls below each of the n columns of convergence levels Vs. The number N of times of transmission is the number of times that the reference level that falls stepwise does not need to be significantly lower than the convergence level Vs of the n columns. In this regard, the period determination unit 56 described above refers to the maximum value data Dmax of the pixel row in which the current measurement period is set and the estimated value of the shift amount ΔVth, and the data shift clock Clkd and the latch pulse The number N of transmissions of the signal LP is determined. Therefore, if the number of transmissions N is determined by the period determination unit 56, the reference level in the current measurement period is stepped down to a range where the convergence level Vs in the previous measurement period can be measured and converged. It becomes difficult to step down to a voltage level that is unnecessary for the measurement of the level Vs.

At timing t4, the input switch SW1 in the p-th column and the output terminal of the output switch SW2 in the (p + 1) -th column are switched to a data latch series connection. The measurement switch SW3 is switched to an OFF state, and each of the n-column AND circuits 43b is switched to a state in which a logical high level is output for each input of the latch pulse signal LP. Further, the transfer switch SWtrs is turned on. Then, the latch pulse signal LP is input from the timing controller 52 to the data driver 40, and the measurement data Dout for each column held in each of the n column data latches 43a is synchronized with the input of the latch pulse signal LP. The data is transferred to the system controller 50 in the order of the column numbers. In FIG. 14, the number of times the latch pulse signal LP is repeated is omitted for convenience of explanation.

At timing t5, the transfer switch SWtrs is switched to the off state. The input switch SW1 connects the input terminal of the data latch 43a to the register in the data register 42, thereby ending the measurement period.

[Operation sequence]
The timing of the measurement period set in one frame period will be described with reference to FIGS. An example in which the pixels PX are arranged in 540 rows × 960 columns and the frame rate is 60 fps will be described. FIG. 15 shows the timing of the measurement period in the black display operation executed in the first frame, and FIG. 16 shows the timing of the measurement period in the black display operation executed in the second frame. Reference numeral 17 denotes the timing of the measurement period in the black display operation executed in the 540th frame.

As shown in FIG. 15, first, at a timing Tf1a, a writing operation in which a light emission period is set in each pixel PX in the first row and the gradation value level Vdata is set in the data line Ld is performed in each pixel in the first row. Start at PX. When the writing operation is finished in each pixel PX in the first row, a display operation based on the gradation value level Vdata is started in each pixel PX in the first row, and the light emission period is set in each pixel PX in the second row. The writing operation for setting the gradation value level Vdata is started in each pixel PX in the second row. Thus, the writing operation based on the gradation value Din is started in the order of row numbers from the first row to the 540th row in the selected shift clock cycle, and the display operation is started in order from the row where the writing operation is completed.

At timing Tf1b, the writing operation for setting the gradation value level Vdata to the data line Ld is completed up to the 540th row, which is the last row, and the length of the light emission period in the pixel PX on the first row is the reference level. Reaches the reference period tb. Then, the length of the period elapsed from the reference period tb is counted in order of the row numbers from the pixel PX in the first row, and the length of the period elapsed from the reference period tb reaches the extension period te. The display extension operation to extend the setting is continued.

At this time, the target row in which the subsequent measurement period is set is the first pixel row, and the current extended period te common to all the pixel rows is the first pixel row in the current measurement. It is determined from the number of transmissions N set in. The extension period te common to all the pixel rows is a shorter period as the number N of transmissions for the first pixel row is larger.

At the timing Tf1c, the length of the period elapsed from the reference period tb reaches the extension period te in the pixels PX in the first row, and the non-light emission period is set in each pixel PX in the first row. Then, a writing operation for displaying black is started in each pixel PX in the first row. When the writing operation for displaying black is finished in each pixel PX in the first row, a non-light emission operation is started in each pixel PX in the first row as a display operation for displaying black. A non-emission period is set for each pixel PX, and a writing operation for displaying black is started at each pixel PX in the second row. Thus, the writing operation for displaying black is started from the first row to the 540th row in the order of the row numbers in the selected shift clock cycle, and the black display operation is started in order from the row where the writing operation is completed. .

At the timing Tf1d, the writing operation for displaying black is completed up to the 540th line which is the last line, and the selection line Ls set to the high level H is lined up from the first line to the 540th line. Shifted by the measurement shift clock period in numerical order. At this time, first, the first line is set as a candidate for the selection line Ls for which the high level H is set, that is, the target line for measuring the convergence voltage, which is a characteristic value, and is set in each pixel PX in the first line. On the other hand, a measurement period is set. At this time, the transmission count N for the first pixel row is a value obtained from the maximum value data Dmax corresponding to the first pixel row for which the current measurement period is set. The reference level set this time for the first pixel row is a range in which the convergence level Vs obtained for the first pixel row can be measured and is converged. It is a value that is difficult to step down to a voltage level that is unnecessary for the measurement of the level Vs.

Thereby, the measurement data Dout relating to each drive transistor T1 in the first row is taken into the data processing unit 54 of the system controller 50 in the order of the column numbers. When the measurement operation for each pixel PX in the first row is completed, the selection line Ls candidates for which the high level H is set are shifted from the second row to the 540th row by the measurement shift clock cycle in the row number order. On the other hand, due to the output of the selection mask pulse signal MP1 and the power supply mask pulse signal MP2, the low level L is continuously set to all the selection lines Ls, and all the pixels PX continue to display black.

At timing Tf2a, the candidate shift based on the measurement shift clock cycle proceeds to the 540th row, which is the final row, and the writing operation for setting the gradation value level Vdata is started again for each pixel PX in the first row. The

As shown in FIG. 16, at the timing Tf2a, the writing operation for setting the gradation value level Vdata is started again in the order of the row numbers from the first row to the 540th row, and the gradation value level Vdata is set to the data line Ld. The light emission period is set in order from the row where the writing operation is completed.

At timing Tf2b, the writing operation for setting the gradation value level Vdata to the data line Ld is completed up to the 540th row, which is the last row, and the display extending operation for extending the setting of the light emission period is started. At this time, the target row in which the subsequent measurement period is set is the second pixel row, and the current extended period te common to all the pixel rows is the second pixel row in the current measurement. It is determined from the number of transmissions N set in. The current extended period te common to all the pixel rows is a shorter period as the number N of times of transmission for the second pixel row is larger.

At timing Tf2c, the display extension operation for extending the setting of the light emission period is completed, and then the setting of the non-light emission period for displaying black is advanced from the first line to the 540th line in order of the line number, and black is displayed. The black display operation is started in order from the row in which the writing operation for completing is completed.

At the timing Tf2d, the writing operation for displaying black is finished up to the 540th line, which is the last line, and the selection line Ls for which the high level H is set is changed from the first line to the 540th line number. It is shifted in turn by the measurement shift clock period. At this time, the second row is set as the target row for which the convergence voltage is measured, and the candidate shift based on the measurement shift clock cycle is advanced to the second row. When the selection line Ls candidate for which the high level H is set is in the first row, the selection line Ls in the first row is set to the low level L by the output of the selection mask pulse signal MP1 and the power supply mask pulse signal MP2. Is applied. When the selection line Ls candidate for which the high level H is set is in the second row, a measurement period is set for each pixel PX in the second row.

At this time, the transmission number N for the second pixel row is a value obtained from the maximum value data Dmax corresponding to the second pixel row for which the current measurement period is set. The reference level set this time for the second pixel row is a range in which the convergence level Vs obtained last time for the second pixel row can be measured and is converged. It is a value that is difficult to step down to a voltage level that is unnecessary for the measurement of the level Vs.

Thereby, the measurement data Dout regarding each driving transistor T1 in the second row is taken into the data processing unit 54 of the system controller 50 in the order of the column numbers. When the measurement operation for each pixel PX in the second row is completed, the selection line Ls candidates for which the high level H is set are shifted in order of the row numbers from the third row to the 540th row. At this time, the low level L is continuously set to all the selection lines Ls by the output of the selection mask pulse signal MP1 and the power supply mask pulse signal MP2, and all the pixels PX continue to display black.

At timing Tf3a, the candidate shift based on the measurement shift clock cycle proceeds to the 540th row, which is the final row, and the writing operation for setting the gradation value level Vdata is started again for each pixel PX in the first row. The

As shown in FIG. 17, at the timing Tfma, the writing operation for setting the gradation value level Vdata to the data line Ld is started again in the order of the row numbers from the first row to the 540th row, and the gradation value level Vdata is set to the data line. The light emission period is set in order from the row where the writing operation set to Ld is completed.

At timing Tfmb, the writing operation for setting the gradation value level Vdata to the data line Ld is completed up to the 540th row, which is the last row, and the display extending operation for extending the setting of the light emission period is started. At this time, the target row in which the subsequent measurement period is set is the 540th pixel row, and the current extended period te common to all the pixel rows is the 540th pixel row in the current measurement. It is determined from the number of transmissions N set in. The current extended period te common to all the pixel rows is a shorter period as the number N of times of transmission for the second pixel row is larger.

At the timing Tfmc, the display extension operation for extending the setting of the light emission period is completed, and then the setting of the non-light emission period for displaying black is advanced from the first line to the 540th line in order of line numbers, and black is displayed. The black display operation is started in order from the row in which the writing operation for completing is completed.

At timing Tfmd, the writing operation for displaying black is finished up to the 540th line, which is the last line, and the selection lines Ls set to the high level H are line numbers from the 1st line to the 540th line. It is shifted in turn by the measurement shift clock period. At this time, when the 540th row is set as the target row for which the convergence voltage is measured, and the selection line Ls candidates for which the high level H is set are from the first row to the 539th row, the selection mask pulse signal MP1, Further, the low level L is set to all the selection lines Ls by the output of the power supply mask pulse signal MP2. When the selection line Ls candidate for which the high level H is set is the 540th row, the measurement period is set for each pixel PX on the 540th row. As a result, the measurement data Dout regarding each drive transistor T1 in the 540th row is taken into the data processing unit 54 of the system controller 50 in the order of the row numbers.

Note that the number of transmissions N for the 540th pixel row is also a value obtained from the maximum value data Dmax corresponding to the 540th pixel row for which the current measurement period is set. The reference level set this time for the 540th pixel row is a range in which the convergence level Vs obtained previously for the 540th pixel row can be measured and is converged. It is a value that is difficult to step down to a voltage level that is unnecessary for the measurement of the level Vs.

At timing Tfme, the measurement operation for each pixel PX in the 540th row is completed, and the writing operation for setting the gradation value level Vdata is started again for each pixel PX in the first row.

Thus, after a black display operation is started up to the 540th line in a period in which one frame is displayed, a measurement period is set for a specific pixel line. The pixel rows to be measured are shifted by one row from the first pixel row in the order of row numbers for each frame. That is, when the pixel row in the q-th row (1 ≦ q ≦ 539) performs the measurement operation in the k-th frame (k is an integer of 1 or more), the pixel row in the q + 1-th row performs the measurement operation in the k + 1-th frame. When the target row for which the measurement period is set reaches the last row, the target row for which the measurement period is set returns to the first pixel row.

At this time, when the target row for which the measurement period is set is the q-th row, the data processing unit 54 of the system controller 50 uses the measurement data Dout obtained from each column of the q-th row for each q-th row. The data is stored in the storage area corresponding to the pixel PX. Therefore, the correction processing unit 53 of the system controller 50 calculates the latest measurement data Dout as the measurement data Dout of each pixel PX in the q-th row when calculating the threshold correction amount k in the k + 1 frame, which is the next frame. Can be used. Then, the monitoring unit 55 of the system controller 50 extracts the maximum value data Dmax from the latest measurement data Dout in each pixel PX in the q row, and updates the maximum value data Dmax in the q row. The period determination unit 56 of the system controller 50 determines the number N of transmissions based on the maximum value data Dmax in the q-th row input from the monitoring unit 55 prior to the next measurement for the q-th pixel row. . Each time such a measurement period is repeated 540 times, the system controller 50 updates the measurement data Dout, the maximum value data Dmax, and the number N of transmissions of all the pixel rows.

Referring to FIG. 18, the transition of each control signal during a period in which one frame is displayed will be described in detail. Hereinafter, a case will be described in which the pixel row for which the measurement period is set in the k-th frame is the q-th row.

The selection driver 20 generates a shift signal in accordance with the selection shift clock cycle in response to the input of the selection start pulse signal SP, and sets the high level H to each selection line Ls in synchronization with the shift signal. The selection driver 20 sets the low level L to the selection line Ls in order from the row where the high level H is set.

The power supply driver 30 generates a shift signal in accordance with the selected shift clock cycle in response to the input of the selection start pulse signal SP, and sets the write level WDVSS to each power supply line La in synchronization with the shift signal. Further, the power supply driver 30 sets the light emission level ELVDD to the power supply line La in order from the row in which the write level WDVSS is set.

When the high level H is set to the q-th selection line Ls and the write level WDVSS is set to the q-th power line La, the data line Ld in each pixel circuit PCC in the q-th row is set. Is set to a gradation value level Vdata based on the gradation value Din. Further, when the low level L is set to the selection line Ls of the qth row and the light emission level ELVDD is set to the power supply line La of the qth row, each pixel circuit PCC of the qth row has a gradation value. A drain-source current Ids based on Din is passed through the EL element OEL.

When the writing operation is completed up to the 540th line which is the last line, the selection driver 20 sets the low level L to all the selection lines Ls only for the current extension period te determined from the number N of transmissions in the current measurement. The power supply driver 30 continues to set the light emission level ELVDD for all the power supply lines La. By continuing such setting, the drain-source current Ids further flows to the EL element OEL only for the extended period te.

When the extension period te elapses from the end of the write operation on the 540th row, the selection driver 20 generates a shift signal again in accordance with the selected shift clock period in response to the input of the selection start pulse signal SP, and synchronizes with the shift signal. The high level H is set to the selection line Ls. The selection driver 20 sets the low level L to the selection line Ls in order from the row where the high level H is set.

Further, the power supply driver 30 again generates a shift signal in accordance with the selected shift clock cycle in response to the input of the selection start pulse signal SP, and sets the write level WDVSS to the power supply line La in synchronization with the shift signal. Further, the power supply driver 30 sets the light emission level ELVDD to the power supply line La in order from the row in which the write level WDVSS is set.

When the high level H is set to the q-th selection line Ls and the write level WDVSS is set to the q-th power line La, the data line Ld in each pixel circuit PCC in the q-th row is set. Is set to a gradation value level Vdata based on the lowest gradation value. In addition, when the low level L is applied to the q-th selection line Ls and the light emission level ELVDD is set to the q-th power line La, each pixel circuit PCC in the q-th row has the lowest gradation. The supply of the drain-source current Ids is suppressed based on the value.

When the black display operation is advanced to the 540th line, which is the final line, each of the selection driver 20 and the power supply driver 30 starts shifting according to the measurement shift clock cycle according to the input of the measurement shift clock Clkr. At this time, the selection driver 20 sets the high level H to the selection line Ls of the q-th row in accordance with the input of the selection mask pulse signal MP1. Further, the power supply driver 30 sets the write level WDVSS for all the power supply lines La in response to the input of the power supply mask pulse signal MP2. Then, the measurement of the convergence voltage is started for each pixel PX in the q-th row.

At this time, the system controller 50 sends the data shift clock Clkd and the latch pulse signal LP by the number N of times of transmission in the q row according to the number of times N of transmission of the q row based on the previous measurements. The reference level in the current measurement period is stepped down to a range in which the convergence level Vs in the measurement period in the q row up to the previous measurement can be measured by sending pulses in accordance with the number N of transmissions in the q row. And it becomes difficult to step down to a voltage level unnecessary for the measurement of the current convergence level Vs.

Next, when the measurement data Dout for each pixel PX in the q-th row is output from the data driver 40, each of the selection driver 20 and the power supply driver 30 shifts the measurement shift clock cycle from the timing th to the 540th row. Proceed. When the shift by the measurement shift clock cycle reaches the 540th row, each of the selection driver 20 and the power supply driver 30 starts from the selection line Ls on the first row in accordance with the input of the selection start pulse signal SP. The writing operation for setting the gradation value level Vdata to the data line Ld is started in the order of the row numbers up to the eye selection line Ls.

According to the embodiment, the effects listed below can be obtained.
(1) The maximum value for each pixel row in the measurement data Dout in each pixel row is stored as maximum value data Dmax for each pixel row. The reference maximum value, which is the maximum value of the reference voltage in the current measurement, is the maximum value data Dmax associated with the pixel row to be measured this time, that is, in the measurement before the current measurement. It is set based on the maximum value in the convergence voltage. Therefore, the time required for the successive comparison in the current measurement period is shorter as the maximum value data Dmax is smaller. As a result, the characteristic value of the drive transistor T1 is compared with the configuration in which the maximum value in the reference voltage is a constant value. It is possible to shorten the time required for obtaining the.

(2) The maximum value data Dmax associated with the pixel row to be measured this time is updated every time a measurement period is set for the pixel row to be measured this time. Here, when the temperature of the driving transistor T1 in the previous measurement is significantly lower than the temperature of the driving transistor T1 in the previous measurement, the maximum value of the convergence voltage in the previous measurement is the maximum value of the convergence voltage in the previous measurement. Sometimes it decreases slightly. As described above, even if the maximum value of the convergence voltage in the pixel row to be measured this time does not increase monotonously for each measurement opportunity, the previous configuration of the convergence voltage can be obtained with the above-described configuration. Based on the maximum value, the maximum value among the reference voltages in this measurement is set. Therefore, it is possible to prevent the convergence level Vs from being accurately measured when the maximum value of the reference voltage in the current measurement falls below the convergence voltage.

(3) The smaller the maximum value of the reference voltage in the current measurement, the longer the extension period te prior to the current measurement. Therefore, the shorter the time required for measuring the convergence level Vs, the longer the time required for the EL element OEL to emit light. Becomes longer prior to the measurement. Therefore, it is possible to lengthen the light emission time of the EL element OEL while suppressing a significant change in the sum of the time required to measure the convergence level Vs and the light emission time of the EL element OEL. As a result, a decrease in luminance in one frame can be suppressed.

(4) In the successive comparison between the convergence level Vs and the reference level, the data driver 40 increases the reference voltage from the minimum value by a certain value. Therefore, the time required for the successive comparison in the current measurement is surely shortened by the smaller maximum value of the reference voltage in the current measurement.

(5) The period determination unit 56 predicts that the threshold voltage Vth changes by the estimated value between the previous measurement period and the current measurement period, and the current count value increases by the estimated value. The number of transmissions N is determined. That is, the period determination unit 56 sets a value obtained by adding a constant value to the maximum value of the convergence voltage in the measurement before the current measurement as the maximum value in the reference voltage in the current measurement. Therefore, even if the convergence voltage increases from the measurement before the current measurement, the maximum value of the reference voltage in the current measurement is less than the convergence voltage if the range in which the convergence voltage increases is within a certain value. Therefore, it is possible to prevent the convergence level Vs from being accurately measured.

(6) The correction processing unit 53 extracts the measurement data Dout of the pixel PX located in the i row and j column, and the threshold correction amount k for the pixel PX located in the i row and j column from the extracted measurement data Dout. Is calculated. Then, the correction processing unit 53 adds the threshold correction amount k for the pixel PX located in the i row and j column to the reference gradation value Db generated for the pixel PX located in the i row and j column. Therefore, even if the threshold voltage Vth of the driving transistor T1 varies, the gradation value Din is corrected according to the threshold voltage Vth after the variation, so that it is possible to suppress degradation of the displayed image quality. It becomes.

(7) The black display operation is an operation that is inserted in order to make the display of the moving image clear, and the successive comparison based on the number N of transmissions described above is performed during the period during which the black display operation is performed. Is done. Therefore, the period during which the black display operation is performed is suppressed from being unnecessarily long, and the period during which the black display operation is performed is a period specialized for clearing the video display. It becomes easy to be close to the length.

[Modification]
The above embodiment can be implemented with the following modifications.
[Operation sequence]
The row number of the pixel row for which the measurement period is set may be the same for each frame, or may be random for each frame. Further, two or more row numbers of pixel rows for which a measurement period is set may be set for each frame.

The pixel row in which the measurement period is set includes all the pixels other than the period in which one frame is displayed, such as when the EL display device is activated or when the EL display device suspends display and then returns. It may be a row or a part of pixel rows.

· The row numbers of the pixel rows for which the measurement period is set may be spaced by a fixed value for each frame. For example, the m selection lines Ls are divided into a plurality of selection line groups including ten selection lines Ls adjacent to each other. Then, one selection line group may be set for each frame in the pixel row in which the measurement period is set.

More specifically, as shown in FIG. 19, in the first frame, the writing operation, the display operation, and the display extension operation are performed in the order of the row numbers from the first row. When the writing operation for displaying black is performed up to the last row, a measurement period is set in the first pixel row. Next, in the second frame, similarly to the first frame, the writing operation, the display operation, and the display extension operation are performed in the order of the row numbers from the first row. When the writing operation for displaying black is performed up to the last row, a measurement period is set in the eleventh pixel row. In this way, every time one frame is displayed, the row number of the pixel row for which the measurement period is set is an interval of 10 rows having a constant value from the first pixel row to the 531st pixel row. Set with a gap.

Next, as shown in FIG. 20, in the 55th frame, the writing operation, the display operation, and the display extension operation are performed in the order of the row numbers from the first row. When the writing operation for displaying black is performed up to the last row, the measurement period is set from the first selection line group to the second pixel row. Next, in the 56th frame, as in the 55th frame, the writing operation, the display operation, and the display extension operation are performed in the order of the row numbers from the first row. When the writing operation for displaying black is performed up to the last row, the measurement period is set from the second selection line group to the twelfth pixel row. In this way, every time one frame is displayed, the row number of the pixel row for which the measurement period is set is an interval of 10 rows having a constant value from the second pixel row to the 532th pixel row. Set with a gap.

Next, as shown in FIG. 21, in the 487th frame, the writing operation, the display operation, and the display extension operation are performed in the order of the row numbers from the first row. When the writing operation for displaying black is performed up to the last row, the measurement period is set from the first selection line group to the tenth pixel row. Next, in the 488th frame, similarly to the 487th frame, a writing operation, a display operation, and a display extending operation are performed in the order of the row numbers from the first row. When the writing operation for displaying black is performed up to the last row, the measurement period is set from the second selection line group to the 20th pixel row. In this way, every time one frame is displayed, the row number of the pixel row for which the measurement period is set is an interval of 10 rows having a constant value from the 10th pixel row to the 540th pixel row. Set with a gap. The measurement data Dout for each pixel row is updated once every m frames are displayed.

Here, when the pixel rows in which the measurement period is set are shifted one by one, for example, while 10 frames are displayed, the range of the pixels PX to which the convergence level Vs is measured is 540 pixel rows. It is biased from the 1st line to the 10th line. On the other hand, when the pixel row in which the measurement period is set is shifted by 10 rows as described above, for example, the range of the pixel PX for which the convergence level Vs is measured is displayed while 10 frames are displayed. The pixel lines from the first line to the 100th line are distributed at equal intervals. Therefore, since the range of the pixels PX whose convergence level Vs is measured is dispersed over a wide range, when the threshold voltage Vth varies over a wide range, degradation of displayed image quality can be effectively suppressed.

The m selection lines Ls are partitioned into a plurality of selection line groups each consisting of s selection lines Ls adjacent to each other, and one pixel line for which a measurement period is set is one selection line for each frame. Each group may be set. At this time, the system controller 50 may handle the measurement data Dout for each pixel PX for each pixel group as a representative value for each column to which the pixel PX to be measured belongs.

For example, the m selection lines Ls are divided into a plurality of selection line groups including ten selection lines Ls adjacent to each other. At this time, the data processing unit 54 in the system controller 50 includes a storage area of m / 10 rows × n columns, and associates each of the ten pixels PX arranged in the column direction with one storage area. . That is, in each of the m / 10 selection line groups, the data processing unit 54 associates each of the ten pixels PX arranged in the column direction with one storage area. The data processing unit 54 stores the measurement data Dout for each pixel PX input to the data processing unit 54 in a storage area associated with the pixel PX. Each time the measurement data Dout for each pixel PX is input, the data processing unit 54 updates the measurement data Dout associated with the pixel PX.

Further, the correction amount adding unit 53B adds the threshold correction amount k for the pixel PX located in the i row and j column from the measurement data Dout corresponding to the pixel PX located in the i row and j column. The correction amount adding unit 53B adds the threshold correction amount k for the pixel PX located in the i row and j column to the reference gradation value Db generated for the pixel PX located in the i row and j column. Then, the correction amount adding unit 53B outputs a new gradation value as a result of the addition as the gradation value Din for the pixel PX located in i row and j column.

Further, the monitoring unit 55 includes a storage area of m / 10 rows as a storage area for each pixel group of n columns arranged in the row direction. The monitoring unit 55 extracts the largest measurement data Dout from the measurement data Dout in the i-th pixel row, and uses the extracted measurement data Dout as the maximum value data Dmax of the pixel group to which the i-th pixel row belongs. Treat as.

Also, the period determining unit 56 determines the number N of transmissions for each pixel group based on the maximum value data Dmax input from the monitoring unit 55. The number N of transmissions determined by the period determination unit 56 is a value having linearity with respect to the maximum value data Dmax, and increases as the maximum value data Dmax input from the monitoring unit 55 increases. The number N of transmissions determined by the period determination unit 56 is a value that determines the maximum value of the count value in the up counter 47 for each pixel group.

For example, the data processing unit 54 associates the ten pixels PX located in the first column in the first selection line group with the storage area in the first row and first column, and 2 in the second selection line group. The ten pixels PX located in the column are associated with the storage area in the second row and the second column. In addition, the data processing unit 54 associates the ten pixels PX located in the 959th column in the 54th selection line group with the storage area in the 54th row, the 959th column, and 960 in the 54th selection line group. The ten pixels PX located in the column are associated with the storage area in the 54th row and the 960th column.

Further, for example, the monitoring unit 55 extracts the largest measurement data Dout from the measurement data Dout in the first pixel row, and uses the extracted measurement data Dout as the maximum value data Dmax in the first pixel group. Treat as. The monitoring unit 55 extracts the largest measurement data Dout from the measurement data Dout in the eleventh pixel row, and handles the extracted measurement data Dout as the maximum value data Dmax in the second pixel group. .

Further, for example, the period determining unit 56 determines the number N of transmissions of the first group of pixels based on the maximum value data Dmax in the first group of pixels, and the determined number N of transmissions is determined by the first group. This is applied to the measurement of each of the pixel rows from the first row to the tenth row belonging to. Further, the period determining unit 56 determines the number N of transmissions of the second group of pixels based on the maximum value data Dmax in the second group of pixels, and the determined number of transmissions N belongs to the second group. This is applied to the measurement of each pixel row from the 11th row to the 20th row.

According to such a configuration, the capacity of the storage area for storing the measurement data Dout is suppressed in the data processing unit 54, and the capacity of the storage area for storing the maximum value data Dmax is suppressed in the monitoring unit 55.

Also, the film characteristics of the thin film constituting the driving transistor T1 often dominate the fluctuation amount of the threshold voltage Vth, and the film characteristics of such a thin film are close to each other in adjacent pixel rows. Therefore, in the pixel rows adjacent to each other, the convergence levels Vs are often close to each other. In this regard, according to the configuration described above, in one pixel group, the measurement data Dout of one pixel row is handled as the measurement data Dout of another pixel row. Therefore, when the measurement data Dout is updated for all the pixels PX, the cycle of updating the measurement data Dout is shortened. As a result, when the change in the characteristic value in the drive transistor T1 is large per unit time, the degradation of the displayed image quality is more effectively suppressed.

[Monitoring unit 55]
The maximum value data Dmax associated with the pixel row to be measured this time may be the maximum value of the convergence voltage in the previous measurement performed on the pixel row to be measured this time.

At this time, the monitoring unit 55 stores only the maximum value data Dmax in the current measurement, grasps the pixel row in which the next measurement period is set, and calculates the maximum value data Dmax associated with the pixel row. Extract from the storage area. When the next measurement period is set, the monitoring unit 55 inputs the maximum value data Dmax extracted from the storage area to the period determination unit 56.

For example, when the driving transistor T1 repeats passing a current through the EL element OEL, the threshold voltage Vth of the driving transistor T1 tends to increase monotonously. If the threshold voltage Vth has a tendency to increase monotonically, the population for determining the maximum value of the convergence voltage in the measurement before the current measurement is sufficient for the convergence voltage in the previous measurement. Therefore, if the monitoring unit 55 is configured to store only the maximum value data Dmax in the current measurement, the time required to acquire the characteristic value of the drive transistor T1 can be shortened, and further, before the current measurement. This simplifies the configuration for determining the maximum value of the convergence voltage in the measurement.
Further, the maximum value data Dmax associated with the pixel row to be measured this time may be, for example, the maximum value of the convergence voltage in every second measurement of the pixel row to be measured. The measurement for extracting the value may be a measurement every predetermined number of times. In short, the maximum value of the reference voltage in this measurement is larger than the maximum value of the convergence voltage in the measurement before the current measurement, and is smaller as the maximum value in the convergence voltage in the measurement before the current measurement is smaller. Any value is acceptable.

[Extension period te]
The extension period te may be a period for extending the light emission period set immediately after the current measurement. In other words, the smaller the maximum value of the reference voltage in the current measurement, the longer the light emission period immediately after the current measurement, and the shorter the time required to measure the convergence level Vs, the longer the light emission time of the EL element OEL. May be long immediately after the measurement. Even with such a configuration, a decrease in luminance in one frame can be suppressed.

・ The extension period te may be omitted. That is, regardless of the magnitude of the reference voltage in the current measurement, the length of the light emission period set immediately before the current measurement and immediately after the current measurement may be a constant value.

[Number of transmissions N]
The number N of transmissions determined by the period determining unit 56 is smaller as the maximum value in the convergence voltage in the measurement before the current measurement is larger and the smaller the maximum value in the convergence voltage in the measurement before the current measurement is smaller. Any value may be used as long as the value is the maximum value among the reference voltages in the current measurement. For example, the transmission count N determined by the period determination unit 56 may be a value obtained by multiplying the maximum value among the count values in the previous measurement by a predetermined value greater than 1.

The threshold correction amount k may be the measurement data Dout itself, or may be a value calculated separately from the extracted measurement data Dout. In short, the threshold correction amount k is a value based on the measurement data Dout and may be a value that corrects the reference gradation value Db so as to suppress a change in luminance due to a change in the shift amount ΔVth.

The convergence level Vs when the relaxation time ts has elapsed may be a voltage level that is regarded as the threshold voltage Vth, or a voltage level that changes linearly with respect to a change in the threshold voltage Vth. It may be. In short, the characteristic value in the driving transistor T1 may be a measurable value that reflects the shift amount ΔVth of the driving transistor T1.

[Measurement operation]
The data line Ld to which the measurement level VM is set in one measurement operation may be a part of all the data lines Ld. At this time, in one measurement operation, only a part of the data lines Ld for which the measurement level VM is set is connected to the analog power supply 70 via the measurement voltage switch SWs. The population of the pixels PX for extracting the maximum value data Dmax may be composed of the pixels PX to which the measurement level VM is set in one measurement operation, or the measurement level in two or more measurement operations. You may comprise from the pixel PX to which VM is set. That is, the pixel group is not limited to the pixel row, but may be a part of one pixel row, or a set of measurement objects in each of the plurality of measurement operations, and the reference voltage Any set of pixels having a common maximum value may be used.

The characteristic value of the driving transistor T1 is a parameter that contributes to the convergence level Vs, and may be the threshold voltage Vth that the driving transistor T1 has, or the current amplification factor β that the driving transistor T1 has. Good.

For example, the input signal SIG is a digital signal indicating a luminance gradation value for each EL element OEL, as in the case where an EL device is used as a light source of two gradations whether or not to expose an exposure target. Also good.

[Pixel circuit PCC]
The pixel circuit PCC is not limited to a 3T1C type circuit including three n-channel transistors and one holding capacitor Cs. For example, a 2T1C circuit including two n-channel transistors and one holding capacitor Cs. It may be a circuit composed of four or more transistors.

The pixel circuit PCC may have a configuration that does not have a function of holding the gate-source voltage Vgs in the driving transistor T1, or has a function other than the function of holding the gate-source voltage Vgs as an active element or a passive element. It may be a configuration. Note that the pixel circuit PCC preferably has a function of holding the gate-source voltage Vgs in the driving transistor T1 in that the luminance in the pixel PX is stabilized.

The driving transistor T1, the holding transistor T2, and the selection transistor T3 are not limited to n-channel transistors but may be p-channel transistors. At this time, the source of the driving transistor T1 is electrically connected to the power supply line La, and the drain of the driving transistor T1 is electrically connected to the node N2. The source of the holding transistor T2 is electrically connected to the source of the driving transistor T1, and the drain of the holding transistor T2 is electrically connected to the gate of the driving transistor T1. The drain of the selection transistor T3 is electrically connected to the data line Ld, and the source of the selection transistor T3 is electrically connected to the drain of the driving transistor T1.

The gate-source voltage Vgs in the non-light emitting period may be reverse biased in the driving transistor T1. For example, in the non-light emission operation during the non-light emission period, a voltage level lower than the reference level ELVSS may be set in the power supply signal Va.

The selection line connected to the gate of the holding transistor T2 and the selection line connected to the gate of the selection transistor T3 are different from each other, and the selection line connected to the holding transistor T2 and the selection transistor Different voltage levels may be set for the selection lines connected to T3.

According to such a configuration, it is possible to set the ON state of the holding transistor T2 and the ON state of the selection transistor T3 at different timings. Further, the off state of the holding transistor T2 and the off state of the selection transistor T3 can also be set at different timings.

In short, each of the plurality of pixel circuits PCC is a circuit in which the drive transistor T1 includes a current path for passing a current to the EL element OEL, and the drive transistor T1 controls the current based on the gradation value level Vdata. Any configuration that can set the high impedance state to the data line Ld may be used. The type of circuit elements provided in the pixel circuit PCC and the connection configuration between the circuit elements can be arbitrarily selected within such a range.

[EL element OEL]
The EL element OEL may be an organic EL element, an inorganic EL element, or a light emitting diode. In short, the EL element may be an element that emits light when a drain-source current of the driving transistor flows.

[EL device]
The EL device can be used in a display unit of various electronic devices such as a digital camera, a mobile personal computer, and a portable device.
The pixel arrangement direction in the EL device may be a two-dimensional direction or a one-dimensional direction. For example, in an EL device, a plurality of pixels PX are mounted on a photosensitive drum as a light emitting element array substrate arranged in a one-dimensional direction, and light emitted from the light emitting element array substrate is irradiated onto the photosensitive drum to cause the photosensitive drum to be used. The exposure apparatus which exposes may be sufficient.

[Element circuit]
The current driving element that receives the driving current from the driving transistor T1 is not limited to the EL element OEL or the light emitting diode, but may be various sensor elements. The element circuit including the current driving element is not limited to the combination of the pixel circuit PCC and the EL element OEL, and the driving transistor T1 includes a current path through which current flows to the current driving element, and the driving transistor T1 has a gradation value level. Any circuit that controls the current based on Vdata and can set the high impedance state to the data line Ld may be used.

The element circuit may be, for example, a sensor circuit including a sensor element and a driving transistor T1, and a current driving device to which the sensor circuit is applied is not limited to an EL device, but a sensor device including various sensor circuits. There may be. The sensor device is embodied in any one of a biosensor device, a temperature sensor device, an illuminance sensor device, and a concentration sensor device, for example. The sensor element is appropriately selected according to an object to be measured by the sensor device. For example, the sensor element is embodied as any one of a biosensor element, a temperature sensor element, an illuminance sensor element, and a concentration sensor element. The
At this time, the period in which the drive transistor T1 passes current to the sensor element, such as the light emission period in which the drive transistor T1 passes current to the EL element OEL, is the measurement period of the detection target in the sensor element.
For example, when the sensor element is an electric field cell, the electric field cell is located between an electrolyte solution containing a substrate for advancing a desired electrochemical reaction, a first working electrode connected to the node N2, and a first working electrode. A second working electrode for generating an electric field reaction and a reference electrode. The first working electrode, the second working electrode, and the reference electrode are all connected to the electrolyte solution. When an electrochemical reaction proceeds between the first working electrode and the second working electrode, the negative potential side electrode functions as a cathode electrode, and the positive potential side electrode functions as an anode electrode.

The data driver 40 sets a response level voltage corresponding to the driving amount of the sensor element to the data line Ld, and based on the voltage corresponding to the difference between the reaction level and the write level, the drive current based on the reaction level is applied to the electric field. Flow in cell EC. Thereby, the element circuit drives the electric field cell with current. Further, the data driver 40 sets a voltage at a reaction level, which is an example of a measurement level, to the data line Ld, and then measures the voltage level of the data line Ld set to the high impedance state and the voltage level of the reference electrode. Then, the oxidation-reduction potential of the substrate in the electrolyte is measured from the difference between the voltage level of the data line Ld and the voltage level of the reference electrode.

Also in the sensor device described above, the maximum value in the measurement data Dout in the element circuit group composed of a plurality of element circuits is stored as the maximum value data Dmax of the element circuit group. The maximum value in the reference voltage in the current measurement is the maximum value data Dmax associated with the pixel row to be measured this time, that is, the convergence voltage in the measurement before the current measurement. It is set based on the maximum value. Therefore, the time required for the successive comparison in the current measurement period is shorter as the maximum value data Dmax is smaller. As a result, the characteristic value of the drive transistor T1 is compared with the configuration in which the maximum value in the reference voltage is a constant value. It is possible to shorten the time required for obtaining the above, and in turn shorten the time required for measuring the oxidation-reduction potential.

k ... threshold correction amount, N ... number of transmissions, t ... elapsed time, Cs ... retention capacity, Db ... reference gradation value, HZ ... high impedance state, L1, L2 ... characteristic curve, La ... power supply line, Ld ... Data line, LP ... Latch pulse signal, Ls ... Select line, PX ... Pixel, SP ... Select start pulse signal, T1 ... Drive transistor, T2 ... Hold transistor, T3 ... Select transistor, tb ... Reference period, te ... Extension period, tp ... correction light emission period, ts ... relaxation time, Va ... power supply signal, Vd ... data signal, VM ... measurement level, Vs ... convergence level, Din ... gradation value, Ids ... drain-source current, MP1 ... selection mask pulse Signal, MP2 ... Power supply mask pulse signal, OEL ... EL element, PCC ... Pixel circuit, RST ... Clear signal, SIG ... Input signal, SP1 ... Data start pulse SPa ... Light emission period start signal, SPb ... Non-light emission period start signal, SPc ... Measurement period start signal, SW1 ... Input switch, SW2 ... Output switch, SW3 ... Measurement switch, SWd ... Display switch, SWs ... Measurement Voltage switch, tma: first non-selection period, tmb: measurement selection period, tmc: second non-selection period, Vds: drain-source voltage, VEE: analog power supply voltage, Vgs: gate-source voltage, Clkd: data Shift clock, Clkr ... Measurement shift clock, Clks ... Drive shift clock, Dmax ... Maximum value data, Dout ... Measurement data, Dsig ... Gradation component, DVSS ... Analog reference voltage, LVDD ... Logic high voltage, LVSS ... Logic low voltage, Vsel ... select signal, ELVDD ... light emission level, ELVSS ... reference level , SWtrs: transfer switch, Vdata: gradation value level, WDVSS: write level, 10: panel, 20: selection driver, 21: shift register circuit, 22: output buffer, 30: power driver, 31: shift register, 32 ... Output buffer, 40 ... Data driver, 41 ... Shift register, 42 ... Data register, 43 ... Data latch circuit, 43a ... Data latch, 43b ... AND circuit, 43c ... Flip-flop, 44 ... DAC, 45 ... Buffer, 46 ... level shifter, 47 ... up counter, 48 ... level shifter, 50 ... system controller, 51 ... input signal processing unit, 52 ... timing controller, 53 ... correction processing unit, 53A ... reference gradation generation unit, 53B ... correction processing unit, 53C ... correction amount calculation unit, 54 ... data processing unit, 55 ... supervision Visual section, 56... Period determining section, 60... Logic power supply, 70.

Claims

An element circuit group including a plurality of element circuits, each element circuit having a current drive element, a data line, and a current path for passing a current based on a voltage set in the data line to the current drive element A drive transistor; and the element circuit group configured such that the data line can be electrically connected to the current path;
A measurement unit configured to measure a convergence voltage for each of the element circuits, the measurement unit being a voltage exceeding a threshold voltage of the driving transistor for each of the plurality of element circuits, And after setting one voltage which is a reverse bias with respect to the said current drive element to the said data line, the said data line is switched to a high impedance state, thereby converging the voltage of the said data line to a convergence voltage, In addition, a plurality of reference voltages used for each element circuit are configured to perform successive comparison between a plurality of reference voltages having different magnitudes and the convergence voltage. The measurement unit in common with the reference voltage of
A setting unit for setting a reference maximum value that is a maximum value among all the reference voltages in the current measurement, and is a maximum among all the convergence voltages in at least one measurement before the current measurement. A setting unit configured to set the reference maximum value such that the reference maximum value is smaller as the maximum value is smaller than the value.
The setting unit sets the reference maximum value such that the reference maximum value is smaller as the maximum value is larger than a maximum value among all the converged voltages in the previous measurement and the maximum value is smaller. 2. The current drive device according to 1.
The said setting part sets the said reference maximum value so that it may be larger than the maximum value in all the said convergence voltage in the last measurement, and the said reference voltage may become so small that the said maximum value is small. The current drive device described.
After the measurement unit performs the current measurement, the gray level voltage based on the driving amount of the current driving element is set in the data line, and then the current based on the gray level voltage is caused to flow through the driving transistor. Further comprising
The setting unit
4. The current according to claim 1, wherein a driving period in which the driving unit flows the current through the current driving element is set to a longer period as the reference maximum value in the current measurement is smaller. 5. Drive device.
Before the measurement unit performs the current measurement, a gradation voltage based on the driving amount of the current driving element is set in the data line, and then the current based on the gradation voltage is caused to flow through the driving transistor. A drive unit;
The setting unit
4. The current according to claim 1, wherein a driving period in which the driving unit flows the current through the current driving element is set to a longer period as the reference maximum value in the current measurement is smaller. 5. Drive device.
The measuring unit is
6. The current driving device according to claim 1, wherein in the successive approximation, a voltage that is increased by a predetermined value from a predetermined minimum value is used as the reference voltage. 7.
The setting unit
The value obtained by adding a constant value to the maximum value of all the convergence voltages in at least one measurement prior to the current measurement is set as the reference maximum value in the current measurement. The current driving device according to claim 1.
A driving method of a current driving device for driving an element circuit group including a plurality of element circuits, wherein the element circuit supplies a current based on a current driving element, a data line, and a voltage set in the data line. A drive transistor having a current path that flows to the drive element, the data line is configured to be electrically connectable to the current path, and the drive method includes:
For each of the plurality of element circuits, after setting one voltage that exceeds the threshold voltage of the driving transistor and that is a reverse bias to the current driving element to the data line, the data line Switching to a high impedance state, thereby converging the data line voltage to a converged voltage;
For each of the plurality of element circuits, a step of sequentially comparing a plurality of reference voltages having different magnitudes with the convergence voltage, thereby measuring the convergence voltage for each of the element circuits, A plurality of the reference voltages used in an element circuit are common to a plurality of the reference voltages used in other element circuits; and
Including
The maximum value among all the reference voltages in the current measurement is the reference maximum value, and is greater than the maximum value among all the convergence voltages in at least one measurement before the current measurement, and The method for driving a current driver further includes a step of setting the reference maximum value such that the reference maximum value is smaller as the maximum value is smaller.