JP2011158864A - Light emission driving device, light emitting device and method for controlling drive of the same, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a light emission driving device which restrains occurrence of luminance unevenness and screen flickering due to waveform distortion of a driving signal in a light emitting panel which is ready for an active matrix type driving system; and to provide a light emitting device and a method for controlling the drive of the same, and electronic equipment equipped with the light emitting device. <P>SOLUTION: A second signal voltage applying period Twh2 and a first signal voltage applying period Twh1 are set to the writing operation period Twrt of each line. Firstly, a selection signal Ssel of a second signal voltage Vsh2 (for example, +18 V) based on an Hi voltage 2 is applied to a selection line Ls in the second signal voltage applying period Twh2. Secondly, a selection signal Ssel of a first signal voltage Vsh1 (for example, +15 V) based on an Hi voltage 1 is applied to the selection line Ls in the first signal voltage applying period Twh1. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a light emission drive device, a light emission device, a drive control method thereof, and an electronic device, and in particular, a light emission drive device for driving a light emission panel (including a display panel) compatible with an active matrix drive method, The present invention relates to a light emitting device including the light emission driving device, a drive control method thereof, and an electronic apparatus including the light emitting device.

  In recent years, as a next-generation display device, a light-emitting element type display device (light-emitting device) including a display panel in which self-light-emitting elements such as organic electroluminescence elements (organic EL elements) are arranged in a matrix has been attracting attention. Such a display device is currently put into practical use as a relatively small display device such as a mobile phone, a digital audio player, and a car navigation monitor.

  Here, in a light emitting element type display device, an active matrix type driving method is widely adopted. According to such a light emitting element type display device, the display response speed is higher than that of a known liquid crystal display device, and there is almost no viewing angle dependence. Further, high brightness and high contrast and display image quality are achieved. It has excellent display characteristics that high definition can be achieved. In addition, the light emitting element type display device does not require a backlight or a light guide plate unlike a liquid crystal display device, and thus has a feature that the device configuration can be further reduced in thickness and weight. Therefore, it is expected to be applied to various electronic devices in the future, and research and development for increasing the size of the display screen is being conducted.

  In general, a drive control method in an active matrix display device is such that display pixels in each row are sequentially set to a selected state, and a gradation voltage corresponding to display data is applied in synchronization with the selection timing (display data is written). Thus, gradation control is performed based on the voltage component held in each display pixel. In such a light emitting element type display device (for example, organic EL display device), as described in, for example, Patent Document 1 and Patent Document 2, a pixel circuit including two or more thin film transistors in each pixel. (Light emission drive circuit) is provided.

JP-A-8-330600 JP 2001-147659 A

  By the way, not only the light emitting element type display device but also a known liquid crystal display device, when the display screen is enlarged, the wiring length from the driver for driving the pixel to the pixel becomes long. It is generally known that the magnitude of the load varies depending on the waveform, and the drive signal waveform is rounded or delayed. Here, in the liquid crystal display device, since the switching element provided in each pixel usually has only one thin film transistor (TFT), for example, the parasitic capacitance (wiring capacitance) generated in the gate line is relatively small.

  On the other hand, in a light emitting element type display device (for example, an organic EL display device) that employs an active matrix type driving method, as described in Patent Document 1 and Patent Document 2 described above, Since a plurality of thin film transistors are provided in a pixel, a parasitic capacitance generated in a wiring such as a scanning line (a gate line; referred to as a “selection line” in the embodiments described later) becomes large, and the time is based on the wiring resistance and the parasitic capacitance. Depending on the constant, there has been a problem that waveform rounding generated in a drive signal such as a scanning signal (gate signal; referred to as “selection signal” in the embodiments described later) becomes significant. For this reason, the substantial selection period of each pixel is different from each other, resulting in uneven brightness in the screen, or the substantial selection period becomes relatively short, resulting in insufficient writing of image data and flickering of the screen. It had a problem that it occurred.

  In particular, in a display device having a large display screen, when a display operation such as a double speed drive (120 Hz drive) is performed, the influence of such rounding of the drive signal tends to become more prominent. Note that the waveform rounding of the scanning signal in the organic EL display device will be described in detail in an embodiment described later.

  Therefore, in view of the above-described problems, the present invention is a light emitting drive that can suppress occurrence of luminance unevenness and screen flicker due to waveform rounding of a drive signal in a light emitting panel that supports an active matrix driving method. An object of the present invention is to provide a light-emitting device having good and uniform light emission characteristics, a drive control method thereof, and an electronic apparatus including the light-emitting device.

  The invention according to claim 1 includes a light emitting drive circuit having a light emitting element, a driving transistor for controlling a current supplied to the light emitting element, and a switching transistor for controlling an operation of the driving transistor, and is connected to the switching transistor. A light emission driving device that drives a plurality of pixels arranged along the extending direction of the scanning line and controls light emission of the light emitting element of each pixel, A selection drive circuit configured to apply a selection signal to one end of the scanning line during a signal application period to set the selection transistor to operate the switching transistor of each pixel, and the selection signal is included in the signal application period; A second signal set to a first signal voltage in the first period and having a higher potential than the first signal in a second period preceding the first period during the signal application period; The voltage of the second period and the voltage value of the second signal voltage are set at the start time of the first period when the selection signal is applied to one end of the scanning line. The first voltage value composed of the voltage value of the scanning line in the vicinity of the first pixel at the position where the distance from the one end of the scanning line is the shortest, and the position where the distance from the one end of the scanning line is the longest And the second voltage value composed of the voltage value of the scanning line in the vicinity of the second pixel is set to a value within an allowable range, and the allowable range is a voltage value of the first signal voltage. It is characterized by a value of 95% to 110%.

According to a second aspect of the present invention, in the light emission driving device according to the first aspect, the voltage of the selection signal is set corresponding to an operating voltage, and the operating voltage is set when the selection signal is set to the first signal voltage. And a voltage switching circuit that switches the operating voltage to a second set voltage that is higher than the first signal voltage when the selection signal is set to the second signal voltage. And
According to a third aspect of the present invention, in the light emission driving device according to the first or second aspect, the device includes a voltage measurement circuit that is connected to the scanning line and measures the first voltage value and the second voltage value. It is characterized by.
According to a fourth aspect of the present invention, in the light emission driving device according to the third aspect, the voltage value of the second signal voltage is set to a fixed value, the time of the second period is set to a variable value, and the voltage A control circuit is provided for setting the time of the second period based on a comparison between the first voltage value and the second voltage value measured by a measurement circuit.
According to a fifth aspect of the present invention, in the light emission driving device according to the third aspect, the time of the second period and the voltage value of the second signal voltage are set to variable values and measured by the voltage measuring circuit. A control circuit is provided for setting the time of the second period and the voltage value of the second signal voltage based on the comparison between the first voltage value and the second voltage value.

  According to a sixth aspect of the present invention, a light emitting device includes a plurality of pixels each having a light emitting element, a light emitting driving circuit having a driving transistor that controls a current supplied to the light emitting element, and a switching transistor that controls an operation of the driving transistor. And a plurality of scanning lines connected to the switching transistors of the plurality of pixels, wherein the pixels are arranged along the extending direction of the scanning lines, A light-emitting drive device that drives the light-emitting elements of the plurality of pixels, and the light-emitting drive device is configured to write each grayscale signal based on image data to each pixel during a writing operation period. A selection drive circuit configured to apply a selection signal to one end to set the selection state in which the switching transistor of each pixel is operated; The first signal voltage is set in the first period during the operation period, and the second signal voltage is higher than the first signal voltage in the second period prior to the first period during the write operation period. The time period of the second period and the voltage value of the second signal voltage are set at the start of the first period when the selection signal is applied to one end of the one scanning line. The first voltage value of the scanning line in the vicinity of the first pixel at the shortest distance from one end of the scanning line and the second voltage at the longest distance from one end of the scanning line The second voltage value of the scanning line in the vicinity of the pixel is set to be a value within an allowable range, and the allowable range is a value of 95% to 110% of the voltage value of the first signal voltage. It is characterized by being.

According to a seventh aspect of the present invention, in the light emitting device according to the sixth aspect, the voltage of the selection signal is set corresponding to an operating voltage, and the operating voltage is set when the selection signal is set to the first signal voltage. A voltage switching circuit configured to switch the operating voltage to a second set voltage having a higher potential than the first signal voltage when the first set voltage is set and the selection signal is set to the second signal voltage; To do.
The invention according to claim 8 is the light emitting device according to claim 6 or 7, further comprising a voltage measurement circuit connected to the scanning line and measuring the first voltage value and the second voltage value. Features.
According to a ninth aspect of the present invention, in the light emitting device according to the eighth aspect, the voltage value of the second signal voltage is set to a fixed value, and the time of the second period is set to a variable value. A control circuit is provided for setting the time of the second period based on a comparison between the first voltage value and the second voltage value measured by a circuit.
According to a tenth aspect of the present invention, in the light emitting device according to the eighth aspect, the time of the second period and the voltage value of the second signal voltage are set to variable values and measured by the voltage measuring circuit. A control circuit is provided for setting the time of the second period and the voltage value of the second signal voltage based on a comparison between the first voltage value and the second voltage value.
According to an eleventh aspect of the present invention, in the light emitting device according to any one of the sixth to tenth aspects, the light emitting element is an organic electroluminescence element.
An electronic apparatus according to a twelfth aspect of the invention is characterized in that the light emitting device according to any of the sixth to eleventh aspects is mounted.

  According to a thirteenth aspect of the present invention, there are provided a plurality of pixels each including a light emitting driving circuit having a light emitting element, a driving transistor for controlling a current supplied to the light emitting element, and a switching transistor for controlling an operation of the driving transistor; A plurality of scanning lines connected to the switching transistors of the pixels, and each pixel includes a light-emitting panel arranged along the extending direction of the scanning lines, and a luminance gradation corresponding to image data A light emitting device driving control method for causing the light emitting elements of the plurality of pixels to emit light, wherein the voltage value of the first signal voltage and the voltage value of the second signal voltage having a potential higher than the first signal voltage; A setting step for setting a time of a second period, and a gradation signal based on the image data in one end of each scanning line in a first period during a writing operation period in which each pixel is written. A first signal voltage applying step in which a voltage value of a selection signal for operating the switching transistor of each pixel is set to the first signal voltage and applied; and in the first period during the writing operation period A second signal voltage applying step of applying the voltage value of the selection signal to the second signal voltage at one end of each scanning line in the second period in advance, and the setting step includes: The time of the second period and the voltage value of the second signal voltage are applied to one end of one scanning line by the second signal voltage step and the first signal voltage step, respectively. The first voltage value of the scanning line in the vicinity of the first pixel at the position where the distance from the one end of the scanning line is the shortest at the start of the first period, and from one end of the scanning line In the position with the longest distance The second voltage value of the scanning line in the vicinity of the second pixel is set to a value within an allowable range, and the allowable range is 95% to 110% of the voltage value of the first signal voltage. % Value.

According to a fourteenth aspect of the present invention, in the drive control method for a light emitting device according to the thirteenth aspect, the setting step includes an initialization step of setting a time of the second period to a predetermined initial value, and the selection signal. A selection signal applying step applied to one end of the scanning line; a voltage measuring step for measuring the first voltage value and the second voltage value; and the measured first voltage value and the second voltage. In the voltage comparison step that compares the value and the first signal voltage, the application time adjustment step that adjusts the time of the second period based on the comparison result in the voltage comparison step, and the voltage comparison step, The time of the second period when the first voltage value and the second voltage value are within the allowable range is set as the time of the second period in the second signal voltage application step. And application period determination step that, characterized in that it comprises a.
According to a fifteenth aspect of the present invention, in the drive control method for a light emitting device according to the thirteenth aspect, the setting step includes a voltage initialization step for setting a voltage value of the second signal voltage to a predetermined initial value, and the first step. An application time initialization step for setting the time of period 2 to a predetermined initial value, a selection signal application step for applying the selection signal to one end of the scanning line, the first voltage value, and the second voltage. A voltage measurement step for measuring a value, a voltage comparison step for comparing the measured first voltage value and the second voltage value with the first signal voltage, and a comparison result in the voltage comparison step An application time adjustment step of adjusting the time of the second period, an application time determination step of determining whether or not the time of the second period is shorter than the writing operation period, and an application time determination step In the voltage value adjusting step for adjusting the voltage value of the second signal voltage based on the determination result, and in the voltage comparing step, the first voltage value and the second voltage value are values within the allowable range. The time of the second period and the voltage value of the second signal voltage are set to the time of the second period and the voltage value of the second signal voltage in the second signal voltage application step. And an application period / voltage determination step.

  According to the present invention, in a light-emitting panel that supports an active matrix driving method, it is possible to suppress occurrence of luminance unevenness and screen flicker due to waveform rounding of a driving signal.

It is a schematic block diagram which shows an example of the display apparatus to which the light-emitting device based on this invention is applied. It is a principal part block diagram which shows an example of the display panel applied to the display apparatus which concerns on 1st Embodiment, and its periphery circuit. It is the schematic which shows the structural example of the voltage value setting mechanism containing the selection driver applied to the display apparatus which concerns on 1st Embodiment. It is the schematic which shows the structural example of the data driver applied to the display apparatus which concerns on 1st Embodiment. It is a circuit block diagram which shows an example of the pixel applied to the display panel which concerns on 1st Embodiment. 5 is a timing chart showing basic operations in display pixels applied to the display device according to the first embodiment. 5 is a timing chart illustrating a voltage value setting operation of a selection signal in a selection driver applied to the display device according to the first embodiment. It is a conceptual diagram which shows the write-in operation | movement and light emission operation | movement in the display pixel which concerns on 1st Embodiment. 5 is a timing chart illustrating an example of a drive control method for a display device to be compared in the first embodiment. It is a figure which shows the change of the selection line voltage at the time of applying the drive control method used as a comparison object. It is a figure which shows the change of the selection line voltage at the time of applying the drive control method which concerns on 1st Embodiment. It is a schematic block diagram which shows the measuring mechanism of the selection line voltage applied to the display apparatus which concerns on 1st Embodiment. It is a flowchart which shows an example of the setting method of the 2nd signal voltage application period applied to the display apparatus which concerns on 1st Embodiment. It is a schematic block diagram which shows an example of the display apparatus which concerns on 2nd Embodiment. 10 is a timing chart illustrating a voltage value setting operation of a selection signal in a selection driver applied to the display device according to the second embodiment. It is a schematic block diagram (the 1) which shows the structural example of the display apparatus which concerns on 3rd Embodiment. It is a schematic block diagram (the 2) which shows the structural example of the display apparatus which concerns on 3rd Embodiment. It is the schematic which shows the structural example of the voltage value setting mechanism containing the selection driver function part of the selection * data 1 chip driver applied to the display apparatus which concerns on 3rd Embodiment. It is a flowchart which shows an example of the setting method of the 2nd signal voltage application period applied to the display apparatus which concerns on 3rd Embodiment, and its voltage. It is a wave form chart for explaining a selection signal set up by a drive control method concerning a 3rd embodiment. It is a perspective view which shows the structural example of the thin-type television to which the display apparatus (light-emitting device) concerning 1st thru | or 3rd embodiment is applied.

DESCRIPTION OF EMBODIMENTS Hereinafter, a light emission drive device, a light emission device, a drive control method thereof, and an electronic device according to the present invention will be described in detail with reference to embodiments.
<First Embodiment>
First, a schematic configuration of a light emitting device including a light emission driving device according to the present invention will be described with reference to the drawings. Here, a case where the light-emitting device according to the present invention is applied as a display device will be described.

(Display device)
FIG. 1 is a schematic block diagram showing an example of a display device to which the light emitting device according to the present invention is applied, and FIG. 2 is an example of a display panel and its peripheral circuit applied to the display device according to the first embodiment. FIG. FIG. 3 is a schematic diagram illustrating a configuration example of a voltage value setting mechanism including a selection driver applied to the display device according to the present embodiment.

  As shown in FIGS. 1 and 2, a display device (light emitting device) 100 according to the present embodiment is schematically shown as a display panel (light emitting panel) 110, a selection driver (selection drive circuit) 120, and a power supply driver (power supply drive). Circuit) 130, a data driver (signal drive circuit) 140, and a controller (control circuit) 150. Here, the selection driver 120, the power supply driver 130, the data driver 140, and the controller 150 correspond to the light emission driving device in the present invention.

  As shown in FIGS. 1 and 2, the display panel 110 includes a plurality of pixels PIX, a plurality of selection lines (scanning lines) Ls connected to each pixel PIX, a plurality of power supply lines La, and a plurality of pixels on the panel substrate. Data line (signal line) Ld and common electrode Ec. The plurality of pixels PIX are two-dimensionally arranged (for example, n rows × m columns; n and m are positive integers) in a row direction (horizontal direction in the drawing) and a column direction (vertical direction in the drawing) on the panel substrate. Each pixel PIX has a light emission drive circuit and a light emitting element, as will be described later. The plurality of selection lines Ls and the plurality of power supply lines La are arranged so as to be connected to the pixels PIX arranged in the row direction of the panel substrate for each row. The plurality of data lines Ld are arranged so as to be connected to the pixels PIX arranged in the column direction of the panel substrate for each column. The common electrode Ec is provided so as to be commonly connected to all the pixels PIX.

  The selection driver 120 is connected to each selection line Ls arranged on the display panel 110 described above. The selection driver 120 applies a selection signal Ssel of a predetermined voltage level (selection level or non-selection level) to the selection line Ls of each row at a predetermined timing based on a selection control signal supplied from the controller 150 described later. Thus, the pixels PIX in each row are set to the selected state. Specifically, the selection driver 120 sequentially shifts and applies the selection signal Ssel to the selection lines Ls of each row at a predetermined timing, thereby sequentially setting the pixels PIX of each row arranged on the display panel 110 to a selected state. Set.

  For example, as shown in FIG. 2, the selection driver 120 sequentially outputs a shift signal corresponding to the selection line Ls of each row based on a selection control signal (scanning clock signal SCK, scanning start signal SST) supplied from the controller 150. Shift register 121 that converts the shift signal to a predetermined signal level (selection level; high level), and a selection line Ls of each row based on a selection control signal (output enable signal SOE) supplied from the controller 150 And an output circuit 122 that sequentially outputs the selection signal Ssel.

  Here, the selection driver 120 according to the present embodiment is configured to be able to set different voltage values as the selection level (high level) of the selection signal Ssel output to the selection line Ls. Specifically, in the output circuit 122 described above, as the high-level side operation voltage (level conversion voltage) used when converting the signal level of the shift signal, different voltage values (for convenience, “Hi voltage 1 ( First setting voltage) ”and“ Hi voltage 2 (second setting voltage) ”are selectively set (switched). Thereby, the voltage of the selection signal Ssel of the selection level output to the selection line Ls is switched to the first signal voltage Vsh1 based on the Hi voltage 1 or the second signal voltage Vsh2 based on the Hi voltage 2 at an arbitrary timing. It is done.

  In order to realize the voltage switching function of the selection signal Ssel, the selection driver 120 has a configuration (voltage value setting mechanism) as shown in FIGS. 3A and 3B, for example. The voltage value setting mechanism shown in FIG. 3A is a high-level operation voltage (Hi voltage; expressed as “Hi power supply” in the figure) supplied to the selection driver 120 (specifically, the output circuit 122). A switch (voltage switching circuit) 161 for switching setting is provided. The switch 161 is connected to the Hi power source 1 (Hi voltage 1; for example, + 15V) and the Hi power source 2 (Hi voltage 2, for example, + 18V), and receives a Hi signal by a switch control signal that is a kind of selection control signal supplied from the controller 150. Switching control is performed so that either the power source 1 or the Hi power source 2 is connected to the selection driver 120 as the Hi power source. Note that a Lo power supply is connected to the selection driver 120, and a Lo voltage (for example, −15 V) is always supplied as an operating voltage on the low level side.

  Further, the voltage value setting mechanism can be applied with a configuration as shown in FIG. The voltage value setting mechanism shown in FIG. 3B has a configuration in which the switch 161 shown in FIG. 3A is provided as a switch (voltage switching circuit) 162 inside the selection driver 120. In other words, the selection driver 120 is connected to the Hi power source 1 and the Hi power source 2, and is supplied with the Hi voltage 1 (for example, + 15V) and the Hi voltage 2 (for example, + 18V) as the operating voltage on the high level side. Then, the switch 162 is switched and controlled by a switch control signal supplied from the controller 150, and either the Hi voltage 1 or the Hi voltage 2 is used as a high-level operating voltage (indicated as “internal Hi power supply” in the figure). To do.

  With the voltage value setting mechanism having such a configuration, in a display drive operation (drive control method) described later, a pixel PIX in each row is set to a selected state, and a gradation signal (gradation voltage Vdata) corresponding to image data is generated. During the writing operation period, based on a selection control signal (switch control signal) from the controller 150, the selection driver 120 first selects the second signal voltage Vsh2 (for example, + 18V) having a potential higher than normal (design value). The signal Ssel is applied to the selection line Ls, and then the selection signal Ssel of the normal first signal voltage Vsh1 (for example, +15 V) is applied.

  The power driver 130 is connected to each power line La provided on the display panel 110. The power supply driver 130 applies a power supply voltage Vsa having a predetermined voltage value (light emission level or non-light emission level) to the power supply line La of each row at a predetermined timing based on a power supply control signal supplied from the controller 150 described later. Specifically, the power supply driver 130 supplies a high-level power supply voltage Vsa to the power supply line La of the pixels PIX in each row only during a light emission operation (light emission operation period) in a display drive operation (drive control method) described later. Apply. On the other hand, the power supply driver 130 applies a low-level power supply voltage Vsa to the power supply line La of the pixels PIX in each row during a non-light-emitting operation including a writing operation period for the pixels PIX in each row.

  The data driver 140 is connected to each data line Ld of the display panel 110 and generates a gradation signal (gradation voltage Vdata) corresponding to image data based on a data control signal supplied from a controller 150 described later. , And supplied to the pixel PIX via each data line Ld.

  FIG. 4 is a schematic diagram illustrating a configuration example of a data driver applied to the display device according to the present embodiment. Note that the configuration of the data driver shown in FIG. 4 is merely an example that can generate the gradation voltage Vdata having a voltage value corresponding to the display data, and the present invention is not limited to this. Absent.

  For example, as illustrated in FIG. 4, the data driver 140 includes a shift register circuit 141, a data register circuit 142, a data latch circuit 143, and a digital-analog conversion circuit (denoted as “D / A converter” in the figure) 144. And a buffer circuit 145.

  The shift register circuit 141 sequentially generates and outputs shift signals based on the data control signals (shift clock signal CLK, sampling start signal STR) supplied from the controller 150. The data register circuit 142 sequentially takes in display data D0 to Dm for one row supplied from the controller 150 based on the input timing of the shift signal. The data latch circuit 143 holds display data D0 to Dm composed of one row of digital data fetched by the data register circuit 142 based on the data control signal (data latch signal STB). The D / A converter 144 converts the held display data D0 to Dm into a predetermined analog signal voltage (grayscale voltage Vpix) based on the grayscale reference voltages V0 to VP supplied from power supply means (not shown). ). The buffer circuit 145 generates a gradation voltage Vdata corresponding to the gradation voltage Vpix. The buffer circuit 145 simultaneously outputs the gradation voltage Vdata to the data line Ld of the column corresponding to the display data at a timing based on the data control signal (output enable signal OE) supplied from the controller 150. .

  The controller 150 generates display data including digital data including luminance gradation data based on image data supplied from the outside of the display device 100 and supplies the display data to the data driver 140. In addition, the controller 150 controls the operation states of the selection driver 120, the power supply driver 130, and the data driver 140 described above based on a timing signal generated or extracted based on the image data, and performs predetermined driving on the display panel 110. A selection control signal, a power supply control signal, and a data control signal for executing the control operation are generated and output.

  In addition, in the controller 150 according to the present embodiment, a selection control signal including a switch control signal is supplied to the selection driver 120 (strictly, a voltage value setting mechanism including the switch 161 or 162). Thus, the voltage of the selection signal Ssel applied from the selection driver 120 to the selection line Ls is controlled to be switched at a predetermined timing during the writing operation period in which the gradation signal (gradation voltage Vdata) corresponding to the image data is written. . Specifically, the controller 150 determines the voltage of the selection signal Ssel in a state where the parasitic capacitance of the selection line Ls is not large and the above-described waveform rounding of the selection signal Ssel does not occur or is not noticeable (normal state). As (design value), control is performed so that the selection signal Ssel of the second signal voltage Vsh2 having a potential higher than the normal voltage is first applied to the selection line Ls. Thereafter, the controller 150 controls the selection signal Ssel of the normal voltage (first signal voltage Vsh1) to be applied to the selection line Ls.

(Pixel)
Next, a configuration example of the pixels PIX arranged in the display panel 110 according to the present embodiment will be specifically described.

  FIG. 5 is a circuit configuration diagram illustrating an example of a pixel applied to the display panel according to the present embodiment. Note that the configuration of the pixel shown in FIG. 5 is merely an example of a pixel circuit (light emission driving circuit) applicable to the active matrix driving method, and the present invention is not limited to this. . That is, as long as the pixel circuit includes a plurality of thin film transistors, those described in Patent Documents 1 and 2 described above may be used. In this embodiment, as an example of a pixel, by applying a gradation voltage having a voltage value corresponding to display data, a light emission driving current corresponding to display data is caused to flow to the light emitting element provided in each pixel. The case where a circuit configuration corresponding to a voltage designation type gradation control method for performing light emission operation (display operation) at a desired luminance gradation is described, but the present invention is not limited to this. That is, the pixel applicable to this embodiment supplies a light emission driving current corresponding to the display data to the light emitting element of each pixel by supplying a gradation current having a current value corresponding to the display data, for example. It may be provided with a circuit configuration corresponding to a current designation type gradation control method in which a light emission operation is performed at a luminance gradation.

  As shown in FIG. 5, the pixel PIX applied to the display panel 110 according to the present embodiment is near each intersection of the selection line Ls connected to the selection driver 120 and the data line Ld connected to the data driver 140. Has been placed. Each pixel PIX includes an organic EL element OEL, which is a current-driven light emitting element, and a light emission drive circuit (pixel circuit) DC that generates a current for driving the organic EL element OEL to emit light.

  Here, the light emission drive circuit DC sets the pixel PIX to the selected state based on the selection signal Ssel applied from the selection driver 120 during the write operation in the display drive operation described later, and is supplied from the data driver 140. A gradation signal (gradation voltage Vdata) is taken in. Further, during the light emission operation, the light emission drive circuit DC generates a light emission drive current corresponding to the captured gradation signal and supplies it to the organic EL element OEL.

  The light emission drive circuit DC shown in FIG. 5 has a circuit configuration including three transistors (thin film transistors) Tr11 to Tr13 and a capacitor Cs. The transistor (switching transistor) Tr11 has a gate terminal connected to the selection line Ls, a drain terminal connected to the power supply line La, and a source terminal connected to the contact N11. The transistor (switching transistor) Tr12 has a gate terminal connected to the selection line Ls, a source terminal connected to the data line Ld, and a drain terminal connected to the contact N12. The transistor (drive transistor) Tr13 has a gate terminal connected to the contact N11, a drain terminal connected to the power supply line La, and a source terminal connected to the contact N12. The capacitor (capacitance element) Cs is connected between the gate terminal (contact N11) and the source terminal (contact N12) of the transistor Tr13. The capacitor Cs may be a parasitic capacitance formed between the gate and the source terminal of the transistor Tr13, or in addition to the parasitic capacitance, a separate capacitance element is connected in parallel between the contact N11 and the contact N12. May be.

  The organic EL element OEL has an anode (anode electrode) connected to the contact N12 of the light emission drive circuit DC and a cathode (cathode electrode) connected to the common electrode Ec. The common electrode Ec is connected to a constant voltage source (not shown), and a predetermined low-potential common voltage Vcom (for example, a ground potential Vgnd) is applied to the common electrode Ec.

  In FIG. 5, the transistors Tr11 to Tr13 are not particularly limited, but for example, thin film transistors having the same channel type can be applied. The transistors Tr11 to Tr13 may be amorphous silicon thin film transistors or polysilicon thin film transistors.

  In particular, when an n-channel thin film transistor is applied as the transistors Tr11 to Tr13 and an amorphous silicon thin film transistor is applied as the transistors Tr11 to Tr13, an amorphous silicon manufacturing technique that has already been established is applied. Compared with a single crystal silicon thin film transistor, a transistor with uniform and stable operation characteristics (such as electron mobility) can be realized with a simple manufacturing process.

(Display device drive control method)
Next, a drive control method (image display operation) in the display device according to the present embodiment will be described with reference to the drawings.

  FIG. 6 is a timing chart showing the basic operation in the display pixel applied to the display device according to the present embodiment. FIG. 7 is a timing chart showing the voltage setting operation of the selection signal in the selection driver applied to the display device according to the present embodiment. In FIG. 6, the operation will be described by focusing on the pixels PIX in a specific row among the pixels PIX two-dimensionally arranged on the display panel 110. In FIG. 7, the voltage value setting operation of the selection signal will be described by paying attention to the first to third selection lines among the pixels PIX two-dimensionally arranged on the display panel 110 for convenience. FIG. 8 is a conceptual diagram showing a writing operation and a light emitting operation in the display pixel according to the present embodiment.

  The drive control method (image display operation) of the display device 100 according to the present embodiment is schematically described as follows. As shown in FIG. 6, a write operation for writing display data to the pixels PIX in each row within a predetermined one processing cycle period Tcyc. It is set to include a period (signal application period) Twrt and a light emission operation period (display operation period) Temp that causes all the pixels PIX to emit light at the same time with a luminance gradation corresponding to the display data ( Tcyc ≧ Twrt + Tem). Here, in the writing operation period Twrt, the organic EL elements OEL of all the pixels PIX are set to a non-light emitting state in which the light emitting operation is not performed.

(Write operation)
In the write operation period Twrt, as shown in FIG. 6, a selection signal Ssel set to a predetermined selection level (high level) is sequentially applied from the selection driver 120 to each selection line Ls. The pixel PIX connected to the selection line Ls is set to the selected state. At this time, the power supply driver 130 applies the power supply voltage Vsa of the non-light emitting level (low level; potential equal to or lower than the common voltage Vcom) to the power supply line La of each row.

  Here, as shown in FIG. 6 and FIG. 7, in the write operation period Twrt of each row, the second signal voltage application period (second period) Twh2 and the first signal voltage application period (first period). Twh1 is set. Then, the selection signal Ssel applied to the selection line Ls from the selection driver 120 is set so that the voltage value thereof differs between the second signal voltage application period Twh2 and the first signal voltage application period Twh1. The switching timing between the second signal voltage application period Twh2 and the first signal voltage application period Twh1 is set in advance.

  Specifically, in the second signal voltage application period Twh2, based on the selection control signal (switch control signal) supplied from the controller 150 to the selection driver 120, the output circuit 122 of the selection driver 120 is An operating voltage of Hi voltage 2 (for example, +18 V) is supplied from the Hi power source 2. Thereby, the selection signal Ssel of the second signal voltage Vsh2 (for example, + 18V) based on the Hi voltage 2 (second setting voltage) is applied as the selection level from the selection driver 120 to the selection line Ls. Here, the time width of the second signal voltage application period Twh2 is defined based on the signal width of the switch control signal supplied from the controller 150, as shown in FIG.

  Next, in the first signal voltage application period Twh1, based on the selection control signal (switch control signal) supplied to the selection driver 120, the Hi power supply 1 to the Hi voltage 1 is supplied to the output circuit 122 of the selection driver 120. An operating voltage (for example, + 15V) is supplied. Accordingly, the selection signal Ssel of the first signal voltage Vsh1 (for example, + 15V) based on the Hi voltage 1 (first setting voltage) is applied as the selection level from the selection driver 120 to the selection line Ls.

  Thus, by applying a predetermined drive signal from each driver, the transistors Tr11 and Tr12 provided in the light emission drive circuit DC of each pixel PIX in the row set to the selected state are turned on, and the transistor Tr13 is turned on. The gate and drain terminals are short-circuited to set the diode connection state.

  Then, as shown in FIG. 6, in synchronization with this timing, the gradation voltage Vdata having a voltage value corresponding to the display data is supplied from the data driver 140 to each data line Ld. Here, the gradation voltage Vdata is set to a negative voltage value corresponding to the luminance gradation value included in the display data written to each pixel PIX. Here, the gradation voltage Vdata is a negative voltage, and a write current Ia, which will be described later, is a negative current. However, in FIG.

  Thus, by supplying the negative gradation voltage Vdata to the data line Ld, a voltage lower than the low-level power supply voltage Vsa is applied to the source terminal (contact N12; the other end of the capacitor Cs) of the transistor Tr13. Side).

  Accordingly, a potential difference is generated between the contacts N11 and N12 (between the gate and the source of the transistor Tr13), so that the transistor Tr13 is turned on. As shown in FIG. 8A, the transistor Tr13, the contact N12, A write current Ia corresponding to the gradation voltage Vdata flows in the direction of the data driver 140 via the transistor Tr12 and the data line Ld.

  At this time, charges corresponding to the potential difference generated between the contacts N11 and N12 (between the gate and source of the thin film transistor Tr13) are accumulated in the capacitor Cs and held as a voltage component. In addition, since the potential applied to the anode (contact N12) of the organic EL element OEL is lower than the cathode potential (common voltage Vcom), no current flows through the organic EL element OEL and no light emission operation is performed (non-lighting). (Light emission operation).

  Then, the writing operation to the pixels PIX in each row as described above is repeatedly executed so as not to overlap each other in time. Specifically, as shown in FIG. 7, the selection signal Ssel that is switched and set to the different voltages (first signal voltage Vsh1, second signal voltage Vsh2) as described above for the selection line Ls in the first row. Is applied to set the pixel PIX to the selected state, and a series of operations for supplying the gradation voltage Vdata and writing the voltage component corresponding to the display data to each data line Ld is performed on the pixels PIX in the second and subsequent rows. Are sequentially executed at different timings. Here, during the period in which the writing operation is repeatedly performed on the pixels PIX in each row, the power supply voltage Vsa of the non-light emission level is applied from the power supply driver 130 to the power supply line La in each row. The organic EL element OEL of each pixel PIX is set to a non-light emitting state where the light emitting operation is not performed.

(Light emission operation)
Next, in the light emission operation period (display operation period) Tem after the end of the write operation period Twrt, as shown in FIG. 6, the selection driver 120 sets Lo as the non-selection level (low level) for each selection line Ls. By applying a selection signal Ssel of a voltage Vsl (for example, −15 V) based on the voltage, each pixel PIX is set to a non-selected state. As a result, the transistors Tr11 and Tr12 provided in the light emission drive circuit DC of each pixel PIX are turned off, and the connection between the data line Ld and each pixel PIX is cut off. At this time, the capacitor Cs holds the charge accumulated in the above-described write operation period Twrt.

  In this state, the power supply driver 130 applies the power supply voltage Vsa of the light emission level (high level; potential higher than the common voltage Vcom) to the power supply line La of each row. As a result, the potential difference between the gate and source of the transistor Tr13 (both ends of the capacitor Cs) of the transistor provided in each pixel PIX is maintained, the transistor Tr13 is maintained in the ON state, and the organic EL element OEL The potential applied to the anode (contact N12) is higher than the cathode potential (ground potential).

  Therefore, as shown in FIG. 8B, in each pixel PIX, a current substantially equal to the write current Ia in the forward bias direction from the power supply line La to the organic EL element OEL via the transistor Tr13 and the contact N12. The light emission drive current Ib of the value flows, and the organic EL element OEL emits light. Thereby, the organic EL element OEL of each pixel PIX continues the operation of emitting light with a luminance gradation corresponding to the display data (gradation voltage Vdata) written in the writing operation period Twrt.

(Comparison verification)
Next, operational effects of the display device (light emitting device) and the drive control method thereof according to the present embodiment will be described in detail with reference to comparison targets.

  FIG. 9 is a timing chart illustrating an example of a drive control method for a display device to be compared in the present embodiment. FIG. 10 is a diagram showing a change in the selected line voltage when the drive control method to be compared is applied.

  First, as a comparison target, in the display device 100 including the pixel PIX as shown in FIG. 5, as shown in FIG. 9, the selection signal Ssel in which the high-level side voltage value is set constant is shown during the writing operation. A case of applying to the selection line Ls will be described. In this case, the selection signal Ssel applied from the selection driver 120 to the selection line Ls is set to a single voltage Vsh (for example, +15 V) as a selection level. This selection level corresponds to the first signal voltage Vsh1 of the selection signal Ssel which is the normal voltage in the first embodiment described above. Further, the selection signal Ssel is set to −15 V, for example, as a non-selection level. This non-selection level corresponds to the voltage Vsl of the Lo power source in the first embodiment described above.

  In the case of using such a drive control method, a simulation experiment was performed on a change in the selection line voltage when the selection signal Ssel was applied to the selection line Ls. According to this, as shown in FIG. 10, the selection line voltage (normalized detection voltage in the drawing) in the vicinity of the pixel PIX in the first column with the shortest distance from the selection driver 120 is the characteristic line SPX ( As shown in 1), with respect to the selection signal Ssel output from the selection driver 120, the voltage value of the selection signal Ssel (in the figure, the normalized value 1.V) in a relatively short time (0 to about 2.0 μsec). 0) and then (approximately from 2.0 μsec), then gradually converged to the voltage value of the selection signal Ssel with time.

  On the other hand, the selection line voltage in the vicinity of the pixel PIX in the m-th column having the longest distance from the selection driver 120 is applied with the selection signal Ssel from the selection driver 120 as shown by the characteristic line SPX (m) in the figure. It gradually increased immediately after that, and showed a tendency to converge to the voltage value (normalized value 1.0) of the selection signal Ssel over a sufficient time (approximately 15.0 μsec or more). That is, it can be seen that the waveform rounding of the selection line voltage (detection voltage) with respect to the selection signal Ssel increases as the distance from the selection driver 120 increases. Of the pixels PIX connected to the selection line Ls, the selection line in the vicinity of the pixel PIX arranged in the middle j column (a positive integer satisfying 1 <j <m) of the first column and the m column. As shown by the characteristic line SPX (j) in the figure, the voltage showed a changing tendency between the characteristic lines SPX (1) and SPX (m) described above.

  As shown in FIG. 10, the cause of the difference in waveform shape (waveform rounding) of the selection signal Ssel for each column is the distance of the selection line Ls from the selection driver 120, which is the output source of the selection signal Ssel, to each pixel PIX. This is due to the time constant based on the wiring resistance caused and the parasitic capacitance caused by the number of transistor elements provided in the light emission drive circuit DC of each pixel PIX. Here, this time constant corresponds to the load of the pixel PIX in each column, if reduced.

  Here, in order to improve the display characteristics when the display panel is enlarged, when the double-speed driving is performed with the operating frequency being 120 Hz, for example, the length of the writing operation period Twrt allowed for the pixels PIX in each row is Therefore, it is set to a short time of about 10 μsec. From this point of view, when the simulation result shown in FIG. 10 is verified, the selection line is selected at any pixel PIX in the m-th column having the longest distance from the selection driver 120 from the first column in about 10 μsec. It can be seen that the voltage does not reach the voltage value (normalized value 1.0) of the selection signal Ssel and is not set in a stable selection state. In particular, the selection state may be extremely unstable at the position of the pixel PIX in the middle j-th column to the m-th column. That is, in the drive control method to be compared, the transition of the pixel PIX to the selection state is greatly delayed, and the period during which the substantial selection state is set in the writing operation period Twrt becomes relatively short. For this reason, there is a problem in that luminance unevenness and screen flickering due to insufficient writing of display data occur and image quality is deteriorated.

  On the other hand, in the drive control method for the display device 100 according to the present embodiment, as described above, the selection signal Ssel applied from the selection driver 120 to the selection line Ls in the writing operation period Twrt is first applied. The second signal voltage Vsh2 is set to a potential higher than the first signal voltage Vsh1 which is a normal voltage. Then, after the second signal voltage application period Twh2 ends, the first signal voltage Vsh1 which is a normal voltage is switched and set. By applying such a selection signal Ssel to the selection line Ls, it is possible to eliminate the difference in delay of the selection signal Ssel applied to the pixels PIX in each column connected to the selection line Ls.

  FIG. 11 is a diagram illustrating a change in the selection line voltage when the drive control method according to the present embodiment is applied. Here, as described above, in the large-screen display panel, the writing operation period Twrt in the case where double speed driving is performed at an operating frequency of, for example, 120 Hz is approximately 10.0 μsec. In FIG. 11, the second signal voltage Vsh2 (for example, + 18V) higher than the normal voltage is applied as the selection signal Ssel to 6.0 μsec during the write operation period Twrt, and then the first signal voltage Vsh1 that is the normal voltage. It is a simulation result at the time of switching and applying (for example + 15V).

  According to this, as shown in FIG. 11, the selection line voltage (normalized detection voltage in the figure) in the vicinity of the pixel PIX in the first column closest to the selection driver 120 is represented by a characteristic line SP (1) in the figure. As shown, after the start of application of the selection signal Ssel, it rises sharply in a relatively short time (0 to approximately 2.0 μsec), and then exceeds the normalized value 1.0 corresponding to the normal voltage, The change tendency to reach approximately 1.1 was shown at the timing of switching Ssel (6.0 μsec). Thereafter, when the voltage value of the selection signal Ssel is switched to the first signal voltage Vsh1 which is a normal voltage, the selection line voltage has a tendency to rapidly converge to the normalized value 1.0 corresponding to the normal voltage.

  On the other hand, the selection line voltage in the vicinity of the pixel PIX in the m-th column furthest from the selection driver 120 rises relatively slowly after the selection signal Ssel is applied, as shown by the characteristic line SP (m) in the figure, and is selected. There was a tendency for the signal Ssel to converge to approximately 1.0 at the timing (6.0 μsec) immediately after the signal Ssel was switched to the first signal voltage Vsh1. It should be noted that the selection line voltage in the vicinity of the pixel PIX arranged in these intermediate j columns is the characteristic line SP (1) and SP (m) described above, as indicated by the characteristic line SP (j) in the figure. The change tendency between was shown.

  Therefore, according to the drive control method according to the present embodiment, the pixel PIX connected to any position of the selection line Ls at the timing immediately after the selection signal Ssel is switched (the start time of the first signal voltage application period Twh1). It was also found that the selection signal Ssel having a substantially uniform voltage value (first signal voltage Vsh1) is applied to the signal. That is, the rounding of the waveform of the selection signal Ssel with respect to the pixels PIX of each column is improved, and a state in which there is almost no difference in signal delay after the timing when the selection signal Ssel is switched to the first signal voltage Vsh1 is realized.

  Here, the meaning of setting the voltage value of the selection signal Ssel to a constant value will be described. As described above, when the selection signal Ssel is applied in the writing operation period Twrt, the selection signal Ssel is applied to the gates of the transistors Tr11 and Tr12 of the light emission drive circuit DC, and the transistors Tr11 and Tr12 are turned on, Tr13 is set in a diode connection state, and at this time, the gradation voltage Vdata is supplied to the data line Ld, and in accordance with the gradation voltage Vdata from the power supply line La through the transistor Tr13, the contact N12, the transistor Tr12, and the data line Ld. Write current Ia flows. At this time, if the transistor Tr12 has ideal characteristics, the voltage value of the voltage applied to the gate of the transistor Tr12 is not less than a predetermined voltage value necessary for the transistor Tr12 to operate in the saturation region. For example, when the voltage between the source and the drain is a constant voltage, the current value of the current flowing between the source and the drain is constant regardless of the gate voltage.

  However, actually, the characteristics of the transistor Tr12 are not ideal characteristics, and the current value of the current flowing between the source and the drain when the voltage between the source and the drain is a constant voltage in the saturation region depends on the gate voltage. It may have changing characteristics. In such a case, the current value of the write current Ia differs depending on the voltage of the selection line Ls during the write operation period Twrt even if the gradation voltage Vdata is the same. As a result, the amount of charge accumulated in the capacitor Cs is different, and as a result, the current value of the light emission drive current Ib supplied to the organic EL element OEL is different, resulting in variations in light emission luminance and the like. In order to suppress the occurrence of such variations in light emission luminance and obtain a good display quality, the current value of the write current Ia with respect to the gradation voltage Vdata must be a constant value. For this reason, it is preferable to make the voltage value of the selection signal Ssel as constant as possible.

  As described above, in the drive control method for the display device 100 according to the present embodiment, the selection signal Ssel having different voltages is sequentially applied to the selection line Ls in the writing operation period Twrt, and the selection signal is first applied. The voltage of Ssel (second signal voltage Vsh2) is set to be higher than the normal voltage (first signal voltage Vsh1). Thus, according to the present embodiment, there is no difference in signal delay with respect to the pixel PIX in each column regardless of the distance from the selection driver 120 (in other words, the load of the pixel PIX in each column). Since the selection signal Ssel can be applied, generation of uneven brightness and flickering of the screen due to insufficient writing of display data can be suppressed, and good image quality can be realized.

  Such switching control of the voltage value of the selection signal Ssel can set the length of the second signal voltage application period Twh2 based on the simulation experiment as described above. It can also set using the structure provided with the measurement mechanism.

FIG. 12 is a schematic configuration diagram showing a selection line voltage measurement mechanism applied to the display device according to the present embodiment.
The selection line voltage measurement mechanism applied to the display device 100 according to the present embodiment includes, for example, measurement wirings Lms (1) and Lms (m) connected to the selection line Ls, as shown in FIG. And a selection line voltage measurement circuit 170 connected to the measurement wirings Lms (1) and Lms (m).

  The measurement wiring Lms (1) is connected in the vicinity of the position where the pixel PIX in the first column is connected in the selection line Ls of a specific row. Further, the measurement wiring Lms (m) is connected to the vicinity of the position of the selection line Ls where the pixel PIX of the last m-th column having the longest distance from the selection driver 120 is connected. As a result, the timing immediately after the selection signal Ssel applied to the pixel PIX in the first column and the m-th column as the final column is switched via the selection line Ls (the start point of the first signal voltage application period Twh1). ) Is measured by the selected line voltage measurement circuit 170.

  The selection line voltage measurement circuit 170 compares the magnitude relationship of the measured selection line voltage, for example, and outputs the result to the controller 150 as a detection result. Based on the detection result, the controller 150 sets the length of the second signal voltage application period Twh2 in the above-described write operation period Twrt.

  Here, if the second signal voltage application period Twh2 is too long, the voltage applied to the selection line Ls (that is, the pixel PIX) is the normal voltage as shown by the characteristic line SP (1) shown in FIG. The signal voltage Vsh1 may be too high. Therefore, the following feedback control can be used as the setting operation of the second signal voltage application period Twh2.

FIG. 13 is a flowchart showing an example of a method for setting the second signal voltage application period Twh2 applied to the display device according to the present embodiment.
As shown in FIG. 13, the setting operation of the second signal voltage application period Twh2 is first performed by applying a second signal voltage applied during the write operation period Twrt in the selection driver 120 by a selection control signal from the controller 150. The length of the period Twh2 is set to “0” (initial value) (initialization step S101). In this state, a selection signal Ssel is applied from the selection driver 120 to the selection line Ls (selection signal application step S102). Here, in the initial state, since the time of the second signal voltage application period Twh2 is set to zero (Twh2 = 0), only the first signal voltage Vsh1 that is substantially a normal voltage is applied to the selection line Ls. .

  Next, at a predetermined timing after the selection signal Ssel is applied (specifically, any timing within the write operation period Twrt), the selection line voltage measurement circuit 170 at the position of the pixel PIX in the first column and the m-th column. The voltage value of the selected line voltage is individually measured via the measurement wirings Lms (1) and Lms (m) (voltage measurement step S103).

  Next, the selected line voltage measurement circuit 170 compares the measured voltage values and outputs the result to the controller 150 (voltage comparison step S104). Here, the voltage value comparison processing may be executed in the state of an analog voltage, or converted into a digital signal by an analog-digital conversion circuit (hereinafter referred to as “ADC”) (not shown). It may be executed later. Further, the voltage value comparison processing may be executed in the selected line voltage measurement circuit 170 or may be executed in the controller 150. When the voltage value comparison process is executed in the controller 150, the selection line voltage measurement circuit 170 converts a measurement voltage composed of an analog voltage into a digital signal, for example, by an ADC provided therein and outputs the digital signal to the controller 150.

  Next, when there is a difference in the comparison result of the measured voltage (specifically, as shown in FIG. 10, the controller 150 compares the voltage when the measured voltage in the first column is higher than the measured voltage in the m-th column. In step S104: No), a predetermined unit time Ta is added to the second signal voltage application period Twh2 (application period adjustment step S106). Then, the controller 150 generates a switch control signal whose signal width is set so as to correspond to the second signal voltage application period Twh2 to which the unit time Ta is added, and the switch 161 or the selection driver 120 shown in FIG. Output to the internal switch 162. As a result, the process returns to the selection signal application step S102, and first, the Hi voltage 2 is applied to the selection line Ls in the second signal voltage application period Twh2 having the time width to which the unit time Ta is added. The first signal voltage is applied to the selection line Ls during the first signal voltage application period Twh1 up to the end of the insertion operation period Twrt.

  As described above, a series of processing operations including the selection signal application step, the voltage measurement step, the voltage comparison step, and the application period adjustment step are repeatedly executed. In the voltage comparison step S104, the measurement voltage in the first column and the measurement in the m-th column are measured. The time width (signal width) when the voltage is approximately or equal to the first signal voltage Vsh1 and is within a predetermined allowable range (voltage comparison step S104: Yes) is the length of the second signal voltage application period Twh2. And stored in the memory (application period determination step S105). Here, the allowable range is set to a value of 95% to 110% of the voltage value of the first signal voltage Vsh1.

  Accordingly, as shown in FIG. 7, in the write operation period Twrt, by supplying a switch control signal having a signal width stored in the memory from the controller 150 to the switch 161 or 162, first, The Hi voltage 2 is applied to the selection line Ls during a predetermined second signal voltage application period Twh2, and then the first signal voltage is selected during the first signal voltage application period Thh1 up to the end of the write operation period Twrt. Applied to the line Ls.

  In the present embodiment, the configuration (selection line voltage measurement mechanism) for realizing the drive control method shown in the flowchart of FIG. 13 is not limited to that shown in FIG. A configuration equivalent to this embodiment (FIG. 12) and further configuration will be described in detail in a third embodiment (see FIGS. 16 and 17) described later.

<Second Embodiment>
Next, a display device (light emitting device) and a drive control method thereof according to a second embodiment of the present invention will be described with reference to the drawings.

  In the first embodiment described above, it is assumed that the distance from the end of the display panel 110 to the selection driver 120 is the same in each row, and the length of the second signal voltage application period Twh2 in the write operation period Twrt. The case of setting is described. That is, in the first embodiment, as shown in FIG. 7, the lengths of the second signal voltage application periods Twh2 in the first to nth rows are all set to be the same. On the other hand, in the second embodiment, there is a display device drive control method corresponding to the case where the length of the connection wiring (leading wiring) from the end of the display panel 110 to the selection driver 120 is different. It is characterized by that.

  FIG. 14 is a schematic block diagram illustrating an example of a display device according to the second embodiment. Here, only the configuration peculiar to the present embodiment is shown in the overall configuration of the display device shown in FIG. 1, and other configurations are omitted. FIG. 15 is a timing chart showing the voltage value setting operation of the selection signal in the selection driver applied to the display device according to the present embodiment.

  In a display device having a large-screen display panel, the size of an IC chip (driver chip) equipped with a driver function is generally smaller than the screen size of the display panel. In such a case, the distance from the end of the selection line arranged in each row of the display panel to the selection driver is not uniform. For example, as shown in FIG. 14, in the configuration in which the selection driver 120 is arranged biased to the outer lower side (final row side) in the row direction (left-right direction in the drawing) of the display panel 110, the selection driver 120 and the first row The length of the routing line Lrt (1) connecting the selection line Ls (1) is significantly larger than the length of the routing line Lrt (n) connected to the selection line Ls (n) in the nth row. become longer. That is, the distance from the selection driver 120 to the pixel PIX connected to the selection line Ls is different for each row.

  As described in the first embodiment, the waveform rounding of the selection signal Ssel is based on the wiring resistance caused by the wiring length of the selection line Ls and the parasitic capacitance caused by the number of transistor elements provided in the pixel PIX. Influenced by time constant. As shown in FIG. 14, even when the wiring length of the selection line Ls including the routing wiring is different for each row, the time constants in the selection line Ls for each row are also different. For this reason, the waveform rounding of the selection signal Ssel applied to the selection line Ls (1) in the first row becomes more significant than the selection line Ls (n) in the nth row, and the selection line Ls ( Insufficient writing tends to occur in the pixel PIX connected to 1).

  Therefore, in the present embodiment, as shown in FIG. 15, in the write operation period Twrt of each row, the length of the second signal voltage application period Twh2 for applying the Hi voltage 2 to the selection line Ls is included in the lead wiring. The selection line Ls is set to vary depending on the wiring length (that is, the load size). Specifically, as shown in FIG. 15, the second signal voltage application period Twh2 in the selection signal Ssel applied to the selection line Ls (1) of the first row having the longest wiring length including the routing wiring Lrt (1). The length of (1) is set to the longest. Then, the length of the second signal voltage application period Twh2 (i) of the i-th row after the second selection line Ls (2) is set to be gradually shortened and includes the lead wiring Lrt (n). The length of the second signal voltage application period Twh2 (n) in the selection signal Ssel applied to the nth selection line Ls (n) with the shortest wiring length is set to be the shortest. Accordingly, the length of the first signal voltage application period Twh1 (1) in the selection signal Ssel applied to the selection line Ls (1) of the first row is set to be the shortest, and the selection line of the nth row is selected. The length of the first signal voltage application period Twh1 (n) in the selection signal Ssel applied to Ls (n) is set to be the longest.

  As a method for setting the second signal voltage application period Twh2 and the first signal voltage application period Twh1, the drive control method (see the flowchart of FIG. 13) shown in the first embodiment described above is used. A series of times when the measurement voltage in the first column and the measurement voltage in the m-th column are equal and the difference between the two is eliminated (becomes 0) is determined as the length of the second signal voltage application period Twh2. These processing operations (steps S101 to S106) are set by executing each row.

  As described above, according to the drive control method of the display device according to the present embodiment, the selection signals having different voltage values are sequentially applied to the selection line during the writing operation period, and the selection signal to be applied first is applied. Adjust the period. Thus, according to the present embodiment, a selection signal having no difference in signal delay can be applied to the pixel PIX in each column regardless of the distance from the selection driver in the selection line of each row. It is possible to achieve good image quality by suppressing the occurrence of luminance unevenness and screen flicker due to insufficient data writing.

  In the present embodiment, the drive control method including the series of processing operations shown in FIG. 13 is executed for all the rows of the display panel 110, and the second signal voltage application period Twh2 having a different length for each row is set. It is not limited to what is set. In the present embodiment, for example, the series of processing operations shown in FIG. 13 are executed only for the selection lines Ls (1) and Ls (n) in the first and nth rows, and the first and nth rows are executed. Based on the length of the second signal voltage application period Twh2 set in the selection lines Ls (1), Ls (n) of the second line (for example, by proportional distribution), the second signal voltage application period of the selection lines Ls in other rows It may be determined by calculating the length of Twh2.

  Also in this embodiment, as in the first embodiment described above, the first embodiment is configured as a configuration (selection line voltage measuring mechanism) for realizing the drive control method shown in the flowchart of FIG. A configuration equivalent to (see FIG. 12) or a configuration shown in a third embodiment (see FIGS. 16 and 17) described later can be applied.

<Third Embodiment>
Next, a display device (light emitting device) and a drive control method thereof according to a third embodiment of the present invention will be described with reference to the drawings.

  In the above-described first and second embodiments, the second signal included in the write operation period Twrt of each row by the drive control method including the series of processing operations (steps S201 to S206) shown in the flowchart of FIG. The method for setting the length of the voltage application period Twh2 has been described. That is, in the first and second embodiments, a method of controlling only the length of the second signal voltage application period Twh2 is shown as a method of suppressing the waveform rounding of the selection signal Ssel described above. On the other hand, in the third embodiment, in addition to the length of the second signal voltage application period Twh2, the voltage value Vsh2 of the selection signal Ssel applied during the second signal voltage application period Twh2 is appropriately changed and controlled. It has the method to do.

  In the first and second embodiments described above, the configuration in which the selection driver 120 is formed as a single IC chip and is independently arranged around the display panel 110 is shown. Incidentally, in recent years, it has been generally performed that different driver functions of peripheral circuits of a display device are mounted on a single IC chip and arranged in the vicinity of a display panel. In the third embodiment described below, a configuration in which a single IC chip (one-chip driver) having functions of a selection driver and a data driver is arranged around the display panel will be described. In addition, in the third embodiment, the selection line voltage measurement mechanism for measuring the voltage value of the selection line also has the same configuration as that of the first and second embodiments (see FIG. 12) and is further different. The configuration will be described.

(Display device)
First, a schematic configuration of a display device (light emitting device) according to the present embodiment will be described with reference to the drawings.

  16 and 17 are schematic block diagrams illustrating a configuration example of the display device according to the third embodiment. Here, only the configuration peculiar to the present embodiment is shown in the overall configuration of the display device shown in FIG. 1, and other configurations are omitted.

(Display device)
The display device 100 according to the third embodiment shown in FIG. 16A includes a selection / data 1 chip driver 180 arranged outside the display panel 110 in the column direction (downward in the drawing), and a routing wiring Lrt ( Lrt (1) to Lrt (n)), measurement wirings Lms (1) and Lms (m), and an ADC 171. The selection / data 1-chip driver 180 has both the functions of the selection driver 120 and the data driver 140 shown in the first embodiment described above mounted on a single chip. The lead wiring Lrt connects the selection line Ls (Ls (1) to Ls (n)) disposed on the display panel 110 to the selection / data 1 chip driver 180. The measurement wirings Lms (1) and Lms (m) are for measuring the selected line voltage at a predetermined position of the selected line, similarly to the configuration shown in the first embodiment (see FIG. 12). . The ADC 171 converts a selection line voltage composed of analog voltages individually measured via the measurement wirings Lms (1) and Lms (m) into a digital signal, and outputs the digital signal to the controller 150 as a detection result.

  Note that the ADC 171 according to the present embodiment may be provided independently as a separate configuration from the selection / data 1 chip driver 180, or the ADC 171 may select / data as shown in FIG. It may be provided inside the one-chip driver 180. Here, the ADC 171 shown in FIGS. 16A and 16B corresponds to the selection line voltage measurement circuit 170 shown in the first embodiment.

  In addition, the display device 100 shown in FIG. 17 is not configured in which the measurement wirings Lms (1), Lms (m) and the ADC 171 are connected in advance as shown in FIG. Only the measurement terminal pads Pms (1) and Pms (m) formed so as to be able to detect the voltage of the selection line Ls from the outside are provided. The probe needles connected to the ADC 172 come into contact with the measurement terminal pads Pms (1) and Pms (m) when detecting the voltage of the selection line Ls. As a result, the ADC 172 converts the selection line voltage composed of the analog voltage measured through the measurement terminal pads Pms (1) and Pms (m) into a digital signal and outputs the digital signal to the controller 150. Here, the ADC 172 shown in FIG. 17 corresponds to the selection line voltage measurement circuit 170 shown in the first embodiment described above, and is provided, for example, in a prober equipped with a probe needle.

  In the display device 100 including the ADC 171 shown in FIGS. 16A and 16B, the selection line voltage measurement mechanism is integrated, and therefore a drive control method (second signal voltage application period described later) is incorporated. It is possible to readjust the waveform of the selection signal Ssel at any timing by executing Twh2 and its voltage value setting operation) at any timing. Therefore, the display device having this configuration is effective when the display image quality is expected to deteriorate over time. On the other hand, in the display device shown in FIG. 17, since the measurement mechanism for the selected line voltage is not incorporated in the display device, the device configuration and drive control of the display device can be simplified. Therefore, the display device having this configuration is effective when the drive control method (second signal voltage application period Twh2 and its voltage value setting operation) to be described later is executed only once before the display device is shipped. .

  Incidentally, in the display device having the configuration shown in FIGS. 16 and 17, the selection / data 1 chip driver 180 is arranged below the display panel 110. In this case, the routing wiring Lrt connected between the selection / data 1 chip driver 180 and the end of the display panel 110 is connected to the selection line Ls in the upper row of the display panel 110, and the display panel 110 side. Will be greatly detoured. Therefore, there is a large difference in wiring length between the first selection line Ls (1) and the last nth selection line Ls (n). As a result, as in the second embodiment described above, the wiring length (that is, the magnitude of the load) of the selection line Ls including the routing wiring Lrt differs from row to row, and n rows close to the selection / data 1 chip driver 180. Compared to the selection line Ls (n) of the eye, the selection signal Ssel applied to the selection line Ls (1) of the first row far from the selection / data 1 chip driver 180 has a larger waveform rounding. Delay becomes noticeable.

  Therefore, in the present embodiment, as a method for suppressing the waveform rounding of the selection signal Ssel, in addition to the length of the second signal voltage application period Twh2, the voltage of the selection signal Ssel applied in the second signal voltage application period Thh2 The value Vsh2 is also controlled as appropriate. In order to realize such adjustment setting of the second signal voltage application period Twh2 and voltage value change setting of the selection signal Ssel, the present embodiment has the following configuration (voltage value setting mechanism). Yes.

FIG. 18 is a schematic diagram illustrating a configuration example of a voltage value setting mechanism including a selection driver function unit of a selection / data 1-chip driver applied to the display device according to the present embodiment.
The voltage value setting mechanism shown in FIG. 18A is a high-level operation voltage (Hi voltage; expressed as “Hi power supply” in the figure) supplied to the selection driver function unit 120A of the selection / data 1 chip driver. The switch 161 provided outside is set to either the Hi power source 1 (Hi voltage 1; for example, +15 V) or the Hi power source 2 (Hi voltage 2) set by the DAC 191. Here, the DAC 191 is connected to the Hi power source 3 having a voltage value equal to or higher than the maximum voltage set as the Hi power source 2, for example, and is arbitrarily set by a DAC control signal that is a type of selection control signal supplied from the controller 150. A Hi voltage 2 having a voltage value is generated and supplied to the switch 161. Here, the DAC control signal supplied from the controller 150 includes a digital value for defining the voltage Vsh2 of the selection signal Ssel applied to the selection line Ls in the second signal voltage application period Twh2. This digital value is acquired when determining the second signal voltage application period Twh2 and the voltage Vsh2 of the second signal voltage in a drive control method (voltage value setting operation) described later. In addition, the switch 161 is switched and controlled to connect either the Hi power source 1 or the Hi power source 2 to the selected driver function unit 120 </ b> A by a switch control signal that is a type of selection control signal supplied from the controller 150. Note that a Lo power supply is connected to the selected driver function unit 120A, and a Lo voltage (for example, −15 V) is always supplied as an operating voltage on the low level side.

  Moreover, the voltage value setting mechanism can also apply a configuration as shown in FIG. The voltage value setting mechanism shown in FIG. 18B has a configuration in which the switch 161 and the DAC 191 shown in FIG. 18A are provided inside the selection driver function unit 120A as the switch 162 and the DAC 192. That is, the Hi power source 1 and the Hi power source 3 are connected to the selected driver function unit 120A, and the Hi voltage 1 (for example, + 15V) and the Hi voltage 3 are supplied as the high-level operation voltage. The DAC 192 generates a Hi voltage 2 having an arbitrary voltage value based on the digital value for defining the voltage value included in the DAC control signal supplied from the controller 150 to the selected driver function unit 120A. 162. The switch 162 is controlled to be switched by a switch control signal supplied from the controller 150 to the selection driver 120, selects either the Hi power source 1 or the Hi power source 2, and uses it as the internal Hi power source.

  By the voltage value setting mechanism having such a configuration, the selection is performed based on the selection control signal (switch control signal, DAC control signal) from the controller 150 during the writing operation period Twrt in the display drive operation (drive control method). The driver function unit 120A first applies a selection signal Ssel of an arbitrary voltage (second signal voltage Vsh2) higher than normal (design value) to the selection line Ls, and then the normal voltage (first signal voltage Vsh1; For example, a selection signal Ssel of + 15V) is applied.

(Display device drive control method)
Next, a drive control method in the display device according to the present embodiment will be described with reference to the drawings.

  FIG. 19 is a flowchart illustrating an example of a method for setting the second signal voltage application period Twh2 and the voltage Vsh2 applied to the display device according to the present embodiment. Here, the description of the processing operation equivalent to that of the above-described first embodiment (see FIG. 13) is simplified. FIG. 20 is a waveform diagram for explaining a selection signal set by the drive control method according to the present embodiment.

  As shown in FIG. 19, the second signal voltage application period Twh2 and its voltage setting operation are first performed by a DAC control signal from the controller 150 in the DAC 191 or 192, where the Hi voltage 1 (Hi power supply 1), which is a normal voltage. A Hi voltage 2 (Hi power supply 2) set to an arbitrary voltage (initial value) higher than the voltage is generated (voltage initialization step S201). Here, the voltage of the Hi voltage 2 that is the initial value is set to a voltage value that is higher by, for example, a unit voltage Va described later than the Hi voltage 1 that is a normal voltage. Then, according to a switch control signal from the controller 150, the switch 161 or 162 selects the Hi voltage 2 set to the initial value as the Hi voltage (Hi power supply, internal Hi power supply). As a result, the second signal voltage Vsh2 of the selection signal Ssel is set to an initial voltage based on the Hi voltage 2.

  Next, in the selection driver function unit 120A, the length of the second signal voltage application period Twh2 set during the write operation period Twrt is set to “0” (initial value) by the selection control signal from the controller 150 ( Application time initialization step S202). In this state, the selection driver function unit 120A applies the selection signal Ssel to the selection line Ls (selection signal application step S203). Here, in the initial state, since the time of the second signal voltage application period Twh2 is set to zero (Twh2 = 0), only the first signal voltage that is substantially a normal voltage is applied to the selection line Ls.

  Next, at a predetermined timing after the selection signal Ssel is applied (specifically, an arbitrary timing within the write operation period Twrt), the pixels PIX in the first column and the m-th column connected to the arbitrary selection line Ls. The voltage value at the timing immediately after the selection signal Ssel of the selected line at the position is switched (at the start time of the second signal voltage application period Twh1) is used for the measurement wirings Lms (1) and Lms (m) or for measurement. Individual measurements are made via the terminal pads Pms (1) and Pms (m). The voltage value composed of the measured analog voltage is converted into a digital signal by the ADC 171 or 172 and output to the controller 150 as a detection result (voltage measurement step S204).

  Next, the controller 150 compares the magnitude relationship of the digital signals corresponding to the selected line voltage acquired via the ADC 171 or 172 (voltage comparison step S205). In the voltage comparison step S205, when there is a difference between the measured voltage comparison results (voltage comparison step S205: No), the controller 150 adds a fixed unit time Ta to the second signal voltage application period Twh2. (Application period adjustment step S207). That is, the length (time) of the second signal voltage application period Twh2 is variably set in the signal waveform of the selection signal Ssel shown in FIG.

  Next, it is determined whether or not the second signal voltage application period Twh2 to which the unit time Ta is added is shorter than the write operation period Twrt (application period determination step S208). When the second signal voltage application period Twh2 is shorter than the write operation period Twrt (Twh2 <Twrt, application period determination step S208: Yes), the controller 150 causes the second signal voltage application period to which the unit time Ta is added. A switch control signal having a signal width set so as to correspond to Twh2 is generated and output to the switch 161 or 162. As a result, the process returns to the selection signal application step S203, and first, the second signal voltage Vsh2 is applied to the selection line Ls in the second signal voltage application period Twh2 having a time width obtained by adding the unit time Ta, and then The first signal voltage is applied to the selection line Ls during the first signal voltage application period Twh1 up to the end of the write operation period Twrt. Thereafter, the processing operations after step S204 described above are executed.

  On the other hand, in the application period determination step S208, when the second signal voltage application period Twh2 is equal to or longer than the write operation period Twrt (application period determination step S208: No). The controller 150 adds a constant unit voltage Va to the voltage value of the Hi voltage 2 (voltage value adjustment step S209). That is, the voltage value of the Hi voltage 2 is variably set in the signal waveform of the selection signal Ssel shown in FIG. Then, the controller 150 generates a DAC control signal in which a digital value is set so as to correspond to the voltage value of the Hi voltage 2 to which the unit voltage Va is added, and outputs the DAC control signal to the DAC 191 or 192. As a result, the process returns to the application time initialization step S202 again, and after setting the length of the second signal voltage application period Twh2 to “0”, the selection signal Ssel is applied to the selection line Ls from the selection driver function unit 120A. Thereafter, the processing operations after step S203 described above are executed.

  In this way, the above-described series of processing operations are repeatedly executed, and in the voltage comparison step S205, the measurement voltage in the first column and the measurement voltage in the m-th column are approximate or equal to the first signal voltage Vsh1, and a predetermined allowable range. The time width (signal width) when the value is within the range (voltage comparison step S205: Yes) is determined as the length of the second signal voltage application period Twh2, and the digital corresponding to the voltage value of the Hi voltage 2 at this time The value is stored in the memory (application period / voltage determination step S206). Here, the allowable range is set to a value of 95% to 110% of the voltage value of the first signal voltage Vsh1.

  As a result, in the write operation period Twrt, the switch control signal having the signal width stored in the memory is supplied from the controller 150 to the switch 161 or 162 and is stored in the memory for the DAC 191 or 192. By supplying a DAC control signal including a digital value corresponding to the voltage value, first, a second signal voltage Vsh2 having a predetermined voltage is selected during a predetermined second signal voltage application period Twh2, as shown in FIG. The first signal voltage, which is a normal voltage, is applied to the selection line Ls during the first signal voltage application period Twh1 that is applied to the line Ls and then until the end of the write operation period Twrt.

  As described above, according to the drive control method of the display device according to the present embodiment, the selection signals having different voltage values are sequentially applied to the selection line during the writing operation period, and the voltage of the selection signal to be applied first is applied. Adjust the value and application period. As a result, according to the present embodiment, the selection signal having no difference in signal delay with respect to the pixel PIX in each column regardless of the distance from the selection driver (selection / data 1 chip driver) in the selection line of each row. Therefore, it is possible to suppress the occurrence of uneven brightness and flickering of the screen due to insufficient writing of display data, thereby realizing good image quality.

<Application examples of electronic devices>
Next, electronic devices to which the display device and the drive control method according to each embodiment described above are applied will be described.

  As shown in the first to third embodiments described above, the display device 100 including the display panel 110 having the light emitting element composed of the organic EL element OEL in each pixel PIX is a large screen such as a thin television or a monitor. The present invention can be applied to an electronic apparatus including the display device.

FIG. 21 is a perspective view showing a configuration example of a thin television to which the display device (light emitting device) according to the first to third embodiments is applied.
In FIG. 21, the flat-screen television 200 roughly includes a main body 201, a display unit 202 including the display device 100 including the display panel 110 of the present embodiment, and an operation controller (remote controller) 203. . In this case, in the display unit 202, the light emitting element of each pixel of the display panel 110 can emit light with an appropriate luminance gradation according to the image data, so that a good and uniform image quality can be realized.

DESCRIPTION OF SYMBOLS 100 Display apparatus 110 Display panel 120 Selection driver 120A Selection driver function part 130 Power supply driver 140 Data driver 150 Controller 161, 162 Switch 170 Selection line voltage measurement circuit 171, 172 ADC
180 selection / data 1 chip driver 191, 192 DAC
PIX pixel DC light emission drive circuit OEL Organic EL element

Claims (15)

A light-emitting drive circuit having a light-emitting element, a drive transistor for controlling a current supplied to the light-emitting element, and a switching transistor for controlling the operation of the drive transistor, and connected to a scanning line connected to the switching transistor; A light emission driving device that drives a plurality of pixels arranged along an extending direction of the scanning line to control light emission of the light emitting element of each pixel;
A selection drive circuit configured to apply a selection signal to one end of the scanning line in a predetermined signal application period and set the selection state to operate the switching transistor of each pixel;
The selection signal is set to a first signal voltage during a first period during the signal application period, and has a higher potential than the first signal during a second period prior to the first period during the signal application period. Having a second signal voltage,
The time of the second period and the voltage value of the second signal voltage are the one end of the scan line at the start of the first period when the selection signal is applied to one end of the scan line. A first voltage value composed of a voltage value of the scanning line in the vicinity of the first pixel at a position where the distance from the first position is the shortest, and a second position where the distance from one end of the scanning line is the longest. The second voltage value composed of the voltage value of the scanning line in the vicinity of the pixel is set to a value within an allowable range, and the allowable range is 95% to 110% of the voltage value of the first signal voltage. The light emission drive device characterized by the above-mentioned.   The voltage of the selection signal is set corresponding to the operating voltage, and when the selection signal is set to the first signal voltage, the operating voltage is set to the first setting voltage, and the selection signal is set to the second signal voltage. The light emission drive device according to claim 1, further comprising a voltage switching circuit that switches the operating voltage to a second set voltage having a higher potential than the first signal voltage when the voltage is set.   The light emission driving device according to claim 1, further comprising a voltage measurement circuit connected to the scanning line and measuring the first voltage value and the second voltage value.   The voltage value of the second signal voltage is set to a fixed value, the time of the second period is set to a variable value, and the first voltage value and the second voltage measured by the voltage measurement circuit The light emission drive device according to claim 3, further comprising a control circuit that sets the time of the second period based on a comparison of values.   Based on the comparison between the first voltage value and the second voltage value measured by the voltage measurement circuit, wherein the time of the second period and the voltage value of the second signal voltage are set to variable values. The light emission driving device according to claim 3, further comprising a control circuit that sets a time of the second period and a voltage value of the second signal voltage. A plurality of pixels each having a light emitting element, a light emission driving circuit having a driving transistor for controlling a current supplied to the light emitting element, and a switching transistor for controlling an operation of the driving transistor, and connected to the switching transistor of the plurality of pixels A plurality of scanning lines, and a light emitting panel in which each pixel is arranged along an extending direction of each scanning line;
A light emission driving device for driving the light emitting elements of the plurality of pixels of the light emitting panel;
With
The light emission driving device applies a selection signal to one end of each scanning line and operates the switching transistor of each pixel during a writing operation period in which a gradation signal based on image data is written to each pixel. With a selection drive circuit to set the state,
The selection signal is set to a first signal voltage during a first period during the write operation period, and from the first signal voltage during a second period prior to the first period during the write operation period. Set to a high potential second signal voltage,
The time of the second period and the voltage value of the second signal voltage are the same as the scanning line at the start of the first period when the selection signal is applied to one end of the one scanning line. The first voltage value of the scanning line in the vicinity of the first pixel at the shortest distance from one end of the second pixel and the second voltage of the second pixel at the longest distance from the one end of the scanning line. The second voltage value of the scanning line in the vicinity is set to a value within an allowable range, and the allowable range is 95% to 110% of the voltage value of the first signal voltage. A light emitting device characterized.   The voltage of the selection signal is set corresponding to the operating voltage, and when the selection signal is set to the first signal voltage, the operating voltage is set to the first setting voltage, and the selection signal is set to the second signal voltage. The light emitting device according to claim 6, further comprising: a voltage switching circuit that switches the operating voltage to a second set voltage having a higher potential than the first signal voltage when set to ≦.   The light-emitting device according to claim 6, further comprising a voltage measurement circuit connected to the scanning line and measuring the first voltage value and the second voltage value.   The voltage value of the second signal voltage is set to a fixed value, the time of the second period is set to a variable value, and the first voltage value and the second voltage measured by the voltage measurement circuit The light-emitting device according to claim 8, further comprising a control circuit that sets the time of the second period based on a comparison of values.   Based on the comparison between the first voltage value and the second voltage value measured by the voltage measurement circuit, wherein the time of the second period and the voltage value of the second signal voltage are set to variable values. The light emitting device according to claim 8, further comprising a control circuit that sets a time period of the second period and a voltage value of the second signal voltage.   The light emitting device according to claim 6, wherein the light emitting element is an organic electroluminescence element.   An electronic apparatus comprising the light-emitting device according to claim 6 mounted thereon. A plurality of pixels each including a light emitting drive circuit having a light emitting element, a driving transistor for controlling a current supplied to the light emitting element, and a switching transistor for controlling an operation of the driving transistor; and connecting to the switching transistor of the plurality of pixels A plurality of scanning lines, and each of the pixels includes a light emitting panel arranged along an extending direction of the scanning lines, and the light emission of the plurality of pixels at a luminance gradation according to image data A drive control method of a light emitting device for causing an element to emit light,
A setting step of setting a voltage value of the first signal voltage, a voltage value of the second signal voltage having a potential higher than the first signal voltage, and a time of the second period;
A selection signal for operating the switching transistor of each pixel at one end of each scanning line in a first period during a writing operation period in which a gradation signal based on the image data is written to each pixel. A first signal voltage application step of setting and applying a voltage value to the first signal voltage;
A second signal that is applied to one end of each scanning line with the voltage value of the selection signal set to the second signal voltage in the second period prior to the first period in the writing operation period. Voltage application step;
Including
In the setting step, the time of the second period and the voltage value of the second signal voltage are converted into one end of one scanning line by the second signal voltage step and the first signal voltage step. A first voltage value of the scanning line in the vicinity of the first pixel at a position where the distance from one end of the scanning line is the shortest at the start of the first period when applied; The second voltage value of the scanning line in the vicinity of the second pixel at the position where the distance from one end of the scanning line is the longest is set to a value within an allowable range, and the allowable range is A drive control method for a light emitting device, characterized in that the value is 95% to 110% of the voltage value of the first signal voltage. The setting step includes
An initialization step of setting the time of the second period to a predetermined initial value;
A selection signal applying step of applying the selection signal to one end of the scanning line;
A voltage measuring step for measuring the first voltage value and the second voltage value;
A voltage comparison step of comparing the measured first voltage value and the second voltage value with the first signal voltage;
An application time adjustment step of adjusting the time of the second period based on the comparison result in the voltage comparison step;
In the voltage comparison step, the time of the second period when the first voltage value and the second voltage value are within the allowable range is determined as the second signal voltage application step. An application period determining step for setting the period of two periods;
The drive control method of the light-emitting device according to claim 13. The setting step includes
A voltage initialization step of setting the voltage value of the second signal voltage to a predetermined initial value;
An application time initialization step of setting the time of the second period to a predetermined initial value;
A selection signal applying step of applying the selection signal to one end of the scanning line;
A voltage measuring step for measuring the first voltage value and the second voltage value;
A voltage comparison step of comparing the measured first voltage value and the second voltage value with the first signal voltage;
An application time adjustment step of adjusting the time of the second period based on the comparison result in the voltage comparison step;
An application time determination step of determining whether or not the time of the second period is shorter than the write operation period;
A voltage value adjusting step for adjusting a voltage value of the second signal voltage based on a determination result in the application time determining step;
In the voltage comparison step, the time of the second period and the voltage value of the second signal voltage when the first voltage value and the second voltage value are within the allowable range, An application period / voltage determination step for setting the time of the second period and the voltage value of the second signal voltage in the second signal voltage application step;
The drive control method of the light-emitting device according to claim 13.

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