JP5359045B2 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
JP5359045B2
JP5359045B2 JP2008158774A JP2008158774A JP5359045B2 JP 5359045 B2 JP5359045 B2 JP 5359045B2 JP 2008158774 A JP2008158774 A JP 2008158774A JP 2008158774 A JP2008158774 A JP 2008158774A JP 5359045 B2 JP5359045 B2 JP 5359045B2
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JP
Japan
Prior art keywords
wiring
plating
insulating substrate
hole
corner
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2008158774A
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English (en)
Japanese (ja)
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JP2010003722A (ja
JP2010003722A5 (enExample
Inventor
勇一 岡田
祐子 青木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nichia Corp
Original Assignee
Nichia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nichia Corp filed Critical Nichia Corp
Priority to JP2008158774A priority Critical patent/JP5359045B2/ja
Publication of JP2010003722A publication Critical patent/JP2010003722A/ja
Publication of JP2010003722A5 publication Critical patent/JP2010003722A5/ja
Application granted granted Critical
Publication of JP5359045B2 publication Critical patent/JP5359045B2/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)
  • Semiconductor Lasers (AREA)
JP2008158774A 2008-06-18 2008-06-18 半導体装置およびその製造方法 Active JP5359045B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008158774A JP5359045B2 (ja) 2008-06-18 2008-06-18 半導体装置およびその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008158774A JP5359045B2 (ja) 2008-06-18 2008-06-18 半導体装置およびその製造方法

Publications (3)

Publication Number Publication Date
JP2010003722A JP2010003722A (ja) 2010-01-07
JP2010003722A5 JP2010003722A5 (enExample) 2011-07-28
JP5359045B2 true JP5359045B2 (ja) 2013-12-04

Family

ID=41585228

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008158774A Active JP5359045B2 (ja) 2008-06-18 2008-06-18 半導体装置およびその製造方法

Country Status (1)

Country Link
JP (1) JP5359045B2 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5537385B2 (ja) * 2010-11-04 2014-07-02 スタンレー電気株式会社 サイドビュー型半導体発光装置およびその製造方法
US9755105B2 (en) 2015-01-30 2017-09-05 Nichia Corporation Method for producing light emitting device
JP6176302B2 (ja) * 2015-01-30 2017-08-09 日亜化学工業株式会社 発光装置の製造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3475757B2 (ja) * 1997-12-01 2003-12-08 松下電器産業株式会社 面実装型光電変換装置作製用基板
US7244965B2 (en) * 2002-09-04 2007-07-17 Cree Inc, Power surface mount light emitting die package
JP5073946B2 (ja) * 2005-12-27 2012-11-14 新光電気工業株式会社 半導体装置および半導体装置の製造方法
JP2007235003A (ja) * 2006-03-03 2007-09-13 Ngk Spark Plug Co Ltd 発光素子収納用パッケージ
JP5103805B2 (ja) * 2006-06-27 2012-12-19 日亜化学工業株式会社 発光装置及びその製造方法

Also Published As

Publication number Publication date
JP2010003722A (ja) 2010-01-07

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