JP5347409B2 - Solar cell and manufacturing method thereof - Google Patents

Solar cell and manufacturing method thereof Download PDF

Info

Publication number
JP5347409B2
JP5347409B2 JP2008250723A JP2008250723A JP5347409B2 JP 5347409 B2 JP5347409 B2 JP 5347409B2 JP 2008250723 A JP2008250723 A JP 2008250723A JP 2008250723 A JP2008250723 A JP 2008250723A JP 5347409 B2 JP5347409 B2 JP 5347409B2
Authority
JP
Japan
Prior art keywords
layer
type
junction
amorphous silicon
solar cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2008250723A
Other languages
Japanese (ja)
Other versions
JP2010080887A (en
Inventor
孝博 三島
仁 坂田
英治 丸山
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP2008250723A priority Critical patent/JP5347409B2/en
Publication of JP2010080887A publication Critical patent/JP2010080887A/en
Application granted granted Critical
Publication of JP5347409B2 publication Critical patent/JP5347409B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L31/00Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H01L31/0745Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L31/00Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0224Electrodes
    • H01L31/022408Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441Electrode arrangements specially adapted for back-contact solar cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solar cell capable of improving characteristics of the solar cell, and to provide a method of manufacturing the same. <P>SOLUTION: The solar cell 10 includes an in junction 20 and an ip junction 30 formed on a backside. An i-type amorphous silicon layer 30i of the ip junction 30 covers one end in a second direction of an n-type amorphous silicon layer 20n. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a back junction solar cell and a manufacturing method thereof.

  Solar cells are expected as a new energy source because they can directly convert clean and infinitely supplied sunlight into electricity.

Conventionally, a so-called back junction solar cell including a plurality of n-type semiconductor layers and a plurality of p-type semiconductor layers formed on the back surface of a semiconductor substrate has been proposed (see, for example, Patent Document 1). Each n-type semiconductor layer and each p-type semiconductor layer are alternately formed along a predetermined direction.
JP 2006-523025 A

  Here, in order to suppress recombination of photogenerated carriers inside the semiconductor substrate, it is preferable to narrow the interval between the n-type semiconductor layer and the p-type semiconductor layer. Thereby, a solar cell characteristic can be improved.

  However, when the interval between the n-type semiconductor layer and the p-type semiconductor layer is narrowed, the n-type semiconductor layer and the p-type semiconductor layer may come into contact with each other. In this case, since a low-quality diode is formed at the contact portion between the n-type semiconductor layer and the p-type semiconductor layer, there is a problem that the solar cell characteristics are deteriorated.

  This invention is made | formed in view of the above-mentioned problem, and it aims at providing the solar cell which can improve a solar cell characteristic, and its manufacturing method.

  A solar cell according to a feature of the present invention includes a semiconductor substrate having a light receiving surface and a back surface provided on the opposite side of the light receiving surface, and a substantially intrinsic first i-type semiconductor layer sequentially formed on the back surface. A first semiconductor junction composed of one conductivity type semiconductor layer having one conductivity type, a substantially intrinsic second i-type semiconductor layer sequentially formed on the back surface, and another conductivity type having another conductivity type Each of the first semiconductor junction and the second semiconductor junction is formed along a first direction, and the second i-type semiconductor layer includes: The gist is to cover one end of the one-conductivity-type semiconductor layer in a second direction substantially orthogonal to the first direction.

  According to the solar cell according to the feature of the present invention, the other-conductivity-type semiconductor layer of the second semiconductor junction is electrically separated from the one-conductivity-type semiconductor layer of the first semiconductor junction by the second i-type semiconductor layer. Is done. Therefore, it is possible to suppress the formation of a low-quality diode between the one conductivity type semiconductor layer and the other conductivity type semiconductor layer. Further, since there is no need to provide a gap between the first semiconductor junction and the second semiconductor junction, the interval between the first semiconductor junction and the second semiconductor junction can be reduced. Therefore, recombination of photogenerated carriers inside the semiconductor substrate can be suppressed. As a result, the solar cell characteristics can be improved.

  In the solar cell according to the feature of the present invention, one end portion in the second direction of the first semiconductor junction has a slope inclined toward the semiconductor substrate, and the second i-type semiconductor layer covers the slope. It may be.

  In the solar cell according to the feature of the present invention, the first i-type semiconductor layer may cover one end of the one-conductivity-type semiconductor layer in the second direction.

  A method for manufacturing a solar cell according to a feature of the present invention is a method for manufacturing a solar cell including a semiconductor substrate having a light receiving surface and a back surface provided on the opposite side of the light receiving surface, and is substantially intrinsic on the back surface. A step of sequentially forming a first i-type semiconductor layer and a one-conductivity-type semiconductor layer having one conductivity type, a step of forming a cover layer on the one-conductivity-type semiconductor layer, and a part of the cover layer in a first direction Forming a first groove by removing the first conductive layer, and forming a second groove extending from the first groove toward the semiconductor substrate by removing the one-conductivity-type semiconductor layer exposed in the first groove. A step of sequentially forming another intrinsic i-type semiconductor layer and another conductivity type semiconductor layer having another conductivity type on the bottom and side surfaces of the second groove, and a step of removing the covering layer In the step of forming the second i-type semiconductor layer, By the body layer, and summarized in that covering the one end portion in a first direction and a second direction substantially perpendicular of the opposite conductivity type semiconductor layer.

  In the method for manufacturing a solar cell according to the feature of the present invention, in the step of forming the second groove, a portion provided between the one end portion in the second direction of the coating layer and the semiconductor substrate in the one-conductive semiconductor layer is formed. It may be removed.

  ADVANTAGE OF THE INVENTION According to this invention, the solar cell which can improve a solar cell characteristic, and its manufacturing method can be provided.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic and ratios of dimensions and the like are different from actual ones. Accordingly, specific dimensions and the like should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

(Configuration of solar cell)
The configuration of the solar cell according to the embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view of the back surface side of the solar cell 10 according to the present embodiment. FIG. 2 is an enlarged cross-sectional view taken along line AA in FIG.

  As shown in FIGS. 1 and 2, the solar cell 10 includes a semiconductor substrate 11, an in-junction 20, an ip junction 30, an n-side electrode 40n, and a p-side electrode 40p.

  The semiconductor substrate 11 has a light receiving surface that receives sunlight and a back surface provided on the opposite side of the light receiving surface. The semiconductor substrate 11 generates photogenerated carriers by receiving light on the light receiving surface. The photogenerated carrier refers to holes and electrons generated when light is absorbed by the semiconductor substrate 11.

  The semiconductor substrate 11 may be composed of a general semiconductor material including a crystalline semiconductor material such as single crystal Si or polycrystalline Si having n-type or p-type conductivity, or a compound semiconductor material such as GaAs or InP. it can. In the present embodiment, it is assumed that the semiconductor substrate 11 is an n-type single crystal silicon substrate. Note that minute irregularities may be formed on the light receiving surface of the semiconductor substrate 11.

  The in-junction 20 is formed in a line shape along the first direction on the back surface of the semiconductor substrate 11. The in-junction 20 according to the present embodiment includes a substantially intrinsic i-type amorphous silicon layer 20i and an n-type amorphous silicon layer 20n having an n-type conductivity type. The i-type amorphous silicon layer 20 i and the n-type amorphous silicon layer 20 n are sequentially formed on the back surface of the semiconductor substrate 11. According to such a configuration (so-called BSF structure), recombination of photogenerated carriers on the back surface of the semiconductor substrate 11 can be suppressed.

  Here, in the second direction substantially orthogonal to the first direction, the width of the n-type amorphous silicon layer 20n is smaller than the width of the i-type amorphous silicon layer 20i. Further, both side surfaces in the second direction of the n-type amorphous silicon layer 20n are formed flush with both side surfaces in the second direction of the i-type amorphous silicon layer 20i. As a result, slopes 20f are formed at both ends of the in-join 20 in the second direction.

  The ip junction 30 is formed in a line shape along the first direction on the back surface of the semiconductor substrate 11. The ip junction 30 according to the present embodiment includes an intrinsic i-type amorphous silicon layer 30i and a p-type amorphous silicon layer 30p having a p-type conductivity type. The i-type amorphous silicon layer 30 i and the p-type amorphous silicon layer 30 p are sequentially formed on the back surface of the semiconductor substrate 11. According to such a configuration (so-called HIT structure), the pn junction characteristics can be improved. In the second direction, the width of the p-type amorphous silicon layer 30p is smaller than the width of the i-type amorphous silicon layer 30i.

  The in-junction 20 and the ip junction 30 are formed so as to be adjacent to each other in the second direction, as shown in FIGS.

  The n-side electrode 40n is formed in a line along the first direction on the in-junction 20. The n-side electrode 40n is a collecting electrode that collects electrons from the in-junction 20. The n-side electrode 40n includes a transparent electrode layer and a conductive layer that are sequentially formed on the in-junction 20 (not shown). As the transparent electrode layer, a light-transmitting conductive material such as ITO (indium tin oxide), tin oxide, or zinc oxide can be used. As the conductive layer, a metal such as Ag or Al, a resin-type conductive paste using a resin material as a binder and conductive particles such as silver particles as a filler can be used.

  The p-side electrode 40p is formed in a line shape along the first direction on the ip junction 30. The p-side electrode 40 p is a collecting electrode that collects holes from the ip junction 30. Similarly to the n-side electrode 40n, the p-side electrode 40p is configured by a transparent electrode layer and a conductive layer that are sequentially formed on the ip junction 30 (not shown).

  Here, in the present embodiment, one end of the ip junction 30 covers one end of the in-junction 20 in the second direction. Specifically, the i-type amorphous silicon layer 30 i of the ip junction 30 covers the slope 20 f of the in-junction 20. The n-type amorphous silicon layer 20n and the p-type amorphous silicon layer 30p are electrically separated by the i-type amorphous silicon layer 30i.

(Method for manufacturing solar cell)
Next, the manufacturing method of the solar cell 10 is demonstrated, referring drawings.

  First, as shown in FIG. 3, an i-type amorphous silicon layer 20i and an n-type amorphous silicon layer 20n are sequentially formed on the back surface of an n-type single crystal silicon substrate (semiconductor substrate 11) using a CVD method. Thereby, the in-junction 20 is formed. The i-type amorphous silicon layer 20i has a thickness that does not substantially contribute to power generation, for example, about several to 250 inches. The layer thickness of the n-type amorphous silicon layer 20n is, for example, about 10 nm.

  Next, as shown in FIG. 4, a coating layer 50 is formed on the n-type amorphous silicon layer 20n by CVD. The covering layer 50 is formed using a material that can be selectively removed by an etching method in a later step. As the coating layer 50, for example, silicon nitride, silicon oxide, or the like can be used. The thickness of the coating layer 50 is, for example, about 100 nm.

  Next, as shown in FIG. 5, a part of the coating layer 50 is removed along the first direction at a predetermined interval by photolithography. Thereby, a plurality of first grooves 50g extending along the first direction are formed.

  Next, as shown in FIG. 6, a part of the i-type amorphous silicon layer 20i and the n-type amorphous silicon layer 20n is removed at a predetermined interval along the first direction by an etching method using the covering layer 50 as a mask. . Thereby, a plurality of second grooves 20g extending along the first direction are formed. The second groove 20g extends from the first groove 50g to the semiconductor substrate 11 side. In the present embodiment, the second groove 20 g is formed so as to reach the semiconductor substrate 11.

  Here, in the step of forming the second groove 20g, the portion of the n-type amorphous silicon layer 20n provided between the one end portion of the coating layer 50 in the second direction and the semiconductor substrate 11 is also removed. That is, the n-type amorphous silicon layer 20n provided under the covering layer 50 is removed so as to cover it. In this case, the i-type amorphous silicon layer 20 i provided under the coating layer 50 may be removed so as to be covered similarly. The slope 20 f is formed in the in-joint 20 by isotropically proceeding etching under the covering layer 50.

  Next, as shown in FIG. 7, an i-type amorphous silicon layer 30i and a p-type amorphous silicon layer 30p are sequentially formed on the bottom and side surfaces of the second groove 20g by using the CVD method. As a result, the ip junction 30 is formed. The i-type amorphous silicon layer 30i has a thickness that does not substantially contribute to power generation, for example, about several to 250 inches. The layer thickness of the p-type amorphous silicon layer 30p is, for example, about 10 nm. By forming the i-type amorphous silicon layer 30 i and the p-type amorphous silicon layer 30 p so as to go around the lower part of the covering layer 50, the inclined surface 20 f of the in-junction 20 is covered with the i-type amorphous silicon layer 30 i of the ip junction 30. . The n-type amorphous silicon layer 20n and the p-type amorphous silicon layer 30p are electrically separated by the i-type amorphous silicon layer 30i.

  Next, as shown in FIG. 8, the entire coating layer 50 is removed by an etching method. As a result, the ip junction 30 and the n-type amorphous silicon layer 20n are exposed. At this time, the end portion of the p-type amorphous silicon layer 30p is covered with the i-type amorphous silicon layer 30i, and the central portion of the p-type amorphous silicon layer 30p is exposed. In this step, the i-type amorphous silicon layer 30 i and the p-type amorphous silicon layer 30 p formed on the surface of the coating layer 50 are removed together with the coating layer 50.

  Next, an ITO layer (transparent electrode layer) is formed along the first direction on the n-type amorphous silicon layer 20n and the p-type amorphous silicon layer 30p by sputtering. Subsequently, a silver paste (conductive layer) is provided on the transparent electrode layer using a printing method, a coating method, or the like.

(Function and effect)
The solar cell 10 according to the present embodiment includes an in junction 20 and an ip junction 30 formed on the back surface. The i-type amorphous silicon layer 30i of the ip junction 30 covers one end of the n-type amorphous silicon layer 20n in the second direction.

  As a result, the p-type amorphous silicon layer 30 p of the ip junction 30 is electrically separated from the n-type amorphous silicon layer 20 n of the in-junction 20. Therefore, it is possible to suppress the formation of a low-quality diode between the p-type amorphous silicon layer 30p and the n-type amorphous silicon layer 20n. Further, since there is no need to provide a gap between the in-junction 20 and the ip junction 30, the interval between the in-junction 20 and the ip junction 30 can be reduced. Therefore, recombination of photogenerated carriers inside the semiconductor substrate 11 can be suppressed. As a result, the solar cell characteristics can be improved.

  In the method for manufacturing the solar cell 10 according to the present embodiment, the ip junction 30 can be formed using the second groove formed by removing a part of the coating layer 50. Therefore, the in-junction 20 and the ip junction 30 which are adjacent and electrically separated can be easily formed.

  Further, the end portion of the p-type amorphous silicon layer 30p is covered with the i-type amorphous silicon layer 30i, and the central portion of the p-type amorphous silicon layer 30p is exposed. For this reason, even if the position of the n-side electrode 40n formed on the n-type amorphous silicon layer 20n is slightly shifted, the short circuit between the p-type amorphous silicon layer 30p and the n-side electrode 40n causes the i-type amorphous silicon layer 30i. Is suppressed by. Therefore, the manufacturing yield of the solar cell 10 can be improved.

(Other embodiments)
Although the present invention has been described according to the above-described embodiments, it should not be understood that the descriptions and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  For example, in the above embodiment, the second groove 20g reaches the semiconductor substrate 11. However, the second groove 20g only needs to reach the i-type amorphous silicon layer 20i. However, when the i-type amorphous silicon layer 20 i is left between the second groove 20 g and the semiconductor substrate 11, it is preferable to reduce the thickness of the i-type amorphous silicon layer 30 i of the ip junction 30. Thereby, the electrical resistance value between the semiconductor substrate 11 and the ip junction 30 can be kept small. Note that the second groove 20 g may penetrate into the semiconductor substrate 11.

  In the above embodiment, the semiconductor substrate 11 is an n-type single crystal silicon substrate. However, the semiconductor substrate 11 may be a p-type single crystal silicon substrate.

  In the above embodiment, the ip junction 30 covers one end of the in-junction 20 in the second direction. However, the in-junction 20 may cover one end of the ip junction 30 in the second direction. .

  In the above embodiment, the in-junction 20 and the ip junction 30 are made of amorphous silicon. However, the present invention is not limited to this. For example, the in-junction 20 and the ip junction 30 may be made of amorphous silicon carbide or microcrystalline silicon.

  In the above embodiment, the i-type amorphous silicon layer 20i and the i-type amorphous silicon layer 30i are substantially intrinsic. However, both the p-type dopant and the n-type dopant are compensated for each other. May be included.

  As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

  Hereinafter, examples of the solar cell according to the present invention will be specifically described. However, the present invention is not limited to those shown in the following examples, and may be appropriately changed within the scope not changing the gist thereof. Can be implemented.

(Example)
First, an (100) -oriented n-type single crystal silicon substrate (100 mm square, 200 μm thickness, resistivity 0.1 Ωcm) was prepared.

  Next, a fine texture structure was formed on the light-receiving surface of the n-type single crystal silicon substrate by anisotropic etching using an aqueous alkali solution (20% sodium hydroxide).

  Next, a non-doped i-type amorphous silicon layer and an n-type amorphous silicon layer doped with n-type impurities were sequentially formed on the back surface of the n-type single crystal silicon substrate by Rf plasma CVD. The layer thickness of the i-type amorphous silicon layer was 5 nm, and the layer thickness of the n-type amorphous silicon layer was 5 nm.

  Next, a 100 nm thick silicon nitride layer was formed as a sacrificial layer on the n-type amorphous silicon layer by Rf plasma CVD.

  Next, a 5 μm-thick photoresist layer was formed on the silicon nitride layer by spin coating, and an opening pattern along the first direction was formed by exposure. Subsequently, a part of the silicon nitride layer was removed according to the opening pattern using a hydrofluoric acid aqueous solution (5% hydrofluoric acid). Thereby, a plurality of first grooves were formed. Note that the opening width of the first groove was adjusted so that the pitch between the in-junction and the ip-junction formed in the subsequent process was 1000 μm.

  Next, an 80 nm thick silicon nitride layer was formed as a passivation layer on the light-receiving surface of the n-type single crystal silicon substrate by Rf plasma CVD.

  Next, the n-type amorphous silicon layer exposed inside the first groove was removed by an isotropic etching method using an alkaline aqueous solution (3% sodium hydroxide). In the step, the i-type amorphous silicon layer and the n-type single crystal silicon substrate were removed at the same time, thereby forming a second groove reaching the inside of the n-type single crystal silicon substrate from the first groove. At this time, the n-type amorphous silicon layer and the i-type amorphous silicon layer provided under the covering layer 50 were removed so that the slope was formed at the end of the in-junction. The vertical length of the second groove was about 2 μm.

  Next, a non-doped i-type amorphous silicon layer and a p-type amorphous silicon layer doped with p-type impurities were sequentially formed on the bottom and side surfaces of the second groove by Rf plasma CVD. The layer thickness of the i-type amorphous silicon layer was 5 nm, and the layer thickness of the p-type amorphous silicon layer was 5 nm. As a result, ip junctions were formed inside the second groove, and 96 in junctions and ip junctions were formed at a pitch of 1000 μm.

  Next, a resist layer was formed as a light-receiving surface protective layer by spin coating on a silicon nitride layer as a passivation layer formed on the light-receiving surface of the n-type single crystal silicon substrate, and was cured by exposure.

  Next, the silicon nitride layer as a sacrificial layer was removed using a hydrofluoric acid aqueous solution (5% hydrofluoric acid).

  Next, an ITO layer having a thickness of 50 nm and an Ag layer having a thickness of 5 μm were formed on the in-junction and the ip-junction by Rf sputtering using a metal mask.

(Comparative example)
Next, a solar cell according to a comparative example was produced as follows.

  First, a non-doped i-type amorphous silicon layer and an n-type amorphous silicon layer doped with an n-type impurity are formed on the back surface of an n-type single crystal silicon substrate similar to the embodiment by Rf plasma CVD using a metal mask. Sequentially formed in a comb shape. The layer thickness of the i-type amorphous silicon layer was 5 nm, and the layer thickness of the n-type amorphous silicon layer was 5 nm.

  Next, a non-doped i-type amorphous silicon layer and a p-type amorphous silicon layer doped with a p-type impurity are comb-shaped on the back surface of the n-type single crystal silicon substrate by Rf plasma CVD using a metal mask. Sequentially formed. The layer thickness of the i-type amorphous silicon layer was 5 nm, and the layer thickness of the p-type amorphous silicon layer was 5 nm. As a result, a plurality of in-junctions and a plurality of ip junctions were alternately formed.

  Next, an 80 nm thick silicon nitride layer was formed as a surface antireflection layer on the light-receiving surface of the n-type single crystal silicon substrate by Rf plasma CVD.

(Measurement of solar cell characteristics)
Next, the conversion efficiency of the solar cell was measured as the solar cell characteristic. Specifically, the solar cell conversion efficiency was measured for each of the ten examples and comparative examples described above using a solar simulator. Table 1 shows the measurement results.

  As shown in the above table, the conversion efficiency of the solar cell according to the example was higher than the conversion efficiency of the solar cell according to the comparative example.

  In the solar cell according to the example, the distance between the in-junction and the ip junction can be narrowed, and both can be electrically separated by the i-type amorphous silicon layer constituting the ip junction. Therefore, conversion efficiency could be improved in the solar cell according to the example.

  On the other hand, in the solar cell according to the comparative example, it is considered that the conversion efficiency was lowered because a low-quality diode was formed in the portion where the in-junction and the ip-junction contacted.

It is a top view of the back surface side of the solar cell 10 which concerns on embodiment of this invention. It is an expanded sectional view in the AA line of FIG. It is a figure for demonstrating the manufacturing method of the solar cell 10 which concerns on embodiment of this invention (the 1). It is a figure for demonstrating the manufacturing method of the solar cell 10 which concerns on embodiment of this invention (the 2). It is a figure for demonstrating the manufacturing method of the solar cell 10 which concerns on embodiment of this invention (the 3). It is a figure for demonstrating the manufacturing method of the solar cell 10 which concerns on embodiment of this invention (the 4). It is a figure for demonstrating the manufacturing method of the solar cell 10 which concerns on embodiment of this invention (the 5). It is a figure for demonstrating the manufacturing method of the solar cell 10 which concerns on embodiment of this invention (the 6).

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Solar cell 11 ... Semiconductor substrate 20 ... In junction 20f ... Slope 20i ... i-type amorphous silicon layer 20n ... n-type amorphous silicon layer 30 ... ip junction 30i ... i-type amorphous silicon layer 30p ... p-type amorphous silicon layer 40n ... n Side electrode 40p ... p side electrode 50 ... covering layer 50g ... first groove 20g ... second groove

Claims (4)

  1. A semiconductor substrate having a light receiving surface and a back surface provided on the opposite side of the light receiving surface;
    A first semiconductor junction composed of an intrinsic first i-type semiconductor layer sequentially formed on the back surface and a one-conductivity-type semiconductor layer having one conductivity type;
    A second semiconductor junction composed of a substantially intrinsic second i-type semiconductor layer sequentially formed on the back surface and another conductivity type semiconductor layer having another conductivity type;
    Each of the first semiconductor junction and the second semiconductor junction is formed along a first direction that is horizontal to the semiconductor substrate,
    The second i-type semiconductor layer includes the first i-type semiconductor layer and the one-conductivity type semiconductor layer so that the other-conductivity-type semiconductor layer and the one-conductivity-type semiconductor layer are electrically separated from each other. A solar cell characterized by covering a side surface of one end portion in a second direction which is substantially perpendicular to the first direction and horizontal to the semiconductor substrate.
  2. The side surface of the one end portion in the second direction of the first semiconductor junction has a slope inclined toward the semiconductor substrate,
    The solar cell according to claim 1, wherein the second i-type semiconductor layer covers the slope.
  3. A method for manufacturing a solar cell comprising a semiconductor substrate having a light receiving surface and a back surface provided on the opposite side of the light receiving surface,
    Sequentially forming an intrinsic first i-type semiconductor layer and one conductivity type semiconductor layer having one conductivity type on the back surface;
    Forming a coating layer on the one conductivity type semiconductor layer;
    Forming a first groove by removing a part of the covering layer along a first direction that is horizontal with the semiconductor substrate;
    Forming a second groove extending from the first groove toward the semiconductor substrate by removing the one-conductivity-type semiconductor layer exposed in the first groove;
    A substantially intrinsic second i-type semiconductor layer and another conductivity type semiconductor layer having another conductivity type are formed on the bottom surface and side surface of the second groove, and the other conductivity type semiconductor layer and the one conductivity type semiconductor layer. Sequentially forming the layers so as to be electrically isolated from each other;
    Removing the coating layer,
    In the step of forming the second i-type semiconductor layer,
    One end of the first i-type semiconductor layer and the one-conductivity-type semiconductor layer in the second direction that is substantially orthogonal to the first direction and is horizontal to the semiconductor substrate by the second i-type semiconductor layer. A method for manufacturing a solar cell, characterized by covering a side surface of the solar cell.
  4. In the step of forming the second groove,
    4. The method for manufacturing a solar cell according to claim 3, wherein a portion provided between the one end portion of the covering layer in the second direction and the semiconductor substrate is removed from the one-conductivity-type semiconductor layer. .
JP2008250723A 2008-09-29 2008-09-29 Solar cell and manufacturing method thereof Active JP5347409B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008250723A JP5347409B2 (en) 2008-09-29 2008-09-29 Solar cell and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008250723A JP5347409B2 (en) 2008-09-29 2008-09-29 Solar cell and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2010080887A JP2010080887A (en) 2010-04-08
JP5347409B2 true JP5347409B2 (en) 2013-11-20

Family

ID=42210944

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008250723A Active JP5347409B2 (en) 2008-09-29 2008-09-29 Solar cell and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP5347409B2 (en)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5485060B2 (en) 2010-07-28 2014-05-07 三洋電機株式会社 Manufacturing method of solar cell
JP5595850B2 (en) 2010-09-27 2014-09-24 三洋電機株式会社 Manufacturing method of solar cell
JP2012138545A (en) * 2010-12-28 2012-07-19 Sanyo Electric Co Ltd Solar cell and solar cell module
JP5879515B2 (en) 2010-12-29 2016-03-08 パナソニックIpマネジメント株式会社 Manufacturing method of solar cell
JP5820987B2 (en) * 2011-03-25 2015-11-24 パナソニックIpマネジメント株式会社 Solar cell
GB2491209B (en) * 2011-05-27 2013-08-21 Renewable Energy Corp Asa Solar cell and method for producing same
JP2013030615A (en) 2011-07-28 2013-02-07 Sanyo Electric Co Ltd Solar cell
JP5948685B2 (en) 2011-12-27 2016-07-06 パナソニックIpマネジメント株式会社 Solar cell and manufacturing method thereof
JP6156748B2 (en) * 2012-03-08 2017-07-05 パナソニックIpマネジメント株式会社 Manufacturing method of semiconductor device
JP6032911B2 (en) * 2012-03-23 2016-11-30 シャープ株式会社 Photoelectric conversion element and manufacturing method thereof
JP2015133341A (en) * 2012-04-27 2015-07-23 パナソニック株式会社 Back-junction solar cell and method of manufacturing the same
GB2503515A (en) * 2012-06-29 2014-01-01 Rec Cells Pte Ltd A rear contact heterojunction solar cell
JP2014072209A (en) * 2012-09-27 2014-04-21 Sharp Corp Photoelectric conversion element and photoelectric conversion element manufacturing method
WO2014163043A1 (en) * 2013-04-02 2014-10-09 シャープ株式会社 Photoelectric conversion element
JP2015185743A (en) 2014-03-25 2015-10-22 シャープ株式会社 photoelectric conversion element
WO2016114271A1 (en) * 2015-01-14 2016-07-21 シャープ株式会社 Photoelectric conversion element, solar cell module provided with same, and photovoltaic power generation system
JP6564199B2 (en) * 2015-02-18 2019-08-21 シャープ株式会社 Back electrode type photoelectric conversion element and method for manufacturing back electrode type photoelectric conversion element
WO2017033232A1 (en) 2015-08-21 2017-03-02 シャープ株式会社 Photoelectric conversion element
WO2019181834A1 (en) * 2018-03-23 2019-09-26 株式会社カネカ Method for producing solar cell, and solar cell

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4155899B2 (en) * 2003-09-24 2008-09-24 三洋電機株式会社 Photovoltaic element manufacturing method
FR2880989B1 (en) * 2005-01-20 2007-03-09 Commissariat Energie Atomique SEMICONDUCTOR DEVICE WITH HETEROJUNCTIONS AND INTERDIGITAL STRUCTURE
JP2009152222A (en) * 2006-10-27 2009-07-09 Kyocera Corp Manufacturing method of solar cell element

Also Published As

Publication number Publication date
JP2010080887A (en) 2010-04-08

Similar Documents

Publication Publication Date Title
US9972738B2 (en) Solar cell and method for manufacturing the same
AU2016231480B2 (en) Photovoltaic devices with electroplated metal grids
US9356165B2 (en) Semiconductor device and method for manufacturing the same
US9711667B2 (en) Solar cell and method of manufacturing the same
USRE47484E1 (en) Solar cell
US20170170340A1 (en) Solar cell
US10181540B2 (en) Solar cell and method of manufacturing the same
US9508875B2 (en) Solar cell and method for manufacturing the same
US20140349441A1 (en) Solar cell with metal grid fabricated by electroplating
JP5879538B2 (en) Photoelectric conversion device and manufacturing method thereof
EP2428997B1 (en) Solar cell with electroplated metal grid
JP5906393B2 (en) Solar cell and method for manufacturing solar cell
EP2822041A1 (en) Solar cell and method for manufacturing the same
KR101275575B1 (en) Back contact solar cell and manufacturing method thereof
EP2371010B1 (en) Solar cell and method of manufacturing the same
US7863515B2 (en) Thin-film solar cell and method of manufacturing the same
US7858426B2 (en) Method of texturing solar cell and method of manufacturing solar cell
CA2744706C (en) Solar cell with a backside via to contact the emitter layer
KR101212198B1 (en) Solar cell
KR101258968B1 (en) Solar cell and solar cell manufacturing method
EP2371009B1 (en) Solar cell and method of manufacturing the same
US20140102524A1 (en) Novel electron collectors for silicon photovoltaic cells
EP3170209B1 (en) Solar cell with interdigitated back contact
EP2219222B1 (en) Solar cell and method for manufacturing the same
US9853178B2 (en) Selective emitter solar cell

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20110913

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120725

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120821

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20121012

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130226

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130306

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20130507

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130619

RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7421

Effective date: 20130702

A911 Transfer of reconsideration by examiner before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20130708

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130723

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130805