KR101828423B1 - Solar cell - Google Patents

Abstract

The present invention relates to a solar cell.
A solar cell according to the present invention includes: a semiconductor substrate containing an impurity of a first conductivity type; An emitter portion disposed on a rear surface of the semiconductor substrate and forming a pn junction with the semiconductor substrate and having a second conductivity type opposite to the first conductivity type; A rear electric field element disposed on a rear surface of the semiconductor substrate and containing impurities of the first conductive type at a high concentration than the semiconductor substrate; A first electrode formed on the emitter portion; A second electrode formed on the rear electric field portion; And a buffer layer disposed between the first electrode and the second electrode in the rear surface of the substrate, wherein the buffer layer is formed on at least one of the rear surface of the semiconductor substrate except for the region overlapping the buffer layer and in contact with the emitter portion or the rear electric portion The surface area per unit area of the rear surface of the semiconductor substrate is larger than the surface area per unit surface of the back surface of the semiconductor substrate in the area overlapping the buffer layer in the rear surface of the semiconductor substrate.

Description

Solar cell {SOLAR CELL}

The present invention relates to a solar cell.

Recently, as energy resources such as oil and coal are expected to be depleted, interest in alternative energy to replace them is increasing, and solar cells that produce electric energy from solar energy are attracting attention.

Typical solar cells have a semiconductor portion that forms a p-n junction by different conductive types, such as p-type and n-type, and electrodes connected to semiconductor portions of different conductivity types, respectively.

When light is incident on such a solar cell, a plurality of electron-hole pairs are generated in the semiconductor, and the generated electron-hole pairs are separated into electrons and holes, respectively, so that electrons move toward the n- And moves toward the semiconductor portion. The transferred electrons and holes are collected by the different electrodes connected to the p-type semiconductor portion and the n-type semiconductor portion, respectively, and the electrodes are connected by a wire to obtain electric power.

An object of the present invention is to improve the efficiency of a solar cell.

A solar cell according to the present invention includes: a semiconductor substrate containing an impurity of a first conductivity type; An emitter portion disposed on a rear surface of the semiconductor substrate, the emitter portion forming a p-n junction with the semiconductor substrate and having a second conductivity type opposite to the first conductivity type; A rear electric field element disposed on a rear surface of the semiconductor substrate and containing impurities of the first conductive type at a high concentration than the semiconductor substrate; A first electrode formed on the emitter portion; A second electrode formed on the rear electric field portion; And a buffer layer disposed between the first electrode and the second electrode in the rear surface of the substrate, wherein the buffer layer is formed on at least one of the rear surface of the semiconductor substrate except for the region overlapping the buffer layer, The surface area per unit area of the rear surface of the semiconductor substrate is larger than the surface area per unit surface of the back surface of the semiconductor substrate in the area overlapping the buffer layer in the rear surface of the semiconductor substrate.

Here, irregularities having a first shape are formed in a region overlapping with the buffer layer in the rear surface of the semiconductor substrate, and regions other than the region overlapping the buffer layer in contact with the emitter portion or the rear surface electric portion are formed Irregularities having a second shape can be formed.

Here, the irregularities having the first shape include a flat surface at the top, and the irregularities having the second shape may not include a flat surface at the top.

Specifically, the side cross-sectional shape of the unevenness having the first shape includes a trapezoidal shape, and the side cross-sectional shape of the unevenness having the second shape may include the pyramidal shape. At this time, the width of the flat surface formed at the top of the unevenness having the first shape may be between 1 and 20 mu m.

Among the irregularities having the trapezoidal shape, the maximum height may be smaller than the height of the irregularities having the maximum height among the irregularities having the pyramidal shape. Specifically, the maximum height among the irregularities having the trapezoidal shape is 5 탆, The maximum height may be 15 占 퐉.

Further, the bottom surface shape of the concavo-convex shape having the trapezoidal shape may be the same as the bottom shape shape of the concavo-convex shape having the pyramidal shape.

The region where the irregularities having the second shape are formed can be overlapped with the junction surface between the first electrode and the emitter portion in the rear surface of the semiconductor substrate, Electrode and the rear surface electric field portion.

In addition, the emitter portion and the rear surface electric portion may be in contact with each other, and the buffer layer may be disposed on the junction surface between the emitter portion and the rear surface electric portion that are in contact with each other, and the buffer layer may include a nonconductive insulating material.

In one example, the buffer layer may comprise at least one of silicon oxide (SiOx) and silicon nitride (SiNx).

In addition, the emitter portion and the rear surface electric portion may include crystalline silicon or amorphous silicon, and the semiconductor substrate may include crystalline silicon.

The side cross-sectional shape of the concavities and convexities having the first shape may include a pyramidal shape and the side cross-sectional shape of the concavities and convexes having the second shape may include a pyramidal shape having a plurality of concavities and convexities .

Alternatively, the side cross-sectional shape of the concavities and convexities having the first shape includes a trapezoidal shape, and the side cross-sectional shape of the concavities and convexes having the second shape includes a concavity having a trapezoidal shape and a plurality of concavo- can do.

The surface area per unit area of the back surface of the semiconductor substrate in at least one region of the back surface of the semiconductor substrate excluding the region overlapping with the buffer layer in the emitter region or the region in contact with the back surface electric field is less than the surface area of the back surface of the semiconductor substrate, The surface area per unit area of the rear surface of the semiconductor substrate in the overlapped region is made larger, and the short-circuit current of the solar cell can be further improved.

1 to 3 are views for explaining a first embodiment of a solar cell according to the present invention.
4 is a view for explaining a second embodiment of a solar cell according to the present invention.
5 is a view for explaining a third embodiment of the solar cell according to the present invention.
6 is a view for explaining a fourth embodiment of the solar cell according to the present invention.
Figs. 7 and 8 are views for explaining another example of the shape of the unevenness shown in Figs. 1 to 3; Fig.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. Like parts are designated with like reference numerals throughout the specification. When a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the case directly above another portion but also the case where there is another portion in between. Conversely, when a part is "directly over" another part, it means that there is no other part in the middle. Also, when a part is formed as "whole" on the other part, it means not only that it is formed on the entire surface (or the front surface) of the other part but also not on the edge part.

Hereinafter, a solar cell according to the present invention will be described with reference to the accompanying drawings.

1 to 3 are views for explaining a first embodiment of a solar cell according to the present invention.

1 is a cross-sectional view taken along line II-II of FIG. 1, and FIG. 3 is a cross-sectional view of a solar cell according to a first embodiment of the present invention, And the shapes of the irregularities having the second shape are compared with each other.

1 and 2, a solar cell 1 according to an embodiment of the present invention includes a semiconductor substrate 110, a front surface of a semiconductor substrate 110, an antireflective portion 130 located on the front electric field portion 171 and a second side opposite to the first side of the semiconductor substrate 110, A plurality of emitter portions 121 are formed on a plurality of emitter portions 121 and a plurality of back surface fields (BSFs) 172 disposed on the back surface of the substrate and extending in parallel with the plurality of emitter portions 121, A plurality of second electrodes 142 positioned on the plurality of rear electric units 172 and a plurality of second electrodes 142 positioned between the first electrodes 141 and the second electrodes 142 on the rear surface of the substrate, And a buffer layer 150 disposed on the buffer layer 150.

1 and 2 show an example in which the solar cell 1 according to the present invention includes the antireflective portion 130 and the front electric field portion 171. Herein, the antireflective portion 130 And the front electric field portion 171 may be omitted.

However, since the photovoltaic efficiency of the solar cell 1 can be further improved when the antireflective portion 130 and the front electric field portion 171 are formed, the antireflective portion 130 and the front electric field portion 171 The solar cell 1 included in the solar cell will be described as an example.

The semiconductor substrate 110 may be a crystalline semiconductor substrate 110 made of silicon of a first conductivity type, for example, n-type conductive type. At this time, the silicon may be crystalline silicon such as single crystal silicon or polycrystalline silicon. Impurities of pentavalent elements such as phosphorus (P), arsenic (As), and antimony (Sb) are doped in the semiconductor substrate 110 when the semiconductor substrate 110 has an n-type conductivity type. Alternatively, however, the semiconductor substrate 110 may be of the p-type conductivity type and may be made of a semiconductor material other than silicon. When the semiconductor substrate 110 has a p-type conductivity type, the semiconductor substrate 110 is doped with impurities of a trivalent element such as boron (B), gallium (Ga), indium (In) do.

The incident surface of the semiconductor substrate 110 is textured to have an irregular surface. Although only the edge portion of the semiconductor substrate 110 is shown as an uneven surface in FIG. 1, substantially the whole front surface of the semiconductor substrate 110 has an uneven surface, The portion 130 and the front electric field portion 171 also have an uneven surface.

1 and 2, the semiconductor substrate 110 may have irregularities on the front surface as well as on the front surface. However, irregularities having a second shape, which is a part of the rear surface of the semiconductor substrate 110, The shape of the irregularities formed in the region where the irregularities having the first shape are formed may be the same as the shape of the irregularities formed in the front surface of the semiconductor substrate 110, As shown in FIG.

Next, the front electric field portion 171 may be positioned on the front surface of the semiconductor substrate 110, as shown in FIG.

Such a front electric field portion 171 has a potential barrier due to a difference in impurity concentration between the semiconductor substrate 110 and the front electric field portion 171 and prevents a charge (e.g., hole) from moving toward the front surface of the semiconductor substrate 110 There is a field effect.

Therefore, the front electric field portion 171 has a front field effect that causes the holes moving toward the front side of the semiconductor substrate 110 to be returned to the rear side of the semiconductor substrate 110 by the potential barrier, Increases the amount of charge output from the external device and reduces the amount of charge lost due to recombination or defects on the front surface of the semiconductor substrate 110. [

Such a front electric field portion 171 may include hydrogen. When the front electric field portion 171 includes hydrogen, a defect such as a dangling bond mainly present on the surface of the semiconductor substrate 110 and its vicinity It is possible to perform a passivation function to reduce the loss of charges on the front surface of the semiconductor substrate 110 due to defects.

The front electric field portion 171 may include any one of amorphous silicon, amorphous silicon oxide (a-SiOx), and amorphous silicon silicon (a-SiC).

The reflection preventing portion 130 may be positioned on the front electric field portion 171 to reduce the reflectivity of the light incident on the solar cell 1 and increase the selectivity of a specific wavelength region, . The reflection preventing part 130 may include at least one of a silicon nitride film (SiNx), a zinc oxide film (ZnO), or an aluminum zinc oxide (AZO) film.

Although the anti-reflection portion 130 has a single-layer structure in FIGS. 1 and 2, the anti-reflection portion 130 may have a double-layer structure or a multi-layer structure.

The plurality of emitter sections 121 extend in parallel with a plurality of rear electric sections 172 in a predetermined direction on the rear surface of the semiconductor substrate 110.

As shown in FIGS. 1 and 2, the backside electrical portion 172 and the emitter portion 121 are alternately located above the semiconductor substrate 110.

Each emitter section 121 is formed on the rear surface of the semiconductor substrate 110 and has a second conductive type opposite to the conductive type of the semiconductor substrate 110, for example, a p-type conductive type, 121 form a pn junction with the semiconductor substrate 110.

Hole pairs formed by the light incident on the semiconductor substrate 110 are separated into electrons and holes by the pn junction formed between the semiconductor substrate 110 and the plurality of emitter sections 121, And the holes move toward the p-type. Therefore, when the semiconductor substrate 110 is n-type and the plurality of emitter portions 121 are p-type, the separated holes move toward the respective emitter portions 121 and the separated electrons are higher in impurity concentration than the semiconductor substrate 110 And moves toward the plurality of rear electric sections 172.

When the semiconductor substrate 110 has a p-type conductivity type, the emitter section 121 is formed to have an n-type conductivity, that is, Type. In this case, the separated electrons move toward the plurality of emitter sections 121, and the separated holes move toward the plurality of rear electric field sections 172.

When the plurality of emitter sections 121 have a p-type conductivity type, the emitter section 121 can be doped with an impurity of a trivalent element. Conversely, when the plurality of emitter sections 121 have an n-type conductivity type , The emitter portion 121 may be doped with an impurity of a pentavalent element.

The emitter 121 may be formed by diffusing an impurity of the second conductivity type on the rear surface of the semiconductor substrate 110 or may be formed on the rear surface of the semiconductor substrate 110 by using an amorphous silicon material containing an impurity of the second conductivity type May be formed by vapor deposition.

When the semiconductor substrate 110 includes crystalline silicon and the emitter section 121 includes amorphous silicon, the emitter section 121 forms a hetero junction as well as a p-n junction with the semiconductor substrate 110. As described above, when the semiconductor substrate 110 and the emitter section 121 form a heterojunction, the open-circuit voltage (Voc) of the solar cell 1 can be further improved.

The plurality of rear electric field sections 172 are regions containing impurities of the same conductivity type as that of the semiconductor substrate 110 at a higher concentration than the semiconductor substrate 110. For example, if the substrate comprises n-type impurities, the plurality of backside electrical sections 172 may be n + impurity regions.

The plurality of rear electric field sections 172 are disposed on the rear surface of the semiconductor substrate 110 and extend in a predetermined direction parallel to the emitter section 121. Here, the rear electric section 172 may be formed in contact with the emitter section 121, as shown in FIGS. 1 and 2, but may be formed to be spaced apart from each other. Hereinafter, as shown in FIGS. 1 to 3, a case where the rear electric section 172 and the emitter section 121 are formed in contact with each other will be described as an example.

In addition, the rear electric field section 172 may be formed by diffusing impurities of the first conductivity type on the rear surface of the semiconductor substrate 110, or may include an impurity of the first conductivity type on the rear surface of the semiconductor substrate 110 Or may be formed by depositing an amorphous silicon material.

The rear electric field 172 disturbs the hole movement toward the rear electric field 172, which is the movement direction of the electrons, due to the potential barrier due to the difference in impurity concentration between the semiconductor substrate 110 and the rear electric field 172, (E. G., Electrons) to the backside electrical < / RTI > Thus, the amount of charge lost by recombination of electrons and holes in the rear electric field 172 and in the vicinity thereof or at the first and second electrodes 141 and 142 is reduced and the electron movement is accelerated to the rear electric field 172 The electron transfer amount can be increased.

Each of the plurality of first electrodes 141 is located on the plurality of emitter sections 121 and extends along the plurality of emitter sections 121 and is electrically and physically connected to the plurality of emitter sections 121. Each first electrode 141 collects charges, for example, holes, which have migrated toward the corresponding emitter section 121.

A plurality of second electrodes 142 extend over the plurality of rear electrical components 172 and are electrically and physically connected to the plurality of rear electrical components 172 have. Each second electrode 142 collects a charge, e. G., Electrons, that travels toward the corresponding rear electric field 172.

 The plurality of first and second electrodes 141 and 142 may be formed of a conductive metal material. For example, a metal such as nickel (Ni), copper (Cu), silver (Ag), aluminum (Al), tin (Sn), zinc (Zn), indium (In), titanium (Ti) , Or alternatively may be formed of a transparent conductive metal, for example, a TCO.

The buffer layer 150 is disposed between the first electrode 141 and the second electrode 142 on the rear surface of the substrate and functions to isolate the first electrode 141 and the second electrode 142 from each other. Accordingly, the buffer layer 150 includes a nonconductive insulating material, and may include at least one of silicon oxide (SiOx) and silicon nitride (SiNx).

The buffer layer 150 may be disposed on the junction surface of the emitter section 121 and the rear electric section 172.

The operation of the solar cell 1 according to this embodiment having such a structure is as follows.

When light is irradiated to the solar cell 1 and is incident on the semiconductor substrate 110, electron-hole pairs are generated in the semiconductor substrate 110 due to light energy. These electron-hole pairs are separated from each other by the pn junction of the semiconductor substrate 110 and the emitter section 121, and the holes move toward the emitter section 121 having the p-type conductivity type, and electrons move to the n- To the first electrode 141 and the second electrode 142, and are collected by the first and second electrodes 141 and 142, respectively. When the first electrode 141 and the second electrode 142 are connected to each other by a conductor, a current flows and the external power is utilized.

In the solar cell 1 according to the present invention, a region of the back surface of the semiconductor substrate 110 excluding the region S1 overlapping with the buffer layer 150 is in contact with the emitter portion 121 or the rear surface electric portion 172 The surface area per unit area of the rear surface of the semiconductor substrate 110 in at least one region is larger than the surface area per unit area of the rear surface of the semiconductor substrate 110 in the region S1 overlapping the buffer layer 150, .

This is because unevenness having a first shape with a relatively small surface area is formed in the region S1 overlapping the buffer layer 150 from the rear surface of the semiconductor substrate 110 and the semiconductor substrate 110 except for the region S1 overlapping the buffer layer 150 The areas SE and SB in contact with the emitter section 121 or the rear electric section 172 in the rear surface of the substrate 110 are formed with irregularities having a relatively large surface area and a second shape different from the first shape .

2, in a solar cell 1 according to the present invention, a semiconductor substrate 110 having a first shape formed in a region S1 that overlaps with a buffer layer 150 from a rear surface of the semiconductor substrate 110, And irregularities having a second shape different from the first shape are formed in a region SE in contact with the emitter portion 121 from the rear surface of the semiconductor substrate 110 excluding the region S1 overlapping with the buffer layer 150 . That is, a region having a second shape in the rear surface of the semiconductor substrate 110 can be overlapped with a surface to which the first electrode 141 and the emitter portion 121 are bonded.

At this time, irregularities P1 having a first shape are formed in a region SB of the rear surface of the semiconductor substrate 110 except for the region S1 overlapping with the buffer layer 150, The concavities and convexities P2 having the second shape may be formed. This will be described in more detail in Fig. 5 and Fig.

3, the irregularities P1 having the first shape include the flat surface PT at the top, and the irregularities P2 having the second shape include the flat surface (PT) at the top portion, ). ≪ / RTI > For example, as shown in Fig. 3, the side cross-sectional shape of the unevenness P2 having the second shape includes a pyramidal shape, and the side cross-sectional shape of the unevenness P1 having the first shape may include a trapezoidal shape have.

Here, the irregularities P1 having the first shape may be formed by another etching process, which is performed by performing a saw damage etching on the back surface of the semiconductor substrate 110, or may be formed by another etching process, After the small damage etching is performed on the rear surface of the semiconductor substrate 110, the protrusions P2 are formed on the back surface of the semiconductor substrate 110 excluding the region S1 to be overlapped with the buffer layer 150, Only the regions SE and SB to be in contact with the step portion 172 may be formed by further performing dry etching or wet etching.

More specifically, during the cutting process for forming the semiconductor substrate 110 for the solar cell 1, defects may occur on the surface of the semiconductor substrate 110. Such defects may be caused by saw damage etching, As shown in FIG.

The saw damage etching can be performed by wet etching. In the case of performing the saw damage etching, the top surface of the semiconductor substrate 110 has a first shape having a flat top portion, that is, Irregularities P1 having a trapezoidal shape can be formed.

Thereafter, wet etching is additionally performed to only the regions SE and SB to be in contact with the emitter portion 121 or the rear electric portion 172 in the rear surface of the semiconductor substrate 110 excluding the region S1 to be overlapped with the buffer layer 150 To form the second shape, that is, the unevenness P2 having the pyramidal shape as described above.

When forming the irregularities P2 having such a pyramidal shape, KOH or NaOH may be used as an etching solution which can be used in the case of wet etching.

As described above, irregularities P1 having a trapezoidal shape are formed in the region S1 overlapping the buffer layer 150 from the rear surface of the semiconductor substrate 110 and the semiconductor substrate 110 except for the region S1 overlapping the buffer layer 150 The projections P2 having a pyramidal shape are formed in the regions SE and SB in contact with the emitter portion 121 or the rear electric portion 172 in the rear surface of the substrate 110 to increase the efficiency of the solar cell 1 .

A concavo-convex structure P2 having a pyramid shape formed on the rear surface of the semiconductor substrate 110 may be formed on the junction surface of the semiconductor substrate 110 and the emitter section 121 or on the surface of the semiconductor substrate 110 and the rear surface The junction areas SE and SB between the emitter part 121 and the first electrode 141 and between the back surface electric part 172 and the second electrode 142 ) Can be made larger than that of the front merged surfaces. Accordingly, carriers can be collected more efficiently through the emitter section 121 and the rear electric section 172, and the short-circuit current of the solar cell 1 can be further improved.

In addition, since the pyramid-shaped projections and depressions P2 do not include the flat surface PT at the top of the projections and depressions, unlike the projections P1 having the trapezoidal shape, It is possible to disperse light of a long wavelength band not absorbed in the semiconductor substrate 110 through a pyramid-shaped concavo-convex slope, to reflect more efficiently, and to generate more carriers in the semiconductor substrate 110 . Thus, the short-circuit current of the solar cell 1 can be further improved.

Hereinafter, the irregularities P1 having the first shape and the irregularities P2 having the second shape in the rear surface of the semiconductor substrate 110 will be described in more detail with reference to FIG.

3 (a) is an enlarged view of a section K1 of a region S1 overlapping the buffer layer 150 from the rear surface of the semiconductor substrate 110. FIG. 3 (b) Sectional view showing a section K2 of an area SE in contact with the emitter section 121 in the rear surface of the semiconductor substrate 110 excluding the overlapped area S1.

3A, the side cross-sectional shape of the irregularities P1 having the first shape formed in the region S1 overlapping the buffer layer 150 from the rear surface of the semiconductor substrate 110 has a trapezoidal shape (B) of FIG. 3, in the back surface of the semiconductor substrate 110 excluding the region S1 overlapping the buffer layer 150 in the solar cell 1 according to the present invention, the emitter portions 121 The side cross-sectional shape of the concavities and convexities P2 having the second shape formed in the region SE in contact with the concave and convex portions may include a pyramidal shape.

Although not shown in FIG. 3, unevenness P2 having a second shape, that is, unevenness P2 having a pyramidal shape is formed on the front surface of the semiconductor substrate 110, as shown in FIGS. 1 and 2 .

Here, the width (WPT) of the flat surface (PT) formed at the top of the concavo-convex (P1) having the first shape may be between 1 and 20 mu m. The width (WPT) of such a flat surface (PT) may vary with the time of the small damage etching. That is, when the small damage etching time is short, the width WPT of the flat surface PT of the trapezoidal shape formed in the region S1 overlapping the buffer layer 150 is relatively wide, and the small damage etching time The width WPT of the flat surface PT is formed to be relatively narrow.

3, the height h1 of the irregularities having the maximum height among the irregularities P1 having the trapezoidal shape is the height (h2) of the irregularities having the maximum height among the irregularities P2 having the pyramidal shape ).

For example, the height h1 of the irregularities having the maximum height among the irregularities P1 having the trapezoidal shape is 5 占 퐉 or less and the height h2 of the irregularities having the maximum height among the irregularities P2 having the pyramidal shape is 15 占 퐉 Or less.

The bottom face B1 of the concavo-convex P1 having the trapezoidal shape may be the same as the bottom face B2 of the concavo-convex P2 having the pyramidal shape.

As described above, in the solar cell 1 according to the present invention, the irregularities P1 of the first shape formed in the region S1 overlapping the buffer layer 150 from the rear surface of the semiconductor substrate 110 overlap with the buffer layer 150 The irregularities P2 of the second shape formed in the region SE in contact with the emitter portion 121 in the rear surface of the semiconductor substrate 110 excluding the region S1 to be formed are clearly distinguished from each other in terms of the forming method, .

As described above, in the rear surface of the semiconductor substrate 110, except for the region S1 overlapping the buffer layer 150 and the region S1 overlapping the buffer layer 150, The solar cell 1 according to the present invention can further improve the power generation efficiency owing to the difference in the concavo-convex structure formed in the contact region SE.

1 and 2, the emitter section 121 and the rear electric section 172 are in contact with each other and the buffer layer 150 is separated from the semiconductor substrate 110 to form the emitter section 121 and the rear electric section 172. [ The emitter section 121 and the rear electric section 172 are spaced apart from each other and the buffer layer 150 is in contact with the semiconductor substrate 110, The present invention can be applied as it is in the case where it is formed between the rear electric conductor portion 121 and the rear electric conductive portion 172.

4 is a view for explaining a second embodiment of a solar cell according to the present invention.

4, the remaining portions are the same as those described with reference to FIGS. 1 to 3, except for the differences in the positions of the emitter 121, the rear electric portion 172, and the buffer layer 150, and a description thereof will be omitted .

4, the buffer layer 150 may be disposed between the emitter section 121 and the rear electric section 172 in contact with the semiconductor substrate 110, according to the second embodiment of the present invention.

4, the irregularities P1 having a first shape on the rear surface of the semiconductor substrate 110 are formed in a region S1 where the rear surface of the semiconductor substrate 110 and the buffer layer 150 are in contact with each other The concavo-convex P2 having the second shape can be formed in a region of the back surface of the semiconductor substrate 110 except for the region S1 where the back surface of the semiconductor substrate 110 and the buffer layer 150 are in contact with the emitter portion 121 (SE).

4, the irregularities P2 having the second shape may be formed on the rear surface of the semiconductor substrate 110 except the region S1 in which the rear surface of the semiconductor substrate 110 and the buffer layer 150 are in contact with each other. And may also be formed in the region SB abutting the step portion 172. [

The solar cell 1 according to the second embodiment of the present invention also has the trapezoidal shape of the side cross-sectional shape of the irregularities P1 having the first shape as described in the first embodiment, The shape of the side surface of the concavities and convexities P2 having a two-sided shape may include a pyramid shape to improve the efficiency of the solar cell 1.

1 to 4, the region where the concavities and convexities P2 having the second shape are formed is formed on the semiconductor substrate 110 except for the region S1 in which the rear surface of the semiconductor substrate 110 and the buffer layer 150 are in contact with each other. As shown in FIG. 5, the concavities and convexities P2 having the second shape are formed on the rear surface of the semiconductor substrate 110 and on the back surface of the semiconductor substrate 110, May be formed in a region SB of the rear surface of the semiconductor substrate 110 except for the region S1 in which the buffer layer 150 is in contact with the rear electric section 172. [

5 is a view for explaining a third embodiment of the solar cell according to the present invention.

5, the remaining portions are the same as those described with reference to FIGS. 1 to 3 except for the region where the concavities and convexities P2 having the second shape are formed, and a description thereof will be omitted.

5, in the solar cell 1 according to the present invention, irregularities P1 having a first shape are formed in the region S1 overlapping the buffer layer 150 from the rear surface of the semiconductor substrate 110 A recessed portion P2 having a second shape different from the first shape is formed in a region SB of the rear surface of the semiconductor substrate 110 that is in contact with the rear electric field portion 172 except the region S1 overlapping the buffer layer 150. [ Can be formed. As described above, the region SB in which the irregularities P2 having the second shape are formed in the rear surface of the semiconductor substrate 110 can be overlapped with the surface to which the second electrode 142 and the rear electric section 172 are bonded .

5, irregularities P1 having a first shape may be formed in a region SE of the semiconductor substrate 110, which is in contact with the emitter 121, from the rear surface thereof.

Therefore, irregularities P1 having a trapezoidal shape are formed in the region S1 overlapping the buffer layer 150 and the region SE contacting the emitter portion 121 from the rear surface of the semiconductor substrate 110, The irregularities P2 having a pyramidal shape may be formed in a region SB of the rear surface of the semiconductor substrate 110 that is in contact with the rear electric section 172. [ Even in such a case, as described above, the short-circuit current of the solar cell 1 can be further improved.

Further, the solar cell 1 according to the present invention may be formed as shown in the following FIG. 6, including both the cases of FIGS. 2 and 5 described above.

6 is a view for explaining a fourth embodiment of the solar cell 1 according to the present invention.

6, the remaining portions are the same as those described with reference to Figs. 1 to 3 except for the region where the concavities and convexities P2 having the second shape are formed, and a description thereof will be omitted.

6, unevenness P1 having a first shape is formed in a region S1 overlapping the buffer layer 150 from the rear surface of the semiconductor substrate 110 in the solar cell 1 according to the present invention And the region SE in contact with the emitter portion 121 and the region SB in contact with the backside electrical portion 172 in the rear surface of the semiconductor substrate 110 except for the region S1 overlapping the buffer layer 150, The concavities and convexities P2 having the second shape different from the shape of the concavities and convexities P2 can be formed.

Therefore, irregularities P1 having a trapezoidal shape are formed in the region S1 overlapping the buffer layer 150 from the rear surface of the semiconductor substrate 110, and the semiconductor substrate 110 except for the region S1 overlapping the buffer layer 150 An unevenness P2 having a pyramidal shape may be formed in an area SB in contact with the rear electric section 172 and an area SE in contact with the emitter section 121 in the rear surface of the emitter section 110. [

In this case, in the rear surface of the semiconductor substrate 110 excluding the region S1 overlapping with the buffer layer 150, both the region SB in contact with the rear electric section 172 and the region SE in contact with the emitter portion 121 The short circuit current can be further improved as compared with the solar cell 1 described with reference to Figs. 1 to 5 above.

Unevenness P1 having a trapezoidal shape is formed in the region S1 overlapping with the buffer layer 150 so far in the rear surface of the semiconductor substrate 110 excluding the region S1 overlapping with the buffer layer 150. [ Only the case where the unevenness P2 having the pyramidal shape is formed in at least one of the region SB contacting the electric system portion 172 and the region SE contacting the emitter portion 121 has been described.

The semiconductor substrate 110 in at least one region of the back surface of the semiconductor substrate 110 excluding the region S1 overlapping with the buffer layer 150 and in contact with the emitter portion 121 or the rear surface electric portion 172, Since the surface area per unit area of the rear surface of the semiconductor substrate 110 is only required to be larger than the surface area per unit surface of the rear surface of the semiconductor substrate 110 in the area S1 overlapping the buffer layer 150 from the rear surface of the semiconductor substrate 110, The same concavo-convex shape can be varied in various ways

Figs. 7 and 8 are views for explaining another example of the shape of the unevenness shown in Figs. 1 to 3; Fig.

Specifically, FIG. 8A is an enlarged view of the portion K1 'in FIG. 7, and FIG. 8B is an enlarged view of the portion K2' in FIG.

In FIGS. 7 and 8, the same elements as those described above with reference to FIGS. 1 to 6 are the same as those described above, and therefore, the description will be omitted.

The back surface of the semiconductor substrate 110 on the back surface of the semiconductor substrate 110 in at least one region of the back surface of the semiconductor substrate 110 excluding the region S1 overlapping with the buffer layer 150 is in contact with the emitter portion 121 or the back surface electric field portion 172, Since the surface area per unit area is only required to be larger than the surface area per unit area of the rear surface of the semiconductor substrate 110 in the area S1 overlapping the buffer layer 150 from the rear surface of the semiconductor substrate 110, In the rear surface of the semiconductor substrate 110, unevenness P1 'having a pyramidal shape is formed in a region S1 overlapping with the buffer layer 150. In the rear surface of the semiconductor substrate 110 excluding the region S1 overlapping the buffer layer 150, (P2 ') having a shape in which a plurality of irregularities having a small size are coupled to a slope of a pyramidal shape may be formed in at least one of the areas SE and SB contacting the rear electric conductor part 121 or the rear electric conductor part 172 have.

7 and 8A, a pyramid-shaped irregular surface P1 'is formed in a region S1 of the rear surface of the semiconductor substrate 110 which overlaps with the buffer layer 150 7A and 8B, a region SE in contact with the emitter portion 121 in the rear surface of the semiconductor substrate 110 except for the region S1 overlapping the buffer layer 150 is provided with a pyramid A concavity and convexity P2 'having a shape in which a plurality of concavities and convexities having a small size are combined is formed on the slope of the shape.

The irregularities P1 'formed in the region S1 overlapping the buffer layer 150 from the rear surface of the semiconductor substrate 110 are formed on the back surface of the semiconductor substrate 110 as shown in FIG. It is possible to perform saw damage etching by increasing the time of the wet etching or increasing the concentration of the etching solution.

In addition, a pyramidal slope formed in a region SE contacting the emitter portion 121 of the back surface of the semiconductor substrate 110 excluding the region S1 overlapping with the buffer layer 150 may be formed by a plurality of small irregularities The recessed portion P2 'having the recessed portion P2' is further subjected to dry etching only in the region SE to be brought into contact with the emitter portion 121 in the rear surface of the semiconductor substrate 110 excluding the region S1 to be overlapped with the buffer layer 150, Reactive ion etching (RIE) may be further performed.

The surface area per unit area of the rear surface of the semiconductor substrate 110 in the area in contact with the emitter section 121 in the rear surface of the semiconductor substrate 110 excluding the area S1 overlapping with the buffer layer 150 is defined as the surface area of the semiconductor substrate 110 The surface area per unit area of the rear surface of the semiconductor substrate 110 in the region S1 overlapping the buffer layer 150 may be larger than the surface area per unit area.

The junction surface of the semiconductor substrate 110 and the emitter section 121 or the junction surface of the semiconductor substrate 110 and the rear electric section 172 (not shown) except for the area S1 overlapping the buffer layer 150, The junction area between the emitter portion 121 and the first electrode 141 or between the rear surface electric portion 172 and the second electrode 142 can be made larger, It is possible to make the junction area of the front merged surfaces more. Accordingly, carriers can be collected more efficiently through the emitter section 121 and the rear electric section 172, and the short-circuit current of the solar cell 1 can be further improved.

Therefore, among the lights incident on the semiconductor substrate 110, light in a long wavelength band not absorbed by the semiconductor substrate 110 can be more efficiently dispersed through slopes having a more detailed concavo-convex form, and more efficiently reflected , There is an effect that more carriers can be generated in the semiconductor substrate 110. Thus, the short-circuit current of the solar cell 1 can be further improved.

7 and 8 illustrate an area of the rear surface of the semiconductor substrate 110 that is in contact with the emitter section 121 except the area S1 where the surface area per unit area of the back surface of the semiconductor substrate 110 overlaps the buffer layer 150 , But the same applies to Figs. 4 to 6.

The surface area per unit area of the rear surface of the semiconductor substrate 110 in a region in contact with the rear electric section 172 in the rear surface of the semiconductor substrate 110 excluding the area S1 overlapping with the buffer layer 150, The surface area per unit area of the rear surface of the semiconductor substrate 110 in the region S1 overlapping the buffer layer 150 in the rear surface of the semiconductor substrate 110 can be made larger.

8B may be provided in a region of the rear surface of the semiconductor substrate 110 other than the region S1 overlapping the buffer layer 150 in contact with the rear electric section 172. [

In addition, unlike the present embodiment, the side cross-sectional shape of the unevenness having the first shape includes a trapezoidal shape and the side sectional shape of the unevenness having the second shape is a trapezoidal inclined surface having a plurality of concave- . ≪ / RTI >

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, Of the right.

Claims (16)

A semiconductor substrate containing an impurity of a first conductivity type;
An emitter section disposed on a rear surface of the semiconductor substrate and having a second conductivity type opposite to the first conductivity type to form a pn junction with the semiconductor substrate;
A rear electric field portion disposed on a rear surface of the semiconductor substrate and containing impurities of the first conductive type at a higher concentration than the semiconductor substrate;
A first electrode formed on the emitter;
A second electrode formed on the rear electric field portion; And
And a buffer layer disposed between the first electrode and the second electrode on a rear surface of the substrate,
Wherein at least a portion of the back surface of the semiconductor substrate that is in contact with the emitter portion or the rear surface electric portion is formed of a back surface of the semiconductor substrate except for a region overlapping the buffer layer, And a second region having a second shape different from the first shape.
delete The method according to claim 1,
Wherein the irregularities having the first shape include a flat surface at the top, and the irregularities having the second shape do not include a flat surface at the top. The method according to claim 1,
Wherein the side cross-sectional shape of the unevenness having the first shape includes a trapezoidal shape, and the side cross-sectional shape of the unevenness having the second shape includes a pyramidal shape. The method according to claim 1,
Wherein a width of a flat surface formed at the top of the unevenness having the first shape is between 1 and 20 mu m. 5. The method of claim 4,
Wherein the maximum height of the irregularities having the trapezoidal shape is smaller than the height of the irregularities having the maximum height among the irregularities having the pyramidal shape. The method according to claim 6,
The maximum height of the concavities and convexities having the trapezoidal shape is 5 占 퐉, and the maximum height of the concavities and convexities having the pyramidal shape is 15 占 퐉. 5. The method of claim 4,
Wherein a bottom surface of the concavities and convexities having the trapezoidal shape is the same as the bottom surface of the concavo-convexes having the pyramidal shape. The method according to claim 1,
Wherein a region where the irregularities having the second shape are formed in the rear surface of the semiconductor substrate is overlapped with the junction surface between the first electrode and the emitter portion. The method according to claim 1,
Wherein a region of the rear surface of the semiconductor substrate where the irregularities having the second shape are formed overlaps a junction surface of the second electrode and the rear electric field portion. The method according to claim 1,
Wherein the emitter portion and the rear surface electric field portion are disposed on a junction surface between the emitter portion and the rear electric field portion, the sides of the emitter portion and the rear surface electric portion being in contact with each other, and the buffer layer being in contact with each other. The method according to claim 1,
Wherein the buffer layer comprises a nonconductive insulating material. The method according to claim 1,
Wherein the buffer layer comprises at least one of silicon oxide (SiOx) and silicon nitride (SiNx). The method according to claim 1,
Wherein the emitter portion and the rear electric field portion comprise crystalline silicon or amorphous silicon. The method according to claim 1,
Wherein the side cross-sectional shape of the concavities and convexities having the first shape includes a pyramidal shape, and the side cross-sectional shape of the concavo-convex having the second shape is a pyramidal shape having a plurality of concavities and convexities smaller than the pyramidal concavo- ≪ / RTI > The method according to claim 1,
The side cross-sectional shape of the unevenness having the first shape includes a trapezoidal shape, and the side cross-sectional shape of the unevenness having the second shape has a trapezoidal inclined surface having a plurality of concavities and convexities smaller than the trapezoidal concavo- ≪ / RTI >

Images