JP5346430B2 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which leakage current characteristic at the time of reverse direction operation is improved and, further, a manufacturing method is easy and a loss reduction at the time of forward direction conduction is possible, and to provide its manufacturing method. <P>SOLUTION: An n<SP>-</SP>-type epitaxial region 2 of the semiconductor device is formed on an n<SP>+</SP>-type substrate region 1; a lamination hetero semiconductor region 6 which consists of a p<SP>+</SP>-type lowermost layer hetero semiconductor region 3 in which band gaps are different from the epitaxial region 2, and a p<SP>+</SP>-type uppermost layer hetero semiconductor region 4 are formed on the epitaxial region 2; a first electrode 7 is connected to the uppermost layer hetero semiconductor region 4; a second electrode 8 is ohmically connected to the substrate region 1; and a part in which the arrangement of a crystal becomes discontinuous exists in a boundary between the lowermost layer hetero semiconductor region 3 and the uppermost layer hetero semiconductor region 4. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  As a prior art which is the background of the present invention, there is a “high voltage silicon carbide diode and a manufacturing method thereof” described in Patent Document 1 below.

The prior art is formed such that an N-type polycrystalline silicon region is in contact with one main surface of a semiconductor substrate in which an N ⁻ -type epitaxial region is formed on an N ⁺ -type silicon carbide substrate region. A heterojunction is formed with the N-type polycrystalline silicon region. A back electrode is formed on the back surface of the N ⁺ type silicon carbide substrate region.

  In the conventional technology configured as described above, when a voltage is applied between the back electrode as a cathode and the polycrystalline silicon region as an anode, a rectifying action occurs at the junction interface between the polycrystalline silicon region and the epitaxial region, and the diode characteristics are reduced. can get.

  For example, when a positive potential is applied to the anode with the cathode grounded, a conduction characteristic corresponding to the forward characteristic of the diode is obtained, and when a negative potential is applied to the anode, a blocking characteristic corresponding to the reverse characteristic of the diode is obtained. In addition, the forward characteristics and the reverse characteristics are characteristics such as a Schottky junction composed of a metal electrode and a semiconductor material.

In the prior art, by changing the impurity concentration and conductivity type of the polycrystalline silicon region, for example, a diode having predetermined reverse characteristics (and forward characteristics corresponding thereto) can be arbitrarily adjusted. Compared to the above, there is an advantage that an optimum withstand voltage system can be adjusted as required.
JP 2003-318413 A

  However, in the conventional structure, simply forming a heterojunction using polycrystalline silicon shows a tendency similar to that of a Schottky junction diode in terms of reverse current leakage current characteristics. In addition to the inability to extract the temperature characteristics, there is a limit to improving the leakage current characteristics during reverse operation due to the presence of crystal grain boundaries.

  The present invention has been made to solve the above-described problems of the prior art, and improves leakage current characteristics during reverse operation, and further facilitates a manufacturing method and reduces loss during forward conduction. An object of the present invention is to provide a semiconductor device capable of performing the above and a manufacturing method thereof.

A semiconductor substrate; a hetero semiconductor region in contact with the semiconductor substrate and having a different band gap from the semiconductor substrate; an anode electrode connected to the hetero semiconductor region; and a cathode electrode ohmically connected to the semiconductor substrate. in the second semiconductor device of the terminal for the hetero semiconductor region, that have a layered hetero semiconductor region in which a plurality of semiconductor layers arranged in the crystal is discontinuous in at least two layers of the boundary are stacked.

  By forming a semiconductor device in which the hetero semiconductor region has a stacked structure in which a plurality of semiconductor layers in which the crystal arrangement is discontinuous at the boundary between at least two layers are stacked, leakage current characteristics during reverse operation can be obtained. In addition to the improvement, it is possible to provide a semiconductor device that can be manufactured easily and can reduce loss during forward conduction, and a method for manufacturing the same.

  An outline of features and effects of the semiconductor device according to the present invention is as follows.

  When the epitaxial region that is the uppermost layer of the semiconductor substrate is N-type, the lowermost layer of the stacked hetero semiconductor region that is in contact with the epitaxial region is made P + -type so that the entire region is not depleted to reduce leakage current. . Further, in order to take advantage of the characteristics of the epitaxial region where the rate of occurrence of leakage current is small, the impurity concentration in the lowermost layer of the stacked hetero semiconductor region is set to a predetermined concentration.

  Furthermore, in the following embodiments, since the heterojunction diode is formed in the laminated hetero semiconductor region while using polycrystalline silicon composed of a large number of crystal grains, the conduction that becomes the majority carrier for the N-type epitaxial region. It is possible to reduce the supply of electrons from the anode electrode (first electrode) through the grain boundary of polycrystalline silicon, and further, a structure in which leakage current is difficult to occur.

  With this configuration, when a reverse bias is applied between the anode and the cathode of the heterojunction diode, the supply of electrons from the lowermost layer of the stacked hetero semiconductor region is dramatically reduced, so that the leakage current is greatly reduced.

  Details of the present invention will be described below with reference to embodiments.

[First Embodiment]
FIG. 1 shows a first embodiment of a semiconductor device according to the present invention. In this embodiment, a semiconductor device using silicon carbide as a substrate material will be described as an example.

  For example, an N− type epitaxial region 2 is formed on an N + type substrate region 1 whose silicon carbide polytype is 4H type. The joined body of the substrate region 1 and the epitaxial region 2 is a semiconductor substrate of the first conductivity type. In this case, the first conductivity type is an N type.

  As the substrate region 1, for example, one having a resistivity of several mΩcm to several tens mΩcm and a thickness of about 50 to 400 μm can be used.

As the epitaxial region 2, for example, an N-type impurity concentration of 10 ¹⁵ to 10 ¹⁸ cm ⁻³ and a thickness of several μm to several tens of μm can be used. In this embodiment, the impurity concentration is 10 ^16. The case where cm ⁻³ and a thickness of 10 μm are used will be described.

  In the present embodiment, as an example, a substrate having an epitaxial region 2 formed on the substrate region 1 will be described. However, a substrate formed only by the substrate region 1 with a corresponding resistivity is used as the first conductive layer. It may be used as a mold semiconductor substrate.

  The lowermost hetero semiconductor region 3 which is the lowermost semiconductor layer is deposited so as to be in contact with the main surface (one main surface of the semiconductor substrate of the first conductivity type) facing the bonding surface of the epitaxial region 2 with the substrate region 1. Yes. In the present embodiment, as an example, the case where the lowermost hetero semiconductor region 3 is made of polycrystalline silicon having a band gap smaller than that of silicon carbide is shown. The junction between epitaxial region 2 and lowermost hetero semiconductor region 3 is formed of a heterojunction made of materials having different band gaps between silicon carbide and polycrystalline silicon, and an energy barrier exists at the junction interface.

  Further, in the present embodiment, the uppermost heterogeneous layer made of polycrystalline silicon, which is the uppermost semiconductor layer, is stacked on the lowermost layer heterosemiconductor region 3 (lowermost layer polycrystalline silicon layer) which is the lowermost layer semiconductor layer. Semiconductor region 4 (uppermost polycrystalline silicon layer) is formed. Thus, in the present embodiment, the lowermost hetero semiconductor region 3 and the uppermost hetero semiconductor region 4 which are two semiconductor layers are stacked to form the stacked hetero semiconductor region 6, and this stacked hetero semiconductor region 6 is formed. The semiconductor region 6 plays a role as a hetero semiconductor region. For example, as shown in FIG. 2, an intermediate hetero semiconductor region which is a semiconductor layer between the lowermost hetero semiconductor region 3 and the uppermost hetero semiconductor region 4 The stacked hetero semiconductor region 6 may be formed by forming one or a plurality of intermediate layers 5 (intermediate polycrystalline silicon layers).

  Since the lowermost hetero semiconductor region 3 and the uppermost hetero semiconductor region 4 are both made of polycrystalline silicon, the crystal arrangement is discontinuous at the boundary between the two layers. Similarly, in the following embodiments, the discontinuity of the crystal arrangement is as long as at least one hetero semiconductor region layer that is a constituent element of the stacked hetero semiconductor region 6 is a polycrystalline layer. Realize. More generally, it is realized that such a crystal arrangement becomes discontinuous at the boundary between two layers, except that all of the hetero semiconductor region layers which are constituent elements of the stacked hetero semiconductor region 6 are epitaxial growth layers. .

  In the description of the present embodiment, impurities are introduced into the lowermost hetero semiconductor region 3 and the uppermost hetero semiconductor region 4, and here, the second conductivity type P-type high concentration (P + type) is doped. (Impurities are introduced).

  In the present embodiment, a first electrode 8 is formed on the upper surface of the uppermost hetero semiconductor region 4, and a second electrode 8 is formed on the lower surface side of the substrate region 1. The first electrode 7 and the second electrode 8 are ohmically connected to the uppermost hetero semiconductor region 4 and the substrate region 1, respectively. For example, as the metal material, the first electrode 7 is Ti (titanium). In addition, a material in which Al (aluminum) is deposited thereon can be used, and a material in which the second electrode 8 is deposited in Ti (titanium) and Ni (nickel) thereon can be used. As described above, in the present embodiment, a case where a vertical diode having the first electrode 7 as an anode electrode and the second electrode 8 as a cathode electrode is configured will be described.

  In the present embodiment, the effect of forming the stacked hetero semiconductor region 6 that is a feature thereof will be described with a configuration in which each region is deposited in layers as shown in FIG. 1 for easy understanding. However, as shown in FIGS. 3 to 6, there may be other structures on the outer periphery and inside. For example, as shown in FIGS. 3 and 4, in order to prevent electric field concentration at the end of the stacked hetero semiconductor region 6, the electric field relaxation region 9 (FIG. 3) may be formed as a P-type region, for example. The end of the laminated hetero semiconductor region 6 may run over the insulating region 10 (FIG. 4) made of an oxide film, for example. Of course, both the electric field relaxation region 5 and the insulating region 10 may be formed as shown in FIG. Further, as shown in FIG. 6, in order to conduct with a low resistance, a conduction region 11 made of, for example, an N-type region may be formed.

  Next, an example of a method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention shown in FIG. 1 will be described with reference to FIG.

(1) First, as shown in FIG. 9A, for example, an N type silicon carbide semiconductor substrate formed by epitaxially growing an N ⁻ type epitaxial region 2 on an N ⁺ type substrate region 1 is used. .

(2) Next, as shown in FIG. 9B, for example, after depositing a first layer of polycrystalline silicon by LP-CVD, boron doping is performed in, for example, a BBr ₃ atmosphere, and P The lowermost hetero semiconductor region 3 of the type is formed. The lowermost hetero semiconductor region 3 may be formed by being deposited by electron beam evaporation or sputtering and then recrystallized by laser annealing or the like, for example, a single crystal heteroepitaxially grown by molecular beam epitaxy or the like It may be formed of silicon. In addition, a combination of ion implantation and activation heat treatment after implantation may be used for doping.

(3) Further, as shown in FIG. 9C, after depositing a second layer of polycrystalline silicon on the lowermost hetero semiconductor region 3 by, for example, LP-CVD, for example, in a BBr ₃ atmosphere. Then, boron doping is performed to form the P-type uppermost hetero semiconductor region 4. The uppermost hetero semiconductor region 4 may also be formed by depositing by electron beam evaporation or sputtering and then recrystallizing by laser annealing or the like, for example, heteroepitaxial growth by molecular beam epitaxy or the like. You may form with the made single crystal silicon. In addition, a combination of ion implantation and activation heat treatment after implantation may be used for doping. Thus, the laminated hetero semiconductor region 6 is formed by the step of laminating a plurality of polycrystalline silicon layers.

  (4) Then, as shown in FIG. 9 (d), a mask material is formed by photolithography and etching as necessary, and the laminated hetero semiconductor region 6 is predetermined by, for example, reactive ion etching (dry etching). The second electrode 8 made of, for example, titanium (Ti) or nickel (Ni) is formed on the substrate region 1 corresponding to the back surface side, and the uppermost hetero semiconductor region 4 corresponding to the front surface side is formed. First, titanium (Ti) and aluminum (Al) are sequentially deposited to form the first electrode 7 to complete the semiconductor device according to the first embodiment of the present invention shown in FIG.

  As described above, the semiconductor device of this embodiment can be easily realized by a conventional manufacturing technique.

  Next, the operation of the present embodiment will be described.

  When a voltage is applied between the second electrode 8 as a cathode electrode and the first electrode 7 as an anode electrode, a rectifying action occurs at the junction interface between the lowermost hetero semiconductor region 3 and the epitaxial region 2, and the diode characteristics are reduced. can get.

  First, when the cathode electrode is set to the ground potential and a positive potential is applied to the anode electrode, a forward current flows. The forward characteristics at this time are the same as those of the Schottky junction diode. That is, the forward characteristic can flow a forward current with a voltage drop determined by the sum of the built-in potentials extending from the heterojunction portion to the epitaxial region 2 and the lowermost hetero semiconductor region 3.

  Next, when the cathode electrode is set to the ground potential and a negative potential is applied to the anode electrode, the reverse characteristic in the present embodiment shows a leakage current characteristic different from that of the Schottky junction diode. In the configuration of the present invention, as will be described later, this occurs through a hetero barrier at the heterojunction interface so that leakage current characteristics due to carriers generated under a predetermined electric field as seen in a PN junction diode become dominant. This is because the leakage current can be greatly reduced.

  Hereinafter, the reverse characteristics will be described in detail.

  The reverse characteristics of the Schottky junction diode are determined almost uniquely by the height of the Schottky barrier formed by the difference between the electron affinity of the semiconductor material and the work function of the Schottky metal. However, in the conventional structure and the heterojunction diode in the present embodiment, the reverse characteristics are largely determined by three elements. The first is the reverse blocking capability determined by the height of the heterobarrier formed by the difference in electron affinity of each semiconductor material, similar to the Schottky junction. The second is a leakage current supply capability determined by the generation source of majority carriers that is the source of the leakage current. The third is a withstand voltage holding capability in which the voltage applied to the heterojunction diode determines the potential distribution to both semiconductor materials depending on the dielectric constant and impurity concentration of each semiconductor material.

  In the present embodiment, the first reverse blocking capability is substantially determined by the semiconductor materials of the epitaxial region 2 made of silicon carbide and the lowermost hetero semiconductor region 3 made of silicon.

  Next, the second leakage current supply capability is remarkably smaller than that of the conventional structure so that conduction electrons that become majority carriers for the N-type epitaxial region 2 are less likely to be generated in the stacked hetero semiconductor region 6. It is configured to suppress the origin of conduction electrons. That is, the stacked hetero semiconductor region 6 is formed in a P-type, and the stacked hetero semiconductor region 6 is configured with an impurity concentration, a thickness, or the like that does not deplete the entire region. Regarding the former, it contributes to the fact that the laminated hetero semiconductor region 6 itself does not become a source of conduction electrons, and with respect to the latter, the laminated hetero semiconductor region 6 is depleted throughout, for example, the conduction electrons from the first electrode 7. It works so that no supply is made.

  Further, in the present embodiment, the heterojunction diode is formed by the laminated hetero semiconductor region 6 in which the hetero semiconductor regions made of polycrystalline silicon made up of a large number of crystal grains are stacked. The supply of conduction electrons as carriers from the anode electrode via the polycrystalline silicon grain boundary can be reduced. This can be explained by a model of polycrystalline silicon constituting the stacked hetero semiconductor region 6 shown in FIG. In FIG. 12, when the lowermost polycrystalline silicon 42 is formed on the silicon carbide semiconductor 41 which is the substrate region, silicon grains having a predetermined size are deposited. Further, when the uppermost polycrystalline silicon 43 is formed on the lowermost polycrystalline silicon 42, the uppermost layer is formed at an arbitrary position different from the crystal grain boundary 44 of the lowermost polycrystalline silicon generated between the grains of the lowermost polycrystalline silicon 42. A grain boundary 45 of polycrystalline silicon is formed. As shown in FIG. 15, the inventor of the present invention has confirmed this phenomenon through experiments. As can be seen from the cross-sectional TEM photograph of FIG. 15, the lowermost polycrystalline silicon layer and the uppermost polycrystalline silicon layer It can be seen that the crystal grain boundaries are not continuous.

  Thus, since the respective crystal grain boundaries of the uppermost hetero semiconductor region 4 in contact with the first electrode 7 that is the anode electrode and the lowermost hetero semiconductor region 3 in contact with the epitaxial region 2 are not continuous, compared to the conventional structure, The flow of conduction electrons through the crystal grain boundary can be reduced, and the leakage current can be further reduced.

  In the present embodiment, as an example, the case where the uppermost polycrystalline silicon 43 is formed on the lowermost polycrystalline silicon 42 and both are made of polycrystalline silicon is described. Even if the lowermost polycrystalline silicon 52 is formed on the silicon carbide semiconductor 51 and the uppermost single crystal silicon 53 is further formed thereon, the crystal grain boundary 54 of the lowermost polycrystalline silicon is the uppermost single crystal silicon. 53 does not extend, and the same effect as that shown in FIG. 12 can be obtained.

  As shown in FIG. 14, even when lowermost single-crystal silicon 62 is formed on silicon carbide semiconductor 61 and uppermost-layer polycrystalline silicon 63 is further formed thereon, Since the crystal defects 64 generated inside and the crystal grain boundaries 65 generated in the uppermost polycrystalline silicon 63 are not continuous, the same effect can be obtained.

  From the viewpoint of the third capability of withstanding voltage, it has the effect of suppressing carriers generated under a predetermined electric field on the semiconductor material side (here, the lowermost hetero semiconductor region 3 side) with a narrow band gap. By forming the lower hetero semiconductor region 3 to be P + type, it has a structure in which avalanche breakdown is unlikely to occur.

  As described above, in the present embodiment, when the epitaxial region 2 is N-type, the lowermost hetero semiconductor region 3 is P + -type so that the entire region is not depleted to reduce leakage current. ing. Further, in order to take advantage of the characteristics of the epitaxial region 2 where the rate of occurrence of leakage current is small, the impurity concentration of the lowermost hetero semiconductor region 3 is set high.

  Further, in the present embodiment, the heterojunction diode is formed in the stacked hetero semiconductor region 6 while using polycrystalline silicon made up of a large number of crystal grains, so that it becomes a majority carrier for the N-type epitaxial region 2. The amount of conduction electrons supplied from the anode electrode via the polycrystalline silicon grain boundary can be reduced, and a leakage current hardly occurs.

  With this configuration, when a reverse bias is applied between the anode and the cathode of the heterojunction diode, the supply of electrons from the lowermost hetero semiconductor region 3 is drastically reduced, so that the leakage current is greatly reduced.

[Second Embodiment]
In the first embodiment, description has been given in the case where both the lowermost hetero semiconductor region 3 and the uppermost hetero semiconductor region 4 are P + type, but in the present embodiment, the lowermost hetero semiconductor region 3 is the uppermost layer. This is the case of the P− type having a lower impurity concentration than the hetero semiconductor region 4, and this will also be described with reference to FIG.

  By adopting such a configuration, the following effects can be obtained. That is, when the second electrode 8 that is the cathode electrode is set to the ground potential and a positive potential is applied to the first electrode 7 that is the anode electrode, a forward current flows. The forward characteristics at this time are the same as those of the Schottky junction diode. However, in this embodiment, the lowermost hetero semiconductor region 3 is of a P− type, so that the P + shown in the first embodiment is used. Compared to the case of the mold, the forward current can flow with a low voltage drop. From this, it is possible to reduce a loss when a current flows in the forward direction.

  Moreover, even when a negative potential is applied to the anode electrode with the cathode electrode as the ground potential, the reverse blocking ability determined by the height of the heterobarrier, which is the three elements of the reverse characteristics, the majority carriers that cause the leakage current Since it has a leakage current supply capability determined by the generation source and a withstand voltage holding capability determined by potential distribution to both semiconductor materials, it exhibits low leakage current characteristics.

  Also in the present embodiment, the crystal grain boundaries of the uppermost hetero semiconductor region 4 in contact with the first electrode 7 that is the anode electrode and the lowermost hetero semiconductor region 3 in contact with the epitaxial region 2 are not continuous. The conduction electrons through the grain boundary can be reduced, and the leakage current can be further reduced. In the present embodiment as well, as in the first embodiment, the configuration shown in FIGS. 2 to 6 in which the basic structure is modified may be used.

  Next, an example of a particularly characteristic manufacturing method in the present embodiment will be described with reference to FIG.

(1) First, as shown in FIG. 9A, as in the first embodiment, for example, an N ⁻ type epitaxial region 2 is formed by epitaxial growth on an N ⁺ type substrate region 1. An N-type silicon carbide semiconductor substrate is used.

(2) Next, as shown in FIG. 9B, for example, after depositing the first layer of polycrystalline silicon (lowermost hetero semiconductor region 3) by LP-CVD,
(3) Further, as shown in FIG. 9C, a second layer of polycrystalline silicon (uppermost hetero semiconductor region 4) is deposited on the lowermost hetero semiconductor region 3 by, for example, LP-CVD. Thereafter, for example, using boron, ion implantation doping is performed on the second polycrystalline silicon layer (uppermost hetero semiconductor region 4), and a predetermined activation heat treatment is performed. Then, as apparent from the result of the experiment by the inventor of the present invention shown in FIG. 16, the impurity concentration becomes discontinuous at the junction between the second polycrystalline silicon layer and the first polycrystalline silicon layer. (Impurity concentrations in the layers are different across a junction located near 1 μm in depth). In this manner, the P-type lowermost hetero semiconductor region 3 and the uppermost hetero semiconductor region 4 are collectively formed before the doping step, and impurities are introduced into a plurality of layers by one doping. Can do. This simplifies the manufacturing process and enables manufacturing at low cost. At the boundary between the lowermost hetero semiconductor region 3 and the uppermost hetero semiconductor region 4 thus formed, the impurity concentration is discontinuous as shown in FIG.

  The present embodiment is greatly different from the second embodiment in that impurities are introduced into the uppermost hetero semiconductor region 4 by the step of introducing impurities into the uppermost hetero semiconductor region 4 and the uppermost hetero semiconductor region 4. The point is to introduce impurities. More generally, the uppermost polycrystalline silicon layer is formed on the lowermost polycrystalline silicon layer or on the single-layered or multi-layered intermediate polycrystalline silicon layer laminated on the lowermost polycrystalline silicon layer, In the process of introducing an impurity with a predetermined concentration into the uppermost polycrystalline silicon layer, an impurity with a concentration different from the predetermined concentration can be introduced into the lowermost polycrystalline silicon layer.

  (4) Finally, as in the first embodiment, as shown in FIG. 9D, a mask material is formed by photolithography and etching as necessary, for example, reactive ion etching ( The stacked hetero semiconductor region 6 is shaped into a predetermined shape by dry etching, and a second electrode 8 made of, for example, titanium (Ti) or nickel (Ni) is formed on the substrate region 1 corresponding to the back surface side. A first electrode 7 is formed on the uppermost hetero semiconductor region 4 corresponding to the surface side by sequentially depositing titanium (Ti) and aluminum (Al), and the first electrode of the present invention shown in FIG. The semiconductor device according to the embodiment is completed.

  As described above, the semiconductor device of this embodiment can reduce on-loss and simplify the manufacturing process.

[Third Embodiment]
In the first embodiment, when both the lowermost hetero semiconductor region 3 and the uppermost hetero semiconductor region 4 are P + type, in the second embodiment, the lowermost hetero semiconductor region 3 is the uppermost layer. In the present embodiment, the case where the P− type has a lower impurity concentration than the hetero semiconductor region 4 has been described, but in the present embodiment, the lowermost hetero semiconductor region 3 has a P + type first layer as shown in FIG. A case in which the lowermost hetero semiconductor region 23 and the P− type second lowermost hetero semiconductor region 24 are configured will be described.

  In FIG. 7, for example, an N− type epitaxial region 22 is formed on an N + type substrate region 21 whose silicon carbide polytype is 4H type. In the present embodiment, the substrate having the epitaxial region 22 formed on the substrate region 21 will be described as an example. However, the substrate formed only by the substrate region 21 having a corresponding resistivity is used. It doesn't matter.

  A P + type first lowermost hetero semiconductor region 23 and a P− type second lowermost hetero semiconductor region 24 are formed so as to be in contact with the main surface of the epitaxial region 22 facing the bonding surface with the substrate region 21. ing. Also in this embodiment, the case where the first lowermost hetero semiconductor region 23 and the second lowermost hetero semiconductor region 24 are made of polycrystalline silicon having a band gap smaller than that of silicon carbide is shown. Further, an uppermost hetero semiconductor region 25 made of P + type polycrystalline silicon is formed so as to be stacked on the first lowermost hetero semiconductor region 23 and the second lowermost hetero semiconductor region. Also in this embodiment, the hetero semiconductor region 26 composed of two layers is illustrated. However, as shown in FIG. 2 shown in the first embodiment, the hetero semiconductor region 26 is formed of three or more layers. Also good.

  Further, a first electrode 28 is formed on the upper surface of the uppermost hetero semiconductor region 25, and a second electrode 28 is formed on the lower surface side of the substrate region 21. The first electrode 27 is in ohmic contact with the uppermost hetero semiconductor region 25, and the second electrode 28 is in ohmic contact with the substrate region 21. In the present embodiment, the effect of forming the stacked hetero semiconductor region 26, which is a feature of the present embodiment, will be described with a basic structure for easy understanding. However, in the first embodiment, FIG. As illustrated in FIG. 6, other structures may be added to the outer periphery or the inside.

  Next, an example of a method for manufacturing the silicon carbide semiconductor device according to the third embodiment of the present invention shown in FIG. 7 will be described with reference to FIG. 10 only in steps different from the steps similar to those in the first embodiment. To do.

  (1) First, as shown in FIG. 10A, an N− type epitaxial region 22 is deposited on an N type silicon carbide semiconductor substrate formed by epitaxial growth on an N + type substrate region 21. Using a mask material formed by predetermined photolithography and etching on the first polycrystalline silicon layer, for example, using an ion implantation method, boron doping at a predetermined concentration is performed at predetermined intervals, respectively. Lower-layer hetero semiconductor region 23 and P-type second lower-layer hetero semiconductor region 24 are formed.

  (2) Further, as shown in FIG. 10B, a second layer of multi-layers is formed on the P + type first lowermost hetero semiconductor region 23 and the P− type second lowermost hetero semiconductor region 24. After the crystalline silicon is deposited, boron doping is similarly performed using, for example, an ion implantation method to form the P-type uppermost hetero semiconductor region 25. Further, after performing a predetermined activation heat treatment, a second electrode 28 made of, for example, titanium (Ti) or nickel (Ni) is formed on the substrate region 21 corresponding to the back surface side, and the outermost surface corresponding to the front surface side is formed. A first electrode 27 is formed on the upper hetero semiconductor region 25 by sequentially depositing titanium (Ti) and aluminum (Al), and the semiconductor device according to the third embodiment of the present invention shown in FIG. To complete.

  As described above, the semiconductor device of this embodiment can be easily realized by a conventional manufacturing technique.

  By adopting such a configuration, the following effects can be obtained.

  When the second electrode 28 serving as the cathode electrode is set to the ground potential and a positive potential is applied to the first electrode 27 serving as the anode electrode, the forward characteristics operate like a Schottky junction diode. Since the second lowermost hetero semiconductor region 24 is of the P− type, a forward current flows with a lower voltage drop than in the case of the P + type shown in the first embodiment. Can do. From this, it is possible to reduce a loss when a current flows in the forward direction.

  On the other hand, even when the cathode electrode is grounded and a negative potential is applied to the anode electrode, the reverse blocking ability determined by the height of the heterobarrier, which is the three elements of the reverse characteristics, the majority carriers that cause the leakage current Since it has a leakage current supply capability determined by the generation source and a withstand voltage holding capability determined by potential distribution to both semiconductor materials, it exhibits low leakage current characteristics.

  Also in the present embodiment, the uppermost hetero semiconductor region 25 in contact with the first electrode 27 that is the anode electrode, the first lowermost hetero semiconductor region 23 in contact with the epitaxial region 22, and the second lower hetero semiconductor region. Since the crystal grain boundaries of each of the 24 are not continuous, conduction electrons through the crystal grain boundaries can be reduced, and leakage current can be further reduced.

  Furthermore, in the present embodiment, unlike the second embodiment, the P + type first lowermost hetero semiconductor region 23 that forms a heterojunction with the epitaxial region 22 has a low resistance. Holes quickly generated at the time of avalanche breakdown generated when a negative potential is applied at a predetermined level or higher are applied to the first electrode 7 via the first lowermost hetero semiconductor region 23 and the uppermost hetero semiconductor region 25. Since it can discharge | emit, the destruction tolerance at the time of avalanche breakdown can be improved.

  As described above, the semiconductor device of this embodiment can reduce on-loss and improve breakdown resistance during reverse operation.

[Fourth Embodiment]
In the third embodiment, the first lowermost hetero semiconductor region 23 and the second lowermost hetero semiconductor region are introduced into the first polycrystalline silicon layer at two impurity concentrations at predetermined intervals. In the present embodiment, as shown in FIG. 8, the P− type lowermost hetero semiconductor region 33 and the P + type uppermost hetero semiconductor region 35 are both epitaxial regions. The case where it contacts 32 is demonstrated.

  By adopting such a configuration, the following effects can be obtained.

  The uppermost layer that is mainly in ohmic contact with the first electrode 37 during forward operation when the second electrode 38 that is the cathode electrode is set to the ground potential and a positive potential is applied to the first electrode 37 that is the anode electrode. Since a forward current flows through the hetero semiconductor region 35 to the heterojunction between the P − -type lowermost hetero semiconductor region 33 and the epitaxial region 32, a low voltage drop is applied as in the third embodiment. Current can flow. From this, it is possible to reduce a loss when a current flows in the forward direction.

  On the other hand, even when the cathode electrode is set to the ground potential and a negative potential is applied to the anode electrode, the present embodiment has a reverse blocking capability and a leakage current determined by the height of the heterobarrier, which are three elements of the reverse characteristics. The leakage current supply capability determined by the majority carrier generation source, the potential distribution to both semiconductor materials + the withstand voltage holding capability determined, so that the low leakage current is the same as in the third embodiment. Show properties.

  Furthermore, in the present embodiment, since the P + type uppermost hetero semiconductor region 35 that forms a heterojunction with the epitaxial region 32 is in direct contact, the potential of the anode electrode becomes a negative potential greater than or equal to a predetermined value. At the time of the avalanche breakdown that occurs, the generated holes can be quickly discharged to the first electrode 37 only through the uppermost hetero semiconductor region 35, so that the breakdown resistance at the time of avalanche breakdown can be further improved.

As for the manufacturing process, only the characteristic process is shown in FIG.
(1) First, as shown in FIG. 11A, a first-layer polycrystal deposited on an N-type silicon carbide semiconductor substrate including an N + -type substrate region 31 and an N-type epitaxial region 32. Using a mask material formed by predetermined photolithography and etching, the silicon layer is shaped into a predetermined shape by, for example, reactive ion etching (dry etching),
(2) Further, as shown in FIG. 11B, after depositing a second layer of polycrystalline silicon, boron doping is performed using an ion implantation method, and a predetermined activation heat treatment is performed. Then, as is apparent from the results of experiments by the inventors of the present invention shown in FIG. 16, the impurity concentration becomes discontinuous at the junction between the second polycrystalline silicon layer and the first polycrystalline silicon layer. Become. In this way, the P − type lowermost hetero semiconductor region 33 and the uppermost hetero semiconductor region 35 can be formed simultaneously. This simplifies the manufacturing process and enables manufacturing at low cost. Thereafter, a second electrode 38 made of, for example, titanium (Ti) or nickel (Ni) is formed on the substrate region 31 corresponding to the back surface side, and on the uppermost hetero semiconductor region 35 corresponding to the front surface side, The first electrode 37 is formed by sequentially depositing titanium (Ti) and aluminum (Al), and the semiconductor device according to the fourth embodiment of the present invention shown in FIG. 8 is completed.

  More generally, before performing the uppermost polycrystalline silicon layer forming step, the lowermost polycrystalline silicon layer is selectively etched using a predetermined mask pattern, and then the uppermost polycrystalline silicon layer forming step is performed. Thus, the uppermost polycrystalline silicon layer can be formed so as to be in contact with the semiconductor substrate directly or via a single-layer or multi-layer intermediate polycrystalline silicon layer.

  As described above, the semiconductor device of the above embodiment can further improve the breakdown tolerance and can be realized by simplifying the manufacturing process.

  In the above-described embodiment, as described in the first embodiment, the configuration corresponding to FIGS. 2 to 6 in which the basic structure is modified may be used.

[Fifth Embodiment]
FIG. 17 is a cross-sectional view of a semiconductor device when the semiconductor device according to the present invention has a gate electrode and functions as a field effect transistor. In the figure, in a predetermined region on the first main surface side of a semiconductor substrate 100 in which an N-type silicon carbide epitaxial layer 72 having an impurity concentration lower than that of the silicon carbide substrate 71 is formed on a high-concentration N-type silicon carbide substrate 71. An electric field relaxation region 73 is formed. Further, in a predetermined region on the first main surface side of the semiconductor substrate 100, a hetero semiconductor region 74 is formed in which heterojunction is formed and N-type polycrystalline silicon layers 80 and 81 having different band gaps from silicon carbide are stacked. Has been. The polycrystalline silicon layers 80 and 81 correspond to the lowermost semiconductor layer and the uppermost semiconductor layer of the hetero semiconductor region 74, respectively. A gate electrode 76 is formed so as to be in contact with the junction between the hetero semiconductor region 74 and the semiconductor substrate 100 via the gate insulating film 75. A source electrode 77 as a first electrode is formed so as to be connected to the hetero semiconductor region 74, and a drain electrode 78 as a second electrode is formed so as to be in ohmic contact with the semiconductor substrate 100. Further, the source electrode 77 and the gate electrode 76 are electrically insulated by the interlayer insulating film 90. Although not shown in FIG. 17, the electric field relaxation region 73 and the source electrode 77 are in contact with each other in the depth direction of the paper.

  Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS.

  As shown in FIG. 18A, a semiconductor substrate 100 is prepared in which an N-type silicon carbide epitaxial layer 72 having an impurity concentration lower than that of a silicon carbide substrate 71 is formed on a high-concentration N-type silicon carbide substrate 71. Thereafter, an electric field relaxation region 73 is formed in a predetermined region. For example, P-type silicon carbide or an insulating layer can be used for the electric field relaxation region 73.

  Next, as shown in FIG. 18B, for example, the polysilicon layer 80 / amorphous silicon layer 82 / polycrystalline silicon layer 81 are successively deposited by changing the deposition temperature in the order of CVD, for example. . The deposition temperature conditions at this time are, for example, a deposition temperature of the polycrystalline silicon layers 80 and 81 of 620 ° C. and a deposition temperature of the amorphous silicon layer 82 of 520 ° C. The film thicknesses of the polycrystalline silicon layers 80 and 81 are about 200 mm and the amorphous silicon layer 82 is 5000 mm, for example. In this way, by sequentially changing the deposition temperature and forming each layer continuously, a laminated structure as shown in the figure can be easily formed.

  Next, as shown in FIG. 18C, heat treatment is performed in a nitrogen atmosphere, and the upper and lower polycrystalline silicon layers 81 and 80 are used as seed layers to cause solid-phase crystal growth in the amorphous silicon layer 82. The amorphous silicon layer 82 is crystallized by solid phase crystal growth. At this time, crystal grains (grains) grown in a solid phase from the upper and lower polycrystalline silicon layers 81 and 80 collide with each other in the middle of the amorphous silicon layer 82, and two polycrystalline silicon layers 81 and 80 as shown in FIG. A hetero semiconductor region 74 having a stacked structure is formed. Further, a portion where the crystal grain arrangement is discontinuous is formed between the two polycrystalline silicon layers 81 and 80.

  Through these steps, the surface layer of each layer is exposed to the atmosphere in order to form each layer continuously, unlike the case where each layer is deposited to form a discontinuous portion of the crystal grain arrangement. Therefore, a natural oxide film is not formed in a portion where the arrangement of crystal grains is discontinuous or impurities are not attached.

  Although the case where the layer structure of the hetero semiconductor region 74 before the solid phase growth is the polycrystalline silicon layer 80 / amorphous silicon layer 82 / polycrystalline silicon layer 81 has been described here, the number of layers other than that is described. In this case, the same process may be used. For example, as shown in FIG. 20, the amorphous silicon layer 82 / polycrystalline silicon layer 81 are deposited in this order on the silicon carbide epitaxial layer 72 of the semiconductor substrate 100, and then heat treatment is performed to fix the amorphous silicon layer 82 in the amorphous silicon layer 82. Phase crystal growth may be caused, and the amorphous silicon layer 82 may be crystallized by solid phase crystal growth. In this case, solid-crystal growth occurs in the amorphous silicon layer 82 using the polycrystalline silicon layer 81 as a seed layer at the interface between the polycrystalline silicon layer 81 and the amorphous silicon layer 82. At the interface with the layer 82, crystallization of the amorphous silicon layer 82 proceeds based on randomly generated crystal nuclei, and a layer corresponding to the polycrystalline silicon layer 80 is formed. Also in this case, crystal grains grown from above and below collide with each other, and a portion where the arrangement of crystal grains becomes discontinuous is formed.

  Next, arsenic is ion-implanted into the hetero semiconductor region 74 composed of the plurality of polycrystalline silicon layers 80 and 81, and an activation heat treatment is performed to make it N-type. As the impurity introduction method, a diffusion method or the like may be used other than ion implantation. Thereafter, as shown in FIG. 19D, the hetero semiconductor region 74 is patterned by photolithography and etching.

  Next, after depositing a gate insulating film 75 and further depositing aluminum to be the gate electrode 76, as shown in FIG. 19E, the aluminum is patterned by photolithography and etching to form the gate electrode 76. To do.

  Next, after the interlayer insulating film 90 is deposited, a contact hole is formed by photolithography and etching, and a source electrode 77 is formed so as to be in contact with the hetero semiconductor region 74. Further, a drain electrode 78 is formed so as to be in contact with the silicon carbide substrate 71, and the semiconductor device according to the embodiment of the present invention is completed as shown in FIG.

  The operation of the semiconductor device thus manufactured as a specific semiconductor element will be described.

  This device is used by grounding the source electrode 77 and applying a positive drain voltage to the drain electrode 78. At this time, if the gate electrode 76 is grounded, the movement of electrons is blocked by the energy barrier at the heterojunction interface, so that no current flows between the source electrode 77 and the drain electrode 78 and a blocking state occurs. In addition, when a high voltage is applied between the source electrode 77 and the drain electrode 78, the electric field is terminated in the accumulation layer formed on the hetero semiconductor region 74 side of the heterojunction interface, and the hetero semiconductor region 74 does not break down. In addition, since the electric field applied to the heterojunction interface is relaxed by the electric field relaxation region 73, a high breakdown voltage between the source electrode 77 and the drain electrode 78 can be ensured.

  Further, similar to the first to fourth embodiments, since it has the hetero semiconductor region 74 which is composed of the polycrystalline silicon layers 80 and 81 and the crystal arrangement is discontinuous between the layers, the single layer is formed. Compared with the case where the polycrystalline silicon is used for the hetero semiconductor region 74, the reverse leakage current can be further reduced.

  Next, when an appropriate positive voltage is applied to the gate electrode 76, electrons are accumulated in the hetero semiconductor region 74 adjacent to the gate insulating film 75 and the silicon carbide epitaxial layer 72. As a result, the source electrode 77 has a predetermined drain voltage. Current flows between the drain electrode 78 and the drain electrode 78. That is, it becomes a conductive state.

  Further, when the positive voltage applied to the gate electrode 76 is removed, the electron accumulation layer disappears in the hetero semiconductor region 74 adjacent to the gate insulating film 75 and the silicon carbide epitaxial layer 72, and the energy barrier at the heterojunction interface causes The electrons are blocked and become blocked.

  In the semiconductor device according to the present embodiment, the stacked hetero semiconductor region 6 and the first electrode 7 of the semiconductor device shown in FIG. 3 are partially removed, and the gate insulating film 75 and the gate electrode 76 are removed at the removed portions. And has a structure in which a gate electrode 76 is in contact with a junction between the laminated hetero semiconductor region 6 and the semiconductor substrate via a gate insulating film 75. In the same manner, the stacked hetero semiconductor regions 6, 26, and 36 of the semiconductor device shown in FIGS. 1, 2, 4, 5, 6, 7, and 8 and the first electrodes 7, 27, and 37 are partially formed. The gate insulating film 75 and the gate electrode 76 are provided at the removed portion, and the gate electrode 76 is in contact with the junction between the stacked hetero semiconductor regions 6, 26 and 36 and the semiconductor substrate via the gate insulating film 75. A semiconductor device having the structure as described above can be configured. In this case, substrate regions 1, 21, and 31 correspond to silicon carbide substrate 71, epitaxial regions 2, 22, and 32 correspond to silicon carbide epitaxial layer 72, and lowermost hetero semiconductor regions 3, 23, 24, and 33 are formed. It corresponds to the polycrystalline silicon layer 80, the uppermost hetero semiconductor region 4, 25, 35 corresponds to the polycrystalline silicon layer 81, the stacked hetero semiconductor region 6, 26, 36 corresponds to the hetero semiconductor region 74, the first The electrodes 7, 27, and 37 correspond to the source electrode 77, and the second electrodes 8, 28, and 38 correspond to the drain electrode 78.

  In the first to fourth embodiments, when the stacked hetero semiconductor regions 6, 26, and 36 are manufactured, the polycrystalline silicon layer 80 or 81 and the amorphous silicon layer 82 in the present embodiment are in contact with each other. A method of crystallizing the amorphous silicon layer 82 by solid-phase crystal growth in the amorphous silicon layer 82 after forming the structure to be applied can be applied.

  As described above, in all the embodiments, the semiconductor device using silicon carbide (SiC) as the semiconductor base material has been described as an example. However, if the semiconductor base material is different from the material of the hetero semiconductor region, GaN, diamond, silicon Other semiconductor materials such as SiGe may also be used.

  In all the embodiments, the 4H type is used as the polytype of silicon carbide, but other polytypes such as 6H and 3C may be used.

  As for the material of the semiconductor layer in the stacked hetero semiconductor region, it is made of any of single crystal silicon, amorphous silicon, polycrystalline silicon, GaAs, Ge, SiGe, etc. as long as it is a material that forms a heterojunction with the substrate material. May be.

  In all the embodiments, the second electrode 8 (the drain electrode 78 in the fifth embodiment) and the first electrode 7 (the source electrode 77 in the fifth embodiment) are connected to the epitaxial region. 2 (the epitaxial layer 72 in the fifth embodiment) is arranged so as to be opposed to each other, and a so-called vertical structure diode (a transistor in the fifth embodiment) that allows current to flow in the vertical direction has been described. However, for example, the second electrode 8 (drain electrode 78 in the fifth embodiment) and the first electrode 7 (source electrode 77 in the fifth embodiment) are arranged on the same main surface. However, it may be a so-called lateral structure diode (a transistor in the fifth embodiment) in which current flows in the lateral direction.

  In the above embodiment, the lowermost hetero semiconductor region 3 (polycrystalline silicon layer 80 in the fifth embodiment) and the uppermost hetero semiconductor region 4 (polycrystalline silicon layer in the fifth embodiment). In the example of using polycrystalline silicon as the material used in 81), any material that forms a heterojunction with silicon carbide may be used.

  In addition, as an example, N-type silicon carbide is used as the epitaxial region 2 and P-type polycrystalline silicon is used as the lowermost hetero semiconductor region 3, but N-type silicon carbide and N-type silicon carbide are used respectively. Any combination of crystalline silicon, P-type silicon carbide and P-type polycrystalline silicon, P-type silicon carbide and N-type polycrystalline silicon may be used. That is, the first conductivity type may be N-type or P-type.

  Further, it goes without saying that modifications are included within the scope not departing from the gist of the present invention.

It is sectional drawing explaining the 1st and 2nd embodiment of this invention. It is sectional drawing explaining another 1st and 2nd embodiment of this invention. It is sectional drawing explaining another 1st and 2nd embodiment of this invention. It is sectional drawing explaining another 1st and 2nd embodiment of this invention. It is sectional drawing explaining another 1st and 2nd embodiment of this invention. It is sectional drawing explaining another 1st and 2nd embodiment of this invention. It is sectional drawing explaining the 3rd Embodiment of this invention. It is sectional drawing explaining the 4th Embodiment of this invention. It is a figure which shows an example of the manufacturing method of the 1st and 2nd embodiment of this invention. It is a figure which shows an example of the manufacturing method of the 3rd Embodiment of this invention. It is a figure which shows an example of the manufacturing method of the 4th Embodiment of this invention. It is an expanded sectional view of a lowermost hetero semiconductor region (polycrystalline silicon) and an uppermost hetero semiconductor region (polycrystalline silicon) junction. It is an expanded sectional view of a lowermost hetero semiconductor region (polycrystalline silicon) and an uppermost hetero semiconductor region (single crystal silicon) junction. It is an expanded sectional view of the lowermost hetero semiconductor region (single crystal silicon) and the uppermost hetero semiconductor region (polycrystalline silicon). It is a figure which shows an example of the experimental result regarding the cross-section of the lowermost hetero semiconductor region (lower polycrystalline silicon layer) and the uppermost hetero semiconductor region (upper polycrystalline silicon layer) junction. It is a figure which shows an example of the experimental result regarding the impurity diffusion distribution of the lowest layer hetero semiconductor region (polycrystalline silicon) and the uppermost layer hetero semiconductor region (polycrystalline silicon) junction. It is sectional drawing explaining the 5th form of this invention. It is a figure which shows an example of the manufacturing method of the 5th Embodiment of this invention. It is a continuation of FIG. It is a figure which shows the example of a partial change of the manufacturing method of the 5th Embodiment of this invention.

Explanation of symbols

  1: substrate region, 2: epitaxial region, 3: lowermost hetero semiconductor region, 4: uppermost hetero semiconductor region, 5: intermediate hetero semiconductor region, 6: stacked hetero semiconductor region, 7: first electrode, 8: Second electrode, 9: electric field relaxation region, 10: insulating region, 11: conduction region, 21: substrate region, 22: epitaxial region, 23: first lowermost hetero semiconductor region, 24: second lowermost hetero Semiconductor region, 25: uppermost hetero semiconductor region, 26: stacked hetero semiconductor region, 27: first electrode, 28: second electrode, 31: substrate region, 32: epitaxial region, 33: lowermost hetero semiconductor region, 35: uppermost hetero semiconductor region, 36: stacked hetero semiconductor region, 37: first electrode, 38: second electrode, 41: silicon carbide semiconductor, 42: lowermost polycrystalline silicon, 43: uppermost layer Crystalline silicon, 44: Grain boundary of lowermost polycrystalline silicon, 45: Grain boundary of uppermost polycrystalline silicon, 51: Silicon carbide semiconductor, 52: Lowermost polycrystalline silicon, 53: Uppermost single crystalline silicon, 54 : Crystal grain boundary of lowermost polycrystalline silicon, 61: silicon carbide semiconductor, 62: lowermost single crystal silicon, 63: uppermost polycrystalline silicon, 64: crystal defect, 65: crystal grain boundary, 71: silicon carbide substrate, 72: silicon carbide epitaxial layer, 73: electric field relaxation region, 74: hetero semiconductor region, 75: gate insulating film, 76: gate electrode, 77: source electrode, 78: drain electrode, 80, 81: polycrystalline silicon layer, 82 : Amorphous silicon layer, 90: interlayer insulating film, 100: semiconductor substrate.

Claims (15)

A cathode region formed of a semiconductor substrate of a first conductivity type; an anode region formed of a hetero semiconductor region in contact with one main surface of the semiconductor substrate and having a different band gap from the semiconductor substrate; and an anode connected to the hetero semiconductor region In a two-terminal semiconductor device having an electrode and a cathode electrode ohmically connected to the semiconductor substrate,
The hetero semiconductor region comprises a stacked hetero semiconductor region in which at least one semiconductor layer is formed by stacking a plurality of semiconductor layers having a polycrystalline structure ,
The uppermost semiconductor layer of the laminated hetero semiconductor region is connected to the anode electrode, the bottom layer of the semiconductor layer of the laminated hetero semiconductor region is in contact with the semiconductor substrate,
A semiconductor device, wherein a crystal grain boundary of the semiconductor layer having a polycrystalline structure is not continuous with a crystal grain boundary of another semiconductor layer .   The semiconductor device according to claim 1, wherein the stacked hetero semiconductor region has a portion in which an impurity concentration is discontinuous. The semiconductor device according to claim 1 or 2 uppermost semiconductor layer of the laminated hetero semiconductor region is characterized by connecting the anode electrode and the ohmic. The semiconductor device according to any one of 3 claims 1, wherein the uppermost semiconductor layer of the laminated hetero semiconductor region is a second conductivity type. 5. The semiconductor device according to claim 1, wherein the semiconductor substrate is in contact with the semiconductor layer other than the lowermost semiconductor layer of the stacked hetero semiconductor region.   6. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of any one of SiC, GaN, and diamond. 7. The semiconductor device according to claim 1 , wherein a material of the semiconductor layer forming the stacked hetero semiconductor region is any one of silicon, GaAs, Ge, and SiGe. 8. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming a stacked hetero semiconductor region of the semiconductor device includes stacking the semiconductor layers having a polycrystalline structure. And a process for stacking the other semiconductor layers comprising a different process . Forming a polycrystalline semiconductor layer of the lowermost layer on the semiconductor substrate, the top of the lowermost polycrystalline semiconductor layer, or a single layer or multiple layers stacked on the lowermost layer of the polycrystalline semiconductor layer in the intermediate layer forms the uppermost layer of polycrystalline semiconductor layer on the polycrystalline semiconductor layer, a top layer of polycrystalline semiconductor layer forming step, the process of introducing an impurity of a predetermined concentration in the polycrystalline semiconductor layer of the top layer the even lowermost polycrystalline semiconductor layer, a method of manufacturing a semiconductor device according to claim 8, characterized in that a step of introducing impurities of different concentrations from the predetermined concentration. Wherein before executing the uppermost polycrystalline semiconductor layer forming step, after selectively etching the polycrystalline semiconductor layer of the lowermost layer using a predetermined mask pattern, it performs the uppermost polycrystalline semiconductor layer forming step Te, the directly semiconductor substrate, or, according to claim 9, characterized in that a polycrystalline semiconductor layer of the uppermost layer in contact with the intermediate layer polycrystalline semiconductor layer of the single layer or multiple layers Semiconductor device manufacturing method. Forming an amorphous semiconductor layer in contact with the semiconductor layer having a polycrystalline structure, the semiconductor device according to claim 8, characterized in that a step of crystallizing the solid-phase crystal growth the amorphous semiconductor layer Production method. And a step of forming an amorphous semiconductor layer sandwiched between a semiconductor substrate of the semiconductor device and the semiconductor layer having a polycrystalline structure , and a step of crystallizing the amorphous semiconductor layer by solid-phase crystal growth. A method for manufacturing a semiconductor device according to claim 8. 9. The method of claim 8, further comprising: forming an amorphous semiconductor layer sandwiched between two semiconductor layers having the polycrystalline structure; and crystallizing the amorphous semiconductor layer by solid-phase crystal growth. A method for manufacturing a semiconductor device. 14. The step of forming the amorphous semiconductor layer and the step of forming the semiconductor layer having a polycrystalline structure are continuously performed by continuously changing a forming temperature. A method for manufacturing a semiconductor device according to any one of the above. A cathode region formed of a semiconductor substrate of a first conductivity type; an anode region formed of a hetero semiconductor region in contact with one main surface of the semiconductor substrate and having a different band gap from the semiconductor substrate; and an anode connected to the hetero semiconductor region In a two-terminal semiconductor device having an electrode and a cathode electrode ohmically connected to the semiconductor substrate,
  The hetero semiconductor region comprises a stacked hetero semiconductor region in which at least one semiconductor layer is formed by stacking a plurality of semiconductor layers having a polycrystalline structure,
  The uppermost semiconductor layer of the stacked hetero semiconductor region is connected to the anode electrode, the lowermost semiconductor layer of the stacked hetero semiconductor region is in contact with the semiconductor substrate,
  A semiconductor device, wherein a crystal grain boundary of the semiconductor layer having a polycrystalline structure is not continuous with a crystal defect generated in another semiconductor layer.

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