JP5368722B2 - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which enhances forward surge breakdown strength while maintaining a high reverse breakdown voltage. <P>SOLUTION: A semiconductor device 1 includes an n<SP>+</SP>-type silicon carbide single crystal substrate 102, an n<SP>-</SP>-type silicon carbide epitaxial layer 104, a polysilicon layer 106, and a back electrode 110, wherein a p-type impurity region 108 is formed on the surface of the n<SP>-</SP>-type silicon carbide epitaxial layer 104 to include the end of the polysilicon layer 106 on the plan view, and an n<SP>--</SP>-type impurity region 112 containing n-type impurities at a lower concentration than that of the n<SP>-</SP>-type silicon carbide epitaxial layer 104 is formed near the surface of the n<SP>-</SP>-type silicon carbide epitaxial layer 104 surrounded by the p-type impurity region 108. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a heterojunction.

  A semiconductor device using silicon carbide as a semiconductor material has excellent characteristics such as high breakdown voltage, low loss, low leakage current, high temperature operation, and high speed operation. Conventionally, in such a semiconductor device, a semiconductor device having a heterojunction instead of a Schottky junction or a pn junction is known (see, for example, Patent Document 1). FIG. 13 is a diagram for explaining a conventional semiconductor device 901. FIG. 13A is a plan view of the semiconductor device 901, and FIG. 13B is a cross-sectional view taken along line AA in FIG.

As shown in FIG. 13, conventional semiconductor device 901 includes an n ⁻ type silicon carbide epitaxial containing an n ⁺ type impurity at a lower concentration than n ⁺ type silicon carbide single crystal substrate 902 and n ⁺ type silicon carbide single crystal substrate 902. a silicon carbide semiconductor substrate 900 having a layer 904, n ^- type silicon carbide is formed on a part of the surface of the epitaxial layer 904, n ^- polysilicon layer 906 to form an interface heterojunction between -type silicon carbide epitaxial layer 904 And a back electrode 910 formed on the back surface of n ⁺ -type silicon carbide single crystal substrate 902, and includes an end portion of polysilicon layer 906 on the surface of n ⁻ -type silicon carbide epitaxial layer 904 in plan view. Thus, the semiconductor device has the p-type impurity region 908 formed therein. The conventional semiconductor device 901 is a heterojunction diode. N ⁻ type silicon carbide epitaxial layer 904 is formed on n ⁺ type silicon carbide single crystal substrate 902.

According to the conventional semiconductor device 901, when the n ⁺ -type silicon carbide single crystal substrate 902 is grounded and a positive potential is applied to the polysilicon layer 906, the forward characteristics of the diode can be obtained. When a negative potential is applied to the polysilicon layer 906, the reverse characteristics of the diode can be obtained. According to the conventional semiconductor device 901, arbitrary forward characteristics and reverse characteristics can be obtained by changing the impurity concentration and conductivity type of the polysilicon layer 906. Note that this feature is compared to a semiconductor device having a Schottky junction, which has a feature that it is not easy to obtain arbitrary forward characteristics and reverse characteristics because the degree of freedom in selecting a barrier metal is narrow. This is a big advantage.

By the way, in a semiconductor device having a normal heterojunction, at the time of reverse bias, a high electric field strength portion is formed in the vicinity of the end portion of the polysilicon layer on the surface of the n ⁻ type silicon carbide epitaxial layer. Can't get. On the other hand, according to the conventional semiconductor device (semiconductor device having a heterojunction) 901, the p-type impurity region 908 is in contact with the end of the polysilicon layer 906 on the surface of the n ⁻ type silicon carbide epitaxial layer 904. Therefore, at the time of reverse bias, the inside of p-type impurity region 908 is depleted, resulting in a high electric field formed near the end of polysilicon layer 906 on the surface of n ⁻ -type silicon carbide epitaxial layer 904. It is possible to reduce the electrolytic strength of the strength portion, and a high reverse breakdown voltage can be obtained.

Japanese Patent Laying-Open No. 2003-318413 (FIG. 17)

  By the way, in such a semiconductor device (semiconductor device having a heterojunction), as in the case of a semiconductor device having a pn junction or a Schottky junction, the forward surge breakdown resistance is increased while maintaining a high reverse breakdown voltage. It is demanded.

  Therefore, the present invention has been made in view of such circumstances, and an object thereof is to provide a semiconductor device capable of increasing the forward surge breakdown withstandability while maintaining a high reverse breakdown voltage.

(1) A semiconductor device according to the present invention includes a first conductivity type first silicon carbide layer and a first conductivity type impurity formed on the first silicon carbide layer and having a lower concentration than the first silicon carbide layer. A second silicon carbide layer of the first conductivity type containing, a silicon layer formed on a part of the surface of the second silicon carbide layer and forming a heterojunction at the interface with the second silicon carbide layer; A back electrode formed on the back surface of the first silicon carbide layer, and the surface of the second silicon carbide layer or the vicinity of the surface includes all or part of the end of the silicon layer as viewed in plan. The second conductivity type impurity region is formed on the surface of the second silicon carbide layer in at least a part or all of the region surrounded by the second conductivity type impurity region. A first conductivity type impurity region containing a low concentration of the first conductivity type impurity is formed. And wherein the Rukoto.

  Therefore, according to the semiconductor device of the present invention, the second conductivity type impurity region is included in the surface of the second silicon carbide layer or in the vicinity of the surface so as to include all or part of the end portion of the silicon layer as viewed in plan. Therefore, at the time of reverse bias, the inside of the second conductivity type impurity region is depleted, and as a result, the electric field of the high electric field strength portion formed near the edge of the silicon layer on the surface of the second silicon carbide layer The strength can be lowered, and a high reverse breakdown voltage can be obtained.

  In addition, according to the semiconductor device of the present invention, the concentration near the surface of the second silicon carbide layer in all or part of the region surrounded by the second conductivity type impurity region is lower than that of the second silicon carbide layer. Since the first conductivity type impurity region containing the first conductivity type impurity is formed, the electric field strength in the vicinity of the heterojunction interface can be made lower than that in the case of the conventional semiconductor device 901 at the time of reverse bias. As a result, a higher reverse breakdown voltage than that of the conventional semiconductor device 901 can be obtained.

  For this reason, according to the semiconductor device of the present invention, it is possible to obtain a desired reverse breakdown voltage even if the thickness of the second silicon carbide layer as a so-called drift layer is reduced. As a result, according to the semiconductor device of the present invention, since the thickness of the second silicon carbide layer can be reduced and the resistance of the second silicon carbide layer can be lowered, the forward surge in the second silicon carbide layer can be reduced. Generation of Joule heat due to voltage or forward surge current can be suppressed. Therefore, the semiconductor device of the present invention is a semiconductor device capable of increasing the forward surge breakdown resistance while maintaining a high reverse breakdown voltage.

  According to the semiconductor device of the present invention, since the first conductivity type impurity region is formed not near the surface of the second silicon carbide layer but near the surface of the second silicon carbide layer, the first conductivity type impurity region is Compared with the case where it is formed on the surface of the second silicon carbide layer, the concentration of the first conductivity type impurity on the surface of the second silicon carbide layer can be increased, and as a result, the reverse recovery time trr is shortened. It becomes possible.

  According to the semiconductor device of the present invention, when the first conductivity type impurity region is formed in the vicinity of the surface of the second silicon carbide layer, the first conductivity type impurity region is formed on the surface of the second silicon carbide layer. Since the step of implanting the second conductivity type impurity ions with higher energy is performed as compared with the case, the amount of the second conductivity type impurity ions that are wasted without being implanted into the second silicon carbide layer is reduced. As a result, it is possible to reduce contamination caused by the second conductivity type impurity ions that are wasted without being implanted into the second silicon carbide layer.

(2) In the semiconductor device of the present invention, the first conductivity type impurity region is formed so that the depth of the shallowest portion is shallower than the depth of the deepest portion of the second conductivity type impurity region. It is preferable.

  With this configuration, it is possible to sufficiently reduce the electric field strength in the vicinity of the heterojunction interface at the time of reverse bias, and thus it is possible to sufficiently increase the forward surge breakdown resistance.

(3) In the semiconductor device of the present invention, the thickness of the second silicon carbide layer is preferably in the range of 3 μm to 20 μm.

  By reducing the thickness of the second silicon carbide layer in this way, it becomes possible to reduce the resistance of the second silicon carbide layer, and therefore, due to the forward surge voltage or forward surge current in the second silicon carbide layer. Generation of Joule heat can be sufficiently suppressed.

(4) In the semiconductor device of the present invention, the second silicon carbide layer contains a first conductivity type impurity having a higher concentration than the second silicon carbide layer and a lower concentration than the first silicon carbide layer. Preferably, the first silicon carbide layer is formed via a one-conductivity type low-resistance silicon carbide layer.

  By comprising in this way, since it becomes possible to comprise a drift layer with a 2nd silicon carbide layer and a low resistance silicon carbide layer, compared with the case where a drift layer is comprised only with a 2nd silicon carbide layer. The resistance of the drift layer can be lowered. For this reason, it becomes possible to suppress the generation of Joule heat due to the forward surge voltage or forward surge current in the drift layer. As a result, the forward surge breakdown resistance is further increased while maintaining a high reverse breakdown voltage. Is possible.

(5) In the semiconductor device of the present invention, the second silicon carbide layer is provided in a region facing the first conductivity type impurity region on the surface of the second silicon carbide layer on the side in contact with the first silicon carbide layer. It is preferable that a first conductive type low-resistance silicon carbide region containing a first conductive type impurity having a higher concentration than the first silicon carbide layer is formed.

  By comprising in this way, since it becomes possible to comprise a drift layer with a 2nd silicon carbide layer and a low resistance silicon carbide area | region, compared with the case where a drift layer is comprised only with a 2nd silicon carbide layer. The resistance of the drift layer can be lowered. For this reason, it becomes possible to suppress the generation of Joule heat due to the forward surge voltage or forward surge current in the drift layer. As a result, the forward surge breakdown resistance is further increased while maintaining a high reverse breakdown voltage. Is possible.

(6) In the semiconductor device of the present invention, the silicon layer is preferably made of polysilicon.

  With this configuration, it is possible to form a silicon layer by a relatively simple process, and as a result, a semiconductor device having a heterojunction can be manufactured by a relatively simple process.

(7) In the semiconductor device of the present invention, it is preferable that an impurity of a first conductivity type or a second conductivity type is introduced into the silicon layer.

  With this configuration, it is possible to obtain arbitrary forward characteristics and reverse characteristics by changing the type and concentration of impurities to be introduced.

  Hereinafter, a semiconductor device of the present invention will be described based on an embodiment shown in the drawings.

[Embodiment 1]
1. Configuration of Semiconductor Device 1 According to First Embodiment FIG. 1 is a diagram for explaining the semiconductor device 1 according to the first embodiment. FIG. 1A is a plan view of the semiconductor device 1, and FIG. 1B is a cross-sectional view taken along the line AA in FIG.

As in the case of the conventional semiconductor device 901, the semiconductor device 1 according to the first embodiment includes an n ⁺ type silicon carbide single crystal substrate (first silicon carbide layer) 102 and an n ⁺ type silicon carbide as shown in FIG. Silicon carbide semiconductor substrate 100 having an n ⁻ type silicon carbide epitaxial layer (second silicon carbide layer) 104 containing an n type impurity (first conductivity type impurity) at a lower concentration than single crystal substrate 102, and n ⁻ type carbonization A polysilicon layer (silicon layer) 106 formed on a part of the surface of silicon epitaxial layer 104 and forming a heterojunction at the interface with n ⁻ type silicon carbide epitaxial layer 104, and n ⁺ type silicon carbide single crystal substrate 102 A back electrode 110 formed on the back surface of the n ^- type silicon carbide epitaxial layer 104, and the surface of the n ⁻ -type silicon carbide epitaxial layer 104 includes a p-type impurity region so as to include an end portion of the polysilicon layer 106 in plan view. This is a semiconductor device (heterojunction diode) in which a region (second conductivity type impurity region) 108 is formed.

N ⁻ type silicon carbide epitaxial layer 104 is formed on n ⁺ type silicon carbide single crystal substrate 102. Further, at least in the region surrounded by p-type impurity region 108, in the vicinity of the surface of n ⁻ -type silicon carbide epitaxial layer 104 (a position slightly lower than the actual surface), it is smaller than n ⁻ -type silicon carbide epitaxial layer 104. An n ⁻⁻ type impurity region (first conductivity type impurity region) 112 containing a low concentration n-type impurity is formed. In the n ⁻⁻ type impurity region 112, the depth of the shallowest portion (the portion in contact with the n ⁻ type region 104 a in the n ⁻⁻ type impurity region 112) is shallower than the depth of the deepest portion of the p type impurity region 108. It is formed as follows.

As the n ⁺ -type silicon carbide single crystal substrate 102, a substrate having an n-type impurity concentration of, for example, about 5 × 10 ¹⁷ cm ^{−3 to} 5 × 10 ¹⁹ cm ⁻³ and a thickness of, for example, about 30 μm to 400 μm can be used. . Further, as the crystal polymorph of the n ⁺ -type silicon carbide single crystal substrate 102, for example, 4H can be used.

As n ⁻ type silicon carbide epitaxial layer 104, an n type impurity concentration of about 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ and a thickness of about ³ μm to 20 μm can be used, for example.

  As the polysilicon layer 106, for example, a polysilicon layer containing an n-type impurity can be used. The polysilicon layer 106 may be used as an anode electrode as it is, or a metal film (for example, a laminated film in which titanium and aluminum are laminated or a nickel film) that can be ohmic-connected to the polysilicon layer 106 is used as an anode electrode. Also good.

  As the back electrode 110, for example, an electrode made of a laminated film in which titanium, nickel, and silver are laminated can be used. The back electrode 110 becomes a cathode electrode.

The p-type impurity region 108 has a depth of about 0.2 μm to 1.0 μm, for example, and a p-type impurity concentration of about 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ , for example. P type impurity region 108 is formed in a ring shape on the surface of n ⁻ type silicon carbide epitaxial layer 104 (see FIG. 1A).

The n ⁻⁻ type impurity region 112 has a shallowest portion having a depth of about 0.2 μm to 0.5 μm, for example, and a deepest portion having a depth of about 0.4 μm to 1.0 μm, for example. The concentration is, for example, about 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ .

2. Method for Manufacturing Semiconductor Device 1 According to Embodiment 1 FIGS. 2 and 3 are views for explaining a method for manufacturing the semiconductor device 1. 2A to 2C and FIGS. 3A to 3C are process diagrams.

  The semiconductor device 1 according to the first embodiment can be manufactured by performing the following steps (S1) to (S6) as shown in FIGS.

(S1) the semiconductor substrate preparation step n ⁺ -type silicon carbide single-crystal substrate 102 (thickness: 400 [mu] m, the impurity ^{concentration: 1 × 10 19 cm -3)} n on the upper surface of the ^- type silicon carbide epitaxial layer 104 (thickness: 10 [mu] m, A silicon carbide semiconductor substrate 100 having an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ ) is prepared (see FIG. 2A).

(S2) First p-type impurity introduction step First, the surface of silicon carbide semiconductor substrate 100 is cleaned. Thereafter, a mask M1 having an opening in a portion corresponding to p type impurity region 108 is formed on the surface of silicon carbide semiconductor substrate 100. Thereafter, a relatively large amount of boron ions as a p-type impurity is implanted into a predetermined portion 107 of the n ⁻ -type silicon carbide epitaxial layer 104 through the mask M1 (see FIG. 2B). In the first p-type impurity introduction step, boron ions may be implanted under conditions where a thin silicon oxide film or the like is present in the opening of the mask M1.

(S3) Second p-type impurity introduction step First, the mask M1 is removed. Thereafter, a mask M <b> 2 having an opening in a portion corresponding to n ⁻⁻ type impurity region 112 is formed on the surface of silicon carbide semiconductor substrate 100. Thereafter, a relatively small amount of boron ions as a p-type impurity is implanted into the predetermined portion 111 of the n ⁻ -type silicon carbide epitaxial layer 104 through the mask M2 with a higher energy than in the first p-type impurity introduction step. (See FIG. 2 (c)). As a result, a region that does not contain boron ions is formed in a portion shallower than predetermined portion 111 of n ⁻ -type silicon carbide epitaxial layer 104 (portion indicated by symbol R in FIG. 2C). In the second p-type impurity introduction step, boron ions may be implanted under conditions where a thin silicon oxide film or the like exists in the opening of the mask M2.

(S4) Impurity activation step First, the mask M2 is removed. Thereafter, after forming a protective resist layer (not shown) on the front and back surfaces of the silicon carbide semiconductor substrate 100, the protective resist layer is carbonized to form graphite masks M3 and M4 (see FIG. 3A). ). Thereafter, p-type impurities are activated by heating silicon carbide semiconductor substrate 100 to a temperature of 1600 ° C. or higher, and p-type impurity regions 108 (depth: 0.5 μm, surface p-type impurity concentration: 1.0 × 10 ¹⁷ cm ⁻³ ) and n ⁻⁻ type impurity region 112 (depth: 0.25 μm to 0.75 μm, n type impurity concentration at depth 0.25 μm: 1.0 × 10 ¹⁵ cm ⁻³ ). (See FIG. 3 (a)). An n ⁻ type region 104 a is formed in a portion shallower than the n ^{− −} type impurity region 112.

(S5) Polysilicon layer forming step First, the graphite masks M3 and M4 are removed. Thereafter, a polysilicon layer 106 containing an n-type impurity is formed on a part of the surface of silicon carbide semiconductor substrate 100 (see FIG. 3B).

(S6) Back Electrode Formation Step Back electrode 110 made of a laminated film in which titanium, nickel and silver are laminated on the back surface of silicon carbide semiconductor substrate 100 is formed (see FIG. 3C).

  By performing the above steps, the semiconductor device 1 according to the first embodiment can be manufactured.

3. Effects of Semiconductor Device 1 According to Embodiment 1 According to semiconductor device 1 according to Embodiment 1, the surface of n ⁻ -type silicon carbide epitaxial layer 104 includes an end portion of polysilicon layer 106 in plan view. Since the p-type impurity region 108 is formed at the time of reverse bias, the inside of the p-type impurity region 108 is depleted, so that the vicinity of the end of the polysilicon layer 106 on the surface of the n ⁻ -type silicon carbide epitaxial layer 104 It is possible to reduce the electric field strength of the high electric field strength portion formed at the same, and a high reverse breakdown voltage can be obtained.

Further, according to the semiconductor device 1 according to Embodiment 1, in the area surrounded by the p-type impurity regions 108, n ^- In the vicinity of the surface of the -type silicon carbide epitaxial layer 104, n ^- than -type silicon carbide epitaxial layer 104 Since the n ⁻⁻ type impurity region 112 containing an n-type impurity at a low concentration is formed, the electric field strength at the heterojunction interface can be made lower than that in the conventional semiconductor device 901 at the time of reverse bias. As a result, a higher reverse breakdown voltage than that of the conventional semiconductor device 901 can be obtained.

For this reason, according to semiconductor device 1 according to the first embodiment, a desired reverse breakdown voltage can be obtained even if the thickness of n ⁻ -type silicon carbide epitaxial layer 104 as a so-called drift layer is reduced. As a result, according to the semiconductor device 1 according to the embodiment 1, n ^- -type thickness thinned by the silicon carbide epitaxial layer 104 n ^- since it is possible to lower the resistance of the -type silicon carbide epitaxial layer 104, Generation of Joule heat due to forward surge voltage or forward surge current in n ⁻ -type silicon carbide epitaxial layer 104 can be suppressed. Therefore, the semiconductor device 1 according to the first embodiment is a semiconductor device capable of increasing the forward surge breakdown resistance while maintaining a high reverse breakdown voltage.

Further, according to the semiconductor device 1 according to the embodiment 1, n ^- -type impurity regions 112, n ^- -type not the surface of the silicon carbide epitaxial layer 104 n ^- is formed near the surface of the -type silicon carbide epitaxial layer 104 are therefore, n ^- as compared to the case of being formed on the surface of the -type silicon carbide epitaxial layer 104, n ^{- -} -type impurity region n increasing the concentration of n-type impurity at the surface of the -type silicon carbide epitaxial layer 104 As a result, the reverse recovery time trr can be shortened.

Further, according to the semiconductor device 1 according to the embodiment 1, n ^- n in the vicinity of the surface of the -type silicon carbide epitaxial layer 104 ^- when -type impurity regions 112, n ^- surface of -type silicon carbide epitaxial layer 104 Compared with the case where the n ⁻⁻ type impurity region is formed in the n ⁻ type impurity region, the step of implanting the p type impurity ions with higher energy is performed, so that the n ⁻ type silicon carbide epitaxial layer 104 is not implanted and is wasted. It is possible to reduce the amount of p-type impurity ions, and as a result, it is possible to reduce contamination caused by p-type impurity ions that are wasted without being implanted into the n ⁻ -type silicon carbide epitaxial layer 104. Become.

Further, according to the semiconductor device 1 according to the first embodiment, the n ⁻⁻ type impurity region 112 is formed so that the depth of the shallowest portion is shallower than the depth of the deepest portion of the p-type impurity region 108. Therefore, it is possible to sufficiently reduce the electric field strength in the vicinity of the heterojunction interface at the time of reverse bias, and thus it is possible to sufficiently increase the forward surge breakdown resistance.

According to semiconductor device 1 in accordance with the first embodiment, since n ⁻ type silicon carbide epitaxial layer 104 has a thickness in the range of 3 μm to 20 μm, the resistance of n ⁻ type silicon carbide epitaxial layer 104 can be reduced. It becomes possible to sufficiently suppress the generation of Joule heat due to the forward surge voltage or forward surge current in n ⁻ type silicon carbide epitaxial layer 104.

  According to the semiconductor device 1 according to the first embodiment, since the silicon layer (polysilicon layer 106) is made of polysilicon, it is possible to form the silicon layer by a relatively simple process, and thus a relatively simple process. Thus, a semiconductor device (a semiconductor device having a heterojunction) can be manufactured.

[Embodiment 2]
FIG. 4 is a cross-sectional view of the semiconductor device 2 according to the second embodiment.
The semiconductor device 2 according to the second embodiment basically has the same configuration as that of the semiconductor device 1 according to the first embodiment, but the structure of the silicon carbide semiconductor substrate used is different from that of the semiconductor device 1 according to the first embodiment. Different. That is, in semiconductor device 2 according to the second embodiment, as shown in FIG. 4, n ⁻ type silicon carbide epitaxial layer 104 is on n ⁺ type silicon carbide single crystal substrate 102 via n type low resistance silicon carbide layer 114. The silicon carbide semiconductor substrate 100a formed in the above is used. N-type low-resistance silicon carbide layer 114 contains an n-type impurity having a higher concentration than n ⁻ -type silicon carbide epitaxial layer 104 and a lower concentration than n ⁺ -type silicon carbide single crystal substrate 102. Silicon carbide semiconductor substrate 100a is formed by continuously epitaxially growing n-type low-resistance silicon carbide layer 114 and n ⁻ -type silicon carbide epitaxial layer 104 on n ⁺ -type silicon carbide single crystal substrate 102. Can do.

As described above, the semiconductor device 2 according to the second embodiment differs from the semiconductor device 1 according to the first embodiment in the structure of the silicon carbide semiconductor substrate used, but is similar to the semiconductor device 1 according to the first embodiment. , in the area surrounded by the p-type impurity region 108, the n ^- -type in the vicinity of the surface of the silicon carbide epitaxial layer 104, n ^- than -type silicon carbide epitaxial layer 104 containing low concentration n-type impurity of n ^- type Since the impurity region 112 is formed, as in the case of the semiconductor device 1 according to the first embodiment, the semiconductor device is capable of increasing the forward surge breakdown withstanding while maintaining a high reverse breakdown voltage.

Further, according to the semiconductor device 2 according to Embodiment 2, n ^- because its type the silicon carbide epitaxial layer 104 and the n-type low-resistance silicon carbide layer 114 can constitute a drift layer, n ^- -type silicon carbide Compared to the case where the drift layer is formed by the epitaxial layer 104 alone, the resistance of the drift layer can be lowered. For this reason, it becomes possible to suppress the generation of Joule heat due to the forward surge voltage or forward surge current in the drift layer. As a result, the forward surge breakdown resistance is further increased while maintaining a high reverse breakdown voltage. Is possible.

  The semiconductor device 2 according to the second embodiment has the same configuration as the semiconductor device 1 according to the first embodiment except for the structure of the silicon carbide semiconductor substrate to be used. It has a corresponding effect among the effects it has.

[Embodiment 3]
FIG. 5 is a cross-sectional view of the semiconductor device 3 according to the third embodiment.
The semiconductor device 3 according to the third embodiment basically has the same configuration as that of the semiconductor device 1 according to the first embodiment, but the structure of the silicon carbide semiconductor substrate used is the case of the semiconductor device 1 according to the first embodiment. Different. That is, in the semiconductor device 3 according to the third embodiment, as shown in FIG. 5, n ^- n on the rear surface of -type silicon carbide epitaxial layer 104 (n ⁺ -type surface of the silicon carbide single-crystal substrate 102 and the contact side) ^- An n-type low-resistance silicon carbide region containing n-type impurities at a concentration higher than that of n ⁻ -type silicon carbide epitaxial layer 104 and lower than that of n ⁺ -type silicon carbide single crystal substrate 102, in a region facing type impurity region 112. A silicon carbide semiconductor substrate 100b on which 116 is formed is used. Silicon carbide semiconductor substrate 100b is formed by selectively epitaxially growing n-type low-resistance silicon carbide region 116 and n ⁻ -type silicon carbide epitaxial layer 104 on n ⁺ -type silicon carbide single crystal substrate 102. Can do.

As described above, the semiconductor device 3 according to the third embodiment differs from the semiconductor device 1 according to the first embodiment in the structure of the silicon carbide semiconductor substrate used, but is similar to the semiconductor device 1 according to the first embodiment. , in the area surrounded by the p-type impurity region 108, the n ^- -type in the vicinity of the surface of the silicon carbide epitaxial layer 104, n ^- than -type silicon carbide epitaxial layer 104 containing low concentration n-type impurity of n ^- type Since the impurity region 112 is formed, as in the case of the semiconductor device 1 according to the first embodiment, the semiconductor device is capable of increasing the forward surge breakdown withstanding while maintaining a high reverse breakdown voltage.

Further, according to semiconductor device 3 according to the third embodiment, it is possible to form a drift layer with n ⁻ type silicon carbide epitaxial layer 104 and n type low resistance silicon carbide region 116, and therefore n ⁻ type silicon carbide. Compared to the case where the drift layer is formed by the epitaxial layer 104 alone, the resistance of the drift layer can be lowered. For this reason, it becomes possible to suppress the generation of Joule heat due to the forward surge voltage or forward surge current in the drift layer. As a result, the forward surge breakdown resistance is further increased while maintaining a high reverse breakdown voltage. Is possible.

  The semiconductor device 3 according to the third embodiment has the same configuration as the semiconductor device 1 according to the first embodiment except for the structure of the silicon carbide semiconductor substrate to be used. It has a corresponding effect among the effects it has.

[Embodiment 4]
FIG. 6 is a view for explaining the semiconductor device 4 according to the fourth embodiment. 6A is a plan view of the semiconductor device 4, and FIG. 6B is a cross-sectional view taken along line AA in FIG. 6A.
The semiconductor device 4 according to the fourth embodiment basically has the same configuration as that of the semiconductor device 1 according to the first embodiment, but the semiconductor according to the first embodiment is that a large number of polysilicon layers are formed on a chip. This is different from the case of the apparatus 1. That is, in the semiconductor device 4 according to the fourth embodiment, as shown in FIG. 6, a large number (nine in FIG. 6) of polysilicon layers 106 are formed on the chip. The p-type impurity region 108 is formed in a lattice shape on the surface of the n ⁻ -type silicon carbide epitaxial layer 104 in accordance with the arrangement of the polysilicon layer 106 (see FIG. 6A).

As described above, the semiconductor device 4 according to the fourth embodiment is different from the semiconductor device 1 according to the first embodiment in that a large number of polysilicon layers are formed on a chip. as in the case of 1, in the area surrounded by the p-type impurity regions 108, n ^- -type in the vicinity of the surface of the silicon carbide epitaxial layer 104, n ^- than -type silicon carbide epitaxial layer 104 of low concentration n-type impurity Since the contained n ⁻⁻ type impurity region 112 is formed, the forward surge breakdown withstand capability can be increased while maintaining a high reverse breakdown voltage, as in the case of the semiconductor device 1 according to the first embodiment. It becomes a semiconductor device.

  The semiconductor device 4 according to the fourth embodiment has the same configuration as that of the semiconductor device 1 according to the first embodiment except for the point that a large number of polysilicon layers are formed on the chip. Among the effects of the semiconductor device 1 according to the above, the corresponding effect is obtained.

  As mentioned above, although the semiconductor device of this invention was demonstrated based on said each embodiment, this invention is not limited to said each embodiment, It implements in a various aspect in the range which does not deviate from the summary. For example, the following modifications are possible.

(1) In each of the above-described embodiments, the depth of the deepest portion in the n ⁻⁻ type impurity region 112 is made deeper than the depth of the p-type impurity region 108, but the present invention is limited to this. is not. FIG. 7 is a cross-sectional view of the semiconductor device 5 according to the first modification. FIG. 8 is a cross-sectional view of the semiconductor device 6 according to the second modification. As shown in FIG. 7, n ^- to a depth of the deepest portion in the impurity regions 112a may be formed at the same depth as the depth of the p-type impurity regions 108, as shown in FIG. 8, n ^- The depth of the deepest portion in the ⁻ type impurity region 112 b may be formed shallower than the depth of the p type impurity region 108.

(2) In each of the above embodiments, the n ⁻⁻ type impurity region 112 is formed over the entire region surrounded by the p type impurity region 108, but the present invention is not limited to this. FIG. 9 is a cross-sectional view of a semiconductor device 7 according to Modification 3. As shown in FIG. 9, an n ⁻⁻ type impurity region 112 c may be formed in a part of the region surrounded by the p type impurity region 108.

(3) In each embodiment described above, p-type impurity region 108 is formed on the surface of n ⁻ -type silicon carbide epitaxial layer 104, but the present invention is not limited to this. FIG. 10 is a cross-sectional view of a semiconductor device 8 according to Modification 4. As shown in FIG. 10, p-type impurity region 108 a may be formed near the surface of n ⁻ -type silicon carbide epitaxial layer 104 (a position slightly lower than the actual surface). Further, n ^- type and a region, in which p-type impurity region 108 is formed on the surface of the silicon carbide epitaxial layer 104, n ^- region p-type impurity region 108 in the vicinity of the surface of the -type silicon carbide epitaxial layer 104 is formed and May be mixed.

(4) In each of the embodiments described above, the p-type impurity region 108 surrounds the entire periphery of the n ⁻⁻ type impurity region 112 (in other words, the entire end portion of the polysilicon layer 106 is seen in plan view). Although it was formed in the shape of a ring or a lattice on the surface of n ⁻ type silicon carbide epitaxial layer 104, the present invention is not limited to this. FIG. 11 is a plan view of the semiconductor device 9 according to the fifth modification. FIG. 12 is a plan view of the semiconductor device 10 according to the sixth modification. In FIGS. 11 and 12, the planar shape of the n ⁻⁻ type impurity regions 112d and 112e is indicated by a broken line. As shown in FIG. 11 and FIG. 12, the p-type impurity regions 108b, 108b, so that a part of the ring is interrupted (in other words, a part of the end of the polysilicon layer 106 is included when seen in a plan view). 108c may be formed. In this case, n ^- -type ⁿ are formed on the surface of the silicon carbide epitaxial layer 104 ^- -type impurity regions 112d, 112e, as shown in FIGS. 11 and 12, p-type impurity regions 108b, surrounded by 108c It may be formed so as to extend to a portion outside the region. That is, n ⁻⁻ type impurity regions 112d and 112e may be formed in all or part of the region surrounded by at least p type impurity regions 108b and 108c on the surface of n ⁻ type silicon carbide epitaxial layer 104.

(5) In each of the embodiments described above, n ⁻ -type impurity region 112 is not formed on the surface of n ⁻ -type silicon carbide epitaxial layer 104, but the present invention is not limited to this. For example, there may be a portion where n ⁻⁻ type impurity region 112 is formed on the surface of n ⁻ type silicon carbide epitaxial layer 104.

(6) In each of the embodiments described above, the polysilicon layer 106 into which n-type impurities are introduced is used as the silicon layer, but the present invention is not limited to this. As the silicon layer, a polysilicon layer into which a p-type impurity is introduced or a non-doped polysilicon layer can also be used. Further, a single crystal silicon layer can be used instead of the polysilicon layer.

(7) In each of the above embodiments, the silicon carbide semiconductor device having the heterojunction of the present invention has been described in which the first conductivity type is n-type and the second conductivity type is p-type. However, the present invention is not limited to this. Is not to be done. For example, the first conductivity type may be p-type and the second conductivity type may be n-type.

(8) In each of the above embodiments, the n ⁺ type silicon carbide single crystal substrate having a crystal polymorph of 4H is used, but the present invention is not limited to this. For example, an n ⁺ type silicon carbide single crystal substrate having a crystal polymorphism of 6H or 3C can be used.

(9) In each of the above embodiments, the semiconductor device of the present invention has been described by taking a diode as an example, but the present invention is not limited to this. For example, the present invention can be applied to an IGBT that injects minority carriers from a heterojunction.

1 is a diagram for explaining a semiconductor device 1 according to a first embodiment. 6 is a view for explaining the method for manufacturing the semiconductor device 1 according to the first embodiment. FIG. 6 is a view for explaining the method for manufacturing the semiconductor device 1 according to the first embodiment. FIG. FIG. 6 is a cross-sectional view of a semiconductor device 2 according to a second embodiment. FIG. 6 is a cross-sectional view of a semiconductor device 3 according to a third embodiment. FIG. 6 is a diagram for explaining a semiconductor device 4 according to a fourth embodiment. 7 is a cross-sectional view of a semiconductor device 5 according to Modification 1. FIG. 10 is a cross-sectional view of a semiconductor device 6 according to Modification 2. FIG. 11 is a cross-sectional view of a semiconductor device 7 according to Modification 3. FIG. 10 is a cross-sectional view of a semiconductor device 8 according to Modification 4. FIG. 10 is a plan view of a semiconductor device 9 according to Modification 5. FIG. 10 is a plan view of a semiconductor device 10 according to Modification 6. FIG. It is a figure shown in order to demonstrate the conventional semiconductor device 901.

Explanation of symbols

1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 901 ... semiconductor device, 100, 100a, 100b, 900 ... silicon carbide semiconductor substrate, 102, 902 ... n ⁺ type silicon carbide single crystal substrate 104,904 ... n ^- type silicon carbide epitaxial layer, 104a ... n ^- type region, 106,906 ... polysilicon layer, 107,111 ... predetermined part (of n ^- type silicon carbide epitaxial layer), 108,108a, 108b , 108c, 908 ... p-type impurity region, 110, 910 ... back electrode, 112, 112a, 112b, 112c, 112d, 112e ... n ^- type impurity region, 114 ... n-type low resistance silicon carbide layer, 116 ... n-type Low resistance silicon carbide region, M1, M2 ... mask, M3, M4 ... graphite mask

Claims (8)

A first conductivity type first silicon carbide layer;
A first conductivity type second silicon carbide layer formed on the first silicon carbide layer and containing a first conductivity type impurity at a lower concentration than the first silicon carbide layer;
A silicon layer formed on a part of the surface of the second silicon carbide layer and forming a heterojunction at an interface with the second silicon carbide layer;
A back electrode formed on the back surface of the first silicon carbide layer,
On the surface of the second silicon carbide layer or in the vicinity of the surface, a second conductivity type impurity region is formed in an annular shape so as to include all or a part of the end portion of the silicon layer in plan view,
In all or part of the region surrounded by the front Stories second conductivity type impurity region, wherein the vicinity of the surface except the surface of the second silicon carbide layer, the second first conductivity type low concentration than the silicon carbide layer A semiconductor device, wherein a first conductivity type impurity region containing an impurity is formed. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the first conductivity type impurity region is formed so that a depth of the shallowest portion is shallower than a depth of the deepest portion of the second conductivity type impurity region. The semiconductor device according to claim 1 or 2,
The thickness of the said 2nd silicon carbide layer exists in the range of 3 micrometers-20 micrometers, The semiconductor device characterized by the above-mentioned. The semiconductor device according to claim 1,
The second silicon carbide layer is interposed via a first conductivity type low resistance silicon carbide layer containing a first conductivity type impurity having a higher concentration than the second silicon carbide layer and a lower concentration than the first silicon carbide layer. The semiconductor device is formed on the first silicon carbide layer. The semiconductor device according to claim 1,
The first silicon carbide layer is higher in concentration than the second silicon carbide layer in a region facing the first conductivity type impurity region on the surface of the second silicon carbide layer on the side in contact with the first silicon carbide layer. A semiconductor device characterized in that a first conductivity type low-resistance silicon carbide region containing a first conductivity type impurity at a lower concentration is formed. In the semiconductor device according to claim 1,
The semiconductor device, wherein the silicon layer is made of polysilicon. The semiconductor device according to claim 6.
A semiconductor device, wherein the silicon layer is doped with an impurity of a first conductivity type or a second conductivity type.   The semiconductor device according to claim 1,
  A number of the silicon layers are formed on a surface of the second silicon carbide layer;
  The semiconductor device, wherein the second conductivity type impurity region is formed in a lattice shape on the surface of the second silicon carbide layer in accordance with the arrangement of the silicon layer.

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