JP5276355B2 - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which makes the reverse surge breakdown strength higher than before without spoiling the static characteristics. <P>SOLUTION: The semiconductor device includes an n<SP>-</SP>-type silicon carbide epitaxial layer 104, and a barrier metal layer 106, wherein a p-type impurity region 108 is formed on the surface of the n<SP>-</SP>-type silicon carbide epitaxial layer 104 to include the end of the barrier metal layer 106 on the plan view, a p<SP>++</SP>-type impurity region 110 is formed on the surface of the p-type impurity region 108 to include a part of the barrier metal layer 106 on the plan view, and an n-type impurity region 112 containing n-type impurities of higher concentration than the n<SP>-</SP>-type silicon carbide epitaxial layer 104 is formed beneath the p-type impurity region 108 in contact with the p-type impurity region 108 in a partial region of the p<SP>++</SP>-type impurity region 110 on the plan view. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a Schottky junction.

  A semiconductor device using silicon carbide as a semiconductor material has excellent characteristics such as high breakdown voltage, low loss, low leakage current, high temperature operation, and high speed operation. Conventionally, a semiconductor device having a Schottky junction is known as such a semiconductor device (see, for example, Patent Document 1). FIG. 11 is a diagram for explaining a conventional semiconductor device 901. FIG. 11A is a plan view of the semiconductor device 901, and FIG. 11B is a cross-sectional view taken along line AA in FIG.

Conventional semiconductor device 901, as shown in FIG. 11, n ^- silicon carbide semiconductor substrate 900 having a -type silicon carbide epitaxial layer 904, n ^- is formed on a part of the surface of the -type silicon carbide epitaxial layer 904, n ^- and a barrier metal layer 906 forming the interface Schottky junction with the -type silicon carbide epitaxial layer 904, n ^- the surface of the -type silicon carbide epitaxial layer 904, the end portion of the barrier metal layer 906 in a plan view A p-type impurity region 908 is formed so as to include, and a p ^++- type impurity region 910 is formed on the surface of the p-type impurity region 908 so as to include a part of the barrier metal layer 906 when seen in a plan view. N ⁻ type silicon carbide epitaxial layer 904 is formed on n ⁺ type silicon carbide single crystal substrate 902 containing n-type impurities at a higher concentration than n ⁻ type silicon carbide epitaxial layer 904. Further, a back electrode 920 is formed on the back surface of n ⁺ type silicon carbide single crystal substrate 902.

Therefore, according to the conventional semiconductor device 901, the p-type impurity region 908 is depleted at the time of reverse bias, and the electric field at the end of the p ⁺⁺ type impurity region 910 can be relaxed to obtain a high breakdown voltage.

Japanese Patent Laying-Open No. 2003-101039 (FIG. 10)

  By the way, since such a semiconductor device is normally used for an application that requires a high breakdown voltage, in such a semiconductor device, it is required to make the reverse surge breakdown withstand higher than before. Of course, it goes without saying that even in such a case, the static characteristics of the semiconductor device must not be impaired.

  Therefore, the present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor device capable of increasing the reverse surge breakdown resistance compared with the conventional one without impairing the static characteristics. .

  The semiconductor device of the present invention includes a first conductivity type silicon carbide layer and a barrier metal layer formed on a part of the surface of the silicon carbide layer and forming a Schottky junction at an interface with the silicon carbide layer. A first second conductivity type impurity region is formed on the surface of the silicon carbide layer or in the vicinity of the surface so as to include all or a part of the end portion of the barrier metal layer in plan view, The second conductivity region having a higher concentration than the first second conductivity type impurity region so as to include a part of the barrier metal layer in plan view on the surface of the first second conductivity type impurity region or in the vicinity of the surface. A second second conductivity type impurity region containing a conductivity type impurity is formed, and the first second conductivity type impurity in a partial region of the second second conductivity type impurity region in plan view. Below the region, the front is in contact with the first second conductivity type impurity region. Wherein the first-conductive type impurity region containing a high concentration first conductivity type impurity than silicon carbide layer is formed.

By the way, in the conventional semiconductor device 901, most of the reverse surge current flows through the end portion of the p ⁺⁺ type impurity region 910 (corresponding to the second second conductivity type impurity region of the present invention), so that it is a narrow region. When a large amount of heat is generated, the temperature easily rises. As a result, it is not easy to increase the reverse surge breakdown resistance.
On the other hand, according to the semiconductor device of the present invention, the first second conductivity type impurity region is located below the first second conductivity type impurity region in a partial region of the second second conductivity type impurity region when seen in a plan view. Since the first conductivity type impurity region containing the first conductivity type impurity having a higher concentration than the silicon carbide layer is formed so as to be in contact with the first second conductivity type impurity region, the first conductivity type at the time of reverse bias is formed. The electric field strength in the vicinity of the type impurity region is increased, and the reverse surge current is induced to flow in the first conductivity type impurity region. As a result, the area through which the reverse surge current flows can be made wider than before, so that the temperature is less likely to rise than before, and as a result, the reverse surge breakdown resistance can be increased.

  In addition, according to the semiconductor device of the present invention, since the drift layer can be configured by the silicon carbide layer and the first conductivity type impurity region, compared with the case where the drift layer is configured by the silicon carbide layer alone. The resistance of the drift layer can be lowered. For this reason, since it becomes possible to suppress the generation of Joule heat due to the reverse surge current in the drift layer, this also makes it possible to increase the reverse surge breakdown resistance.

  In addition, according to the semiconductor device of the present invention, the Schottky junction portion that determines the static characteristics of the semiconductor device has the same structure as that of the conventional semiconductor device, so that the static characteristics are not impaired.

  Therefore, the semiconductor device of the present invention is a semiconductor device capable of increasing the reverse surge breakdown resistance compared to the conventional one without impairing the static characteristics.

  Further, according to the semiconductor device of the present invention, since the first conductivity type impurity region is formed, the electric field strength in the vicinity of the first conductivity type impurity region at the time of off becomes high, and the reverse recovery time trr can be shortened. The effect that it becomes possible is also acquired.

  In the semiconductor device of the present invention, it is preferable that the first conductivity type impurity region is formed in a region excluding an end portion of the second second conductivity type impurity region.

  By adopting such a configuration, the reverse surge current is reliably induced to flow in the first conductivity type impurity region, so that the reverse surge breakdown resistance can be increased.

  In the semiconductor device of the present invention, an end portion of the barrier metal layer may be positioned on the first conductivity type impurity region, or a second second conductivity type outside the first conductivity type impurity region. It may be located on the impurity region, or may be located on the first second conductivity type impurity region outside the second second conductivity type impurity region.

  With such a configuration, the reverse surge current is surely induced and flows in the first conductivity type impurity region, so that the reverse surge breakdown resistance can be increased.

  In the semiconductor device of the present invention, it is preferable that the width of the first conductivity type impurity region is wider than the width of the region in the second second conductivity type impurity region that does not overlap with the first conductivity type impurity region.

  With such a configuration, the reverse surge breakdown resistance can be further increased by further increasing the area through which the reverse surge current flows.

  In the semiconductor device of the present invention, the silicon carbide layer is located on a surface opposite to the surface on which the barrier metal layer is formed, and contains a first conductivity type impurity having a higher concentration than the silicon carbide layer. A second silicon carbide layer of one conductivity type may be further provided, or a back electrode formed on the back surface of the second silicon carbide layer may be further provided.

  Hereinafter, a semiconductor device of the present invention will be described based on an embodiment shown in the drawings.

[Embodiment 1]
1. Configuration of Semiconductor Device 1 According to First Embodiment FIG. 1 is a diagram for explaining the semiconductor device 1 according to the first embodiment. FIG. 1A is a plan view of the semiconductor device 1, and FIG. 1B is a cross-sectional view taken along the line AA in FIG.

As shown in FIG. 1, semiconductor device 1 according to Embodiment 1 includes silicon carbide semiconductor substrate 100 having n ⁻ -type silicon carbide epitaxial layer (silicon carbide layer) 104, as in the case of conventional semiconductor device 901, n ^- it is formed on a part of the surface of the -type silicon carbide epitaxial layer 104, n ^- and a barrier metal layer 106 to form an interface Schottky junction between the -type silicon carbide epitaxial layer 104, n ^- -type silicon carbide epitaxial A semiconductor device (Schottky barrier diode) in which a p-type impurity region (first second conductivity type impurity region) 108 is formed on the surface of the layer 104 so as to include the end portion of the barrier metal layer 106 in plan view. It is.

N ⁻ type silicon carbide epitaxial layer 104 is formed on n ⁺ type silicon carbide single crystal substrate (second silicon carbide layer) 102 containing n-type impurities at a higher concentration than n ⁻ type silicon carbide epitaxial layer 104. Yes. Further, on the surface of the p-type impurity region 108, a p-type impurity (second conductivity type impurity) having a concentration higher than that of the p-type impurity region 108 is included so as to include a part of the barrier metal layer 108 in plan view. A p ⁺⁺ type impurity region (second second conductivity type impurity region) 110 to be contained is formed. In addition, in a part of the p ⁺⁺ type impurity region 110 in a plan view, below the p type impurity region 108 and in contact with the p type impurity region 108 than the n ⁻ type silicon carbide epitaxial layer 104. An n-type impurity region (first conductivity type impurity region) 112 containing a high concentration n-type impurity is formed. A back electrode 120 is formed on the back surface of n ⁺ -type silicon carbide single crystal substrate 102.

As the n ⁺ -type silicon carbide single crystal substrate 102, a substrate having an n-type impurity concentration of, for example, about 5 × 10 ¹⁷ cm ^{−3 to} 5 × 10 ¹⁹ cm ⁻³ and a thickness of, for example, about 30 μm to 400 μm can be used. . Further, as the crystal polymorph of the n ⁺ -type silicon carbide single crystal substrate 102, for example, 4H can be used.

As n ⁻ type silicon carbide epitaxial layer 104, an n type impurity concentration of about 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ and a thickness of about ³ μm to 20 μm can be used, for example.

As barrier metal layer 106, a barrier metal layer made of a metal (eg, titanium) that forms a Schottky junction with n ⁻ type silicon carbide epitaxial layer 104 can be used. The barrier metal layer 106 may be used as an anode electrode as it is, or a metal film (for example, a laminated film or a nickel film in which titanium and aluminum are laminated) that can be ohmic-connected to the barrier metal layer 106 may be used as an anode electrode. Good.

  As the back electrode 120, for example, an electrode made of a laminated film in which titanium, nickel, and silver are laminated can be used. The back electrode 120 serves as a cathode electrode.

The p-type impurity region 108 has a depth of about 0.2 μm to 1.0 μm, for example, and a p-type impurity concentration of about 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ , for example. P type impurity region 108 is formed in a ring shape on the surface of n ⁻ type silicon carbide epitaxial layer 104 (see FIG. 1A).

The p ⁺⁺ type impurity region 110 has a depth of, for example, about 0.1 μm to 0.5 μm, and a p type impurity concentration of, for example, about 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ .

The bottom surface of the n-type impurity region 112 is about 0.1 to 0.5 μm deeper than the bottom surface of the p-type impurity region 108. The n-type impurity region 112 has an n-type impurity concentration of, for example, about 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ .

2. Method for Manufacturing Semiconductor Device 1 According to Embodiment 1 FIGS. 2 and 3 are views for explaining a method for manufacturing the semiconductor device 1 according to Embodiment 1. FIG. 2 (a) to 2 (c) and FIGS. 3 (a) to 3 (d) are process diagrams.

  As shown in FIGS. 2 and 3, the semiconductor device 1 according to the first embodiment can be manufactured by performing the following steps (S1) to (S7).

(S1) the semiconductor substrate preparation step n ⁺ -type silicon carbide single-crystal substrate 102 (thickness: 400 [mu] m, the impurity ^{concentration: 1 × 10 19 cm -3)} n on the upper surface of the ^- type silicon carbide epitaxial layer 104 (thickness: 10 [mu] m, A silicon carbide semiconductor substrate 100 having an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ ) is prepared (see FIG. 2A).

(S2) First p-type impurity introduction step First, the surface of silicon carbide semiconductor substrate 100 is cleaned. Thereafter, a mask M1 having an opening in a portion corresponding to p type impurity region 108 is formed on the surface of silicon carbide semiconductor substrate 100. Thereafter, a relatively small amount of boron ions as a p-type impurity is implanted into a predetermined portion 107 of the n ⁻ -type silicon carbide epitaxial layer 104 through the mask M1 (see FIG. 2B). In the first p-type impurity introduction step, boron ions may be implanted under conditions where a thin silicon oxide film or the like is present in the opening of the mask M1.

(S3) Second p-type impurity introduction step First, the mask M1 is removed. Thereafter, a mask M2 having an opening at a portion corresponding to p ⁺⁺ type impurity region 110 is formed on the surface of silicon carbide semiconductor substrate 100. Thereafter, boron ions as a p-type impurity are introduced into the predetermined portion 109 of the n ⁻ -type silicon carbide epitaxial layer 104 through the mask M2 at a lower energy amount than in the first p-type impurity introduction step and the first p-type. A larger amount is implanted than in the impurity introduction step (see FIG. 2C). In the second p-type impurity introduction step, boron ions may be implanted under conditions where a thin silicon oxide film or the like exists in the opening of the mask M2.

(S4) n-type impurity introduction step First, the mask M2 is removed. Thereafter, a mask M3 having an opening in a portion corresponding to n-type impurity region 112 is formed on the surface of silicon carbide semiconductor substrate 100. Thereafter, phosphorus ions as n-type impurities are implanted with a relatively high energy amount into a predetermined portion 111 of the n ⁻ -type silicon carbide epitaxial layer 104 through the mask M3 (see FIG. 3A). In the n-type impurity introduction step, phosphorus ions may be implanted under conditions where a thin silicon oxide film or the like is present in the opening of the mask M3.

(S5) Impurity activation step First, the mask M3 is removed. Thereafter, after forming a protective resist layer (not shown) on the front and back surfaces of the silicon carbide semiconductor substrate 100, the protective resist layer is carbonized to form graphite masks M4 and M5 (see FIG. 3B). ). Thereafter, p-type impurity and n-type impurity are activated by heating silicon carbide semiconductor substrate 100 to a temperature of 1600 ° C. or higher, and p-type impurity region 108 (depth: 0.5 μm, surface p-type impurity concentration: 1.0 × 10 ¹⁷ cm ⁻³ ), p ^{+ +} type impurity region 110 (depth: 0.2 μm, surface p-type impurity concentration: 1.0 × 10 ¹⁹ cm ⁻³ ) and n-type impurity region 112 (bottom surface). Depth: 0.7 μm, n-type impurity concentration: 1.0 × 10 ¹⁸ cm ⁻³ ) is formed (see FIG. 3B).

(S6) Barrier metal layer forming step First, the graphite masks M4 and M5 are removed. Thereafter, a barrier metal layer 106 made of titanium is formed on a part of the surface of silicon carbide semiconductor substrate 100 (see FIG. 3C).

(S7) Back Electrode Formation Step A back electrode 120 made of a laminated film in which titanium, nickel, and silver are laminated on the back surface of the silicon carbide semiconductor substrate 100 is formed (see FIG. 3D).

  By performing the above steps, the semiconductor device 1 according to the first embodiment can be manufactured.

3. Effect of Semiconductor Device 1 According to First Embodiment FIG. 4 is a diagram for explaining the effect of the semiconductor device 1 according to the first embodiment. FIG. 4A is a diagram schematically showing a current path of a reverse surge current in the semiconductor device 1 according to the first embodiment, and FIG. 4B is a semiconductor device 901 according to the comparative example 1 (conventional semiconductor device). It is a figure which shows typically the electric current path | route of the reverse direction surge current in 901.).

According to the semiconductor device 1 according to the first embodiment, a part of the p ⁺⁺ type impurity region 110 in a plan view has a part below the p type impurity region 108 in contact with the p type impurity region 108 in plan view. Since n-type impurity region 112 containing n-type impurity having a higher concentration than n ⁻ -type silicon carbide epitaxial layer 104 is formed, as shown in FIG. The electric field strength is increased, and the reverse surge current is induced to flow in the n-type impurity region 112. As a result, the area through which the reverse surge current flows can be made wider than before, so that the temperature is less likely to rise than before, and as a result, the reverse surge breakdown resistance can be increased.

Further, according to the semiconductor device 1 according to the embodiment 1, n ^- since it is possible to configure the drift layer in the -type silicon carbide epitaxial layer 104 and the n-type impurity regions 112, n ^- -type silicon carbide epitaxial layer alone As compared with the case where the drift layer is formed, the resistance of the drift layer can be lowered. For this reason, since it becomes possible to suppress the generation of Joule heat due to the reverse surge current in the drift layer, this also makes it possible to increase the reverse surge breakdown resistance.

  In addition, according to the semiconductor device 1 according to the first embodiment, the portion of the Schottky junction that determines the static characteristics of the semiconductor device has the same structure as that of the conventional semiconductor device 901, so that the static characteristics are not impaired.

  Therefore, the semiconductor device 1 according to the first embodiment is a semiconductor device that can increase the reverse surge breakdown resistance compared to the conventional one without impairing the static characteristics.

  Further, according to the semiconductor device 1 according to the first embodiment, since the n-type impurity region 112 is formed, the electric field strength in the vicinity of the n-type impurity region 112 at the time of OFF is increased, and the reverse recovery time trr is shortened. Is possible.

Further, according to the semiconductor device 1 according to the first embodiment, since the n-type impurity region 112 is formed in a region excluding the end portion of the p ⁺⁺ type impurity region 110, the reverse surge current is generated in the n-type impurity region. 112 is reliably guided to flow. As a result, the effects of the present invention can be obtained with certainty.

Further, in the semiconductor device 1 according to the first embodiment, since the end portion of the barrier metal layer 106 is located on the n-type impurity region 112, the reverse surge current is passed through the p ⁺⁺ type impurity region 110. The n-type impurity region 112 is reliably guided to flow. As a result, the effects of the present invention can be obtained with certainty.

In the semiconductor device 1 according to the first embodiment, the width of the n-type impurity region 112 (the width of the region excluding the end of the p ^++- type impurity region 110) is the same as that in the p ^++- type impurity region 110 in plan view. Since the width of the region not overlapping with the n-type impurity region 112 is wider, the reverse surge breakdown resistance can be further increased by further increasing the area through which the reverse surge current flows.

[Embodiment 2]
FIG. 5 is a partial cross-sectional view of the semiconductor device 2 according to the second embodiment.
The semiconductor device 2 according to the second embodiment basically has the same configuration as that of the semiconductor device 1 according to the first embodiment, but the position of the end of the barrier metal layer 106 is the case of the semiconductor device 1 according to the first embodiment. Is different. That is, in the semiconductor device 2 according to the second embodiment, as shown in FIG. 5, the position of the end of the barrier metal layer 106 is located on the p ⁺⁺ type impurity region 110 outside the n type impurity region 112.

As described above, the semiconductor device 2 according to the second embodiment is different from the semiconductor device 1 according to the first embodiment in the position of the end of the barrier metal layer 106, but the semiconductor device 2 according to the first embodiment. Similarly, the n ⁻ -type silicon carbide epitaxial layer 104 is in contact with the p-type impurity region 108 below the p-type impurity region 108 in a partial region of the p ⁺⁺ -type impurity region 110 when seen in a plan view. Since the n-type impurity region 112 containing high-concentration n-type impurities is formed, the semiconductor device can have a higher reverse surge breakdown resistance than before without impairing the static characteristics.

  The semiconductor device 2 according to the second embodiment has the same configuration as that of the semiconductor device 1 according to the first embodiment except for the position of the end of the barrier metal layer 106, and thus the semiconductor device according to the first embodiment. 1 has the corresponding effect.

[Embodiment 3]
FIG. 6 is a partial cross-sectional view of the semiconductor device 3 according to the third embodiment.
The semiconductor device 3 according to the third embodiment basically has the same configuration as that of the semiconductor device 1 according to the first embodiment, but the end portion of the barrier metal layer 106 is located in the semiconductor device 1 according to the first embodiment. Is different. In other words, in the semiconductor device 3 according to the third embodiment, as shown in FIG. 6, the end portion of the barrier metal layer 106 is located on the p-type impurity region 108 outside the p ^++- type impurity region 110.

As described above, the semiconductor device 3 according to the third embodiment differs from the semiconductor device 1 according to the first embodiment in the position of the end of the barrier metal layer 106, but is different from the case of the semiconductor device 1 according to the first embodiment. Similarly, the n ⁻ -type silicon carbide epitaxial layer 104 is in contact with the p-type impurity region 108 below the p-type impurity region 108 in a partial region of the p ⁺⁺ -type impurity region 110 when seen in a plan view. Since the n-type impurity region 112 containing high-concentration n-type impurities is formed, the semiconductor device can have a higher reverse surge breakdown resistance than before without impairing the static characteristics.

  The semiconductor device 3 according to the third embodiment has the same configuration as that of the semiconductor device 1 according to the first embodiment except for the position of the end portion of the barrier metal layer 106, and thus the semiconductor device according to the first embodiment. 1 has the corresponding effect.

  Although the semiconductor device of the present invention has been described based on the above embodiment, the present invention is not limited to the above embodiment, and can be implemented in various modes without departing from the gist thereof. For example, the following modifications are possible.

(1) In each of the embodiments described above, the n-type impurity region 112 is formed below the p ^++- type impurity region 110 in the semiconductor substrate in which the p ^++- type impurity region 110 is formed on the surface of the p-type impurity region 108. Although the semiconductor device of the present invention has been described by taking the manufactured semiconductor device as an example, the present invention is not limited to this. FIG. 7 is a partial cross-sectional view of the semiconductor device 4 according to the first modification. FIG. 8 is a partial cross-sectional view of the semiconductor device 5 according to the second modification. As shown in FIGS. 7 and 8, ^{p ++} -type impurity regions 114 and spaced apart from the ^{p ++} -type impurity regions 110 on the outside of the ^{p ++} type impurity region 110 in plan view at the surface of the p-type impurity region 108 is further In the formed semiconductor substrate, a semiconductor device in which an n-type impurity region 112 is formed below the p ^++- type impurity region 110 may be used, or when viewed in plan on the surface of the n ⁻ -type silicon carbide epitaxial layer 104. A semiconductor in which an n-type impurity region 112 is formed below the p ^++- type impurity region 110 in a semiconductor substrate in which a p-type impurity region 116 is further formed outside the p-type impurity region 108 and separated from the p-type impurity region 108. It may be a device.

(2) In each of the embodiments described above, the semiconductor device of the present invention is exemplified by the case where the n-type impurity introduction step is performed after the first p-type impurity introduction step and the second p-type impurity introduction step. However, the present invention is not limited to this. 9 and 10 are views for explaining the method of manufacturing the semiconductor device according to the third modification. FIG. 9A to FIG. 9C and FIG. 10A to FIG. 10D are process diagrams. As shown in FIGS. 9 and 10, the n-type impurity introduction step may be performed prior to the first p-type impurity introduction step and the second p-type impurity introduction step.

(3) In each of the embodiments described above, the semiconductor device of the present invention has been described by taking the semiconductor device in which the p-type impurity region 108 is formed on the surface of the n ⁻ -type silicon carbide epitaxial layer 104 as an example. It is not limited to. For example, the present invention can be applied to a semiconductor device in which a p-type impurity region is formed near the surface of an n ⁻ -type silicon carbide epitaxial layer.

(4) In each of the above-described embodiments, the semiconductor device of the present invention has been described by taking the semiconductor device in which the p ⁺⁺ type impurity region 110 is formed on the surface of the p-type impurity region 108 as an example. However, the present invention is not limited to this. Is not to be done. For example, the present invention can also be applied to a semiconductor device in which a p ⁺⁺ type impurity region is formed near the surface of the p type impurity region.

(5) In each of the above embodiments, the semiconductor device of the present invention has been described with the first conductivity type as n-type and the second conductivity type as p-type. However, the present invention is not limited to this. For example, the first conductivity type may be p-type and the second conductivity type may be n-type.

(6) In each of the above embodiments, an n ⁺ type silicon carbide single crystal substrate having a crystal polymorph of 4H is used, but the present invention is not limited to this. For example, an n ⁺ type silicon carbide single crystal substrate having a crystal polymorphism of 6H or 3C can be used.

1 is a diagram for explaining a semiconductor device 1 according to a first embodiment. 6 is a view for explaining the method for manufacturing the semiconductor device 1 according to the first embodiment. FIG. 6 is a view for explaining the method for manufacturing the semiconductor device 1 according to the first embodiment. FIG. FIG. 6 is a diagram for explaining the effect of the semiconductor device 1 according to the first embodiment. FIG. 6 is a partial cross-sectional view of a semiconductor device 2 according to a second embodiment. FIG. 6 is a partial cross-sectional view of a semiconductor device 3 according to a third embodiment. 7 is a partial cross-sectional view of a semiconductor device 4 according to Modification 1. FIG. 11 is a partial cross-sectional view of a semiconductor device 5 according to Modification 2. FIG. 10 is a view for explaining a method for manufacturing a semiconductor device according to Modification 3. FIG. 10 is a view for explaining a method for manufacturing a semiconductor device according to Modification 3. FIG. It is a figure shown in order to demonstrate the conventional semiconductor device 901.

Explanation of symbols

1, 2, 3, 4, 5, 901 ... semiconductor device, 100, 900 ... silicon carbide semiconductor substrate, 102, 902 ... n ⁺ type silicon carbide single crystal substrate, 104, 904 ... n ^- type silicon carbide epitaxial layer, 106 , 906 ... barrier metal layer, 107, 109, 111 ... (n ^- type silicon carbide epitaxial layer) predetermined site, 108,116,908 ... p-type impurity region, 110,114,910 ... ^{p ++} type impurity regions, 112 ... n-type impurity region, 120, 920 ... back electrode, M1, M2, M3 ... mask, M4, M5 ... graphite mask

Claims (10)

A silicon carbide layer of a first conductivity type;
A barrier metal layer formed on a part of the surface of the silicon carbide layer and forming a Schottky junction at an interface with the silicon carbide layer;
On the surface of the silicon carbide layer or in the vicinity of the surface, a first second conductivity type impurity region is formed so as to include all or a part of the end portion of the barrier metal layer in plan view,
A part of the barrier metal layer is included in the surface of the first second conductivity type impurity region in the first second conductivity type impurity region or in the vicinity of the surface inside the first second conductivity type impurity region in plan view. As described above, a second second conductivity type impurity region containing a second conductivity type impurity having a concentration higher than that of the first second conductivity type impurity region is formed.
A portion of the second second conductivity type impurity region in a plan view is in contact with the first second conductivity type impurity region below the first second conductivity type impurity region. And a semiconductor device in which a first conductivity type impurity region containing a first conductivity type impurity having a higher concentration than the silicon carbide layer is formed ,
A depth of the first second conductivity type impurity region is 0.2 to 1.0 μm;
A depth of the second second conductivity type impurity region is 0.1 to 0.5 μm;
The semiconductor device according to claim 1, wherein the first conductivity type impurity region is formed to a depth exceeding the bottom surface of the first second conductivity type impurity region by 0.1 to 0.5 μm.   The semiconductor device according to claim 1,
  The first second conductivity type impurity region, the second second conductivity type impurity region, and the first conductivity type impurity region are “regions corresponding to the first second conductivity type impurity region by an ion implantation method”. First conductivity type impurity introduction step for introducing a second conductivity type impurity into the first step "," a second conductivity type impurity is introduced into a region corresponding to the second second conductivity type impurity region by ion implantation. 2 ”second conductivity type impurity introduction step” and “first conductivity type impurity introduction step of introducing a first conductivity type impurity into a region corresponding to the first conductivity type impurity region by ion implantation”. A semiconductor device characterized by that.   The semiconductor device according to claim 1 or 2,
  A thickness of the silicon carbide layer is 3 to 20 μm. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the first conductivity type impurity region is formed in a region excluding an end portion of the second second conductivity type impurity region. The semiconductor device according to claim 1,
An end of the barrier metal layer is located on the first conductivity type impurity region. The semiconductor device according to claim 1,
An end portion of the barrier metal layer is located on a second second conductivity type impurity region outside the first conductivity type impurity region. The semiconductor device according to claim 1,
An end portion of the barrier metal layer is located on the first second conductivity type impurity region outside the second second conductivity type impurity region. The semiconductor device according to claim 1,
The width of the first conductivity type impurity region is wider than the width of a region of the second second conductivity type impurity region that does not overlap with the first conductivity type impurity region. The semiconductor device according to claim 1,
Located on the surface of the silicon carbide layer opposite to the surface on which the barrier metal layer is formed,
A semiconductor device, further comprising: a first conductivity type second silicon carbide layer containing a first conductivity type impurity at a higher concentration than the silicon carbide layer. The semiconductor device according to claim 9 .
The semiconductor device further comprising a back electrode formed on the back surface of the second silicon carbide layer.

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