JP5439873B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a high breakdown voltage semiconductor device having an electric field relaxation region around a heterojunction.

  Conventionally, as this type of technology, for example, those described in the following documents are known (see Patent Document 1). In this document, a heterojunction is formed on a first main surface of a silicon carbide semiconductor substrate by a silicon carbide semiconductor of the substrate and a hetero semiconductor region made of a semiconductor material having a different band gap from the silicon carbide. An invention of a semiconductor device is described in which an electric field relaxation region made of silicon carbide is formed at the terminal portion of the semiconductor substrate, an anode electrode is formed so as to be in contact with the hetero semiconductor region, and a cathode electrode is formed on the second main surface of the silicon carbide semiconductor substrate. Has been.

JP 2003-318413 A

  In the semiconductor device described in the above-mentioned document, when a high voltage is applied to the cathode electrode, a specific part of the electric field relaxation region is easily broken.

  Accordingly, the present invention has been made in view of the above, and an object of the present invention is to prevent a breakdown of an electric field relaxation region when a high voltage is applied in a semiconductor device having an electric field relaxation region around a heterojunction. To provide an apparatus.

  In order to achieve the above object, the means for solving the problems of the present invention is that when an electric field relaxation region that receives an electric field from a plane orientation side whose dielectric breakdown field strength is lower than other plane orientations receives the electric field, The resistance value of the hetero semiconductor region located in the current flow path of the current flowing in the relaxation region is larger than the resistance value of other hetero semiconductor regions.

  According to the present invention, the current flowing to the electric field relaxation region that receives the electric field from the plane orientation side whose dielectric breakdown strength is lower than that of other plane orientations is limited by the hetero semiconductor region having higher resistance than the others. It is possible to prevent dielectric breakdown at a specific location in the region.

It is sectional drawing which shows the relationship between the crystal axis in a silicon carbide semiconductor substrate, and a dielectric breakdown strength. It is sectional drawing which shows the mode of the electric field which the electric field relaxation area | region formed in the silicon carbide semiconductor substrate receives. It is a top view which shows the structure of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 1 of this invention. It is a top view which shows the structure of the semiconductor device which concerns on Example 2 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Example 2 of this invention. It is a top view which shows the structure of the semiconductor device which concerns on Example 3 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Example 3 of this invention. It is a top view which shows the structure of the semiconductor device which concerns on Example 4 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Example 4 of this invention.

  Embodiments for carrying out the present invention will be described below with reference to the drawings.

  First, before describing the embodiments of the present invention, characteristic technical ideas adopted by the present invention will be described in order from the background.

  For example, hexagonal silicon carbide, which is one of the semiconductors forming the heterojunction of the semiconductor device of the present invention, has anisotropy in breakdown field strength, and the direction of the <0001> axis of the crystal axis ( The so-called breakdown field strength in the plane direction is c-plane and the breakdown field strength in the horizontal direction (so-called plane direction is a-plane) with respect to the <0001> axis are greatly different. It is known that it is lower than the dielectric breakdown electric field in the c-plane direction. Further, as shown in FIG. 1, a silicon carbide semiconductor substrate 200 generally used in the technical field of a semiconductor device has a <0001> axis of a crystal axis inclined several degrees with respect to the horizontal direction of the substrate. That is, various elements are formed with an offset angle.

  When the conventional semiconductor device described in the background section above is formed on such a silicon carbide semiconductor substrate 200 and a high voltage is applied to the cathode electrode, as shown in FIG. The electric field (electric field lines) 202 concentrates on the part. Therefore, among the electric field 202 applied to the electric field relaxation region 201, a part of the electric field 202 is applied in parallel to the above-described a-plane with a low dielectric breakdown electric field, as shown in the circle of FIG. The Thereby, in the electric field relaxation region 201 having a region receiving an electric field from the a-plane side where the dielectric breakdown electric field is low, dielectric breakdown is likely to occur at a lower voltage than other regions. As a result, the avalanche breakdown current is concentrated at a specific location in the electric field relaxation region 201, and the specific location where the current is concentrated leads to destruction.

  Accordingly, a semiconductor device of the present invention includes a semiconductor substrate, a hetero semiconductor region that is stacked on the main surface of the semiconductor substrate to form a heterojunction with the semiconductor substrate, and an electric field relaxation region formed in the semiconductor substrate at the periphery of the heterojunction. When the first electric field relaxation region that receives the electric field from the plane orientation side in the electric field relaxation region where the dielectric breakdown field strength is lower than the other plane orientations receives the electric field, The resistance value of the first hetero semiconductor region located in the current flow path of the current flowing in the electric field relaxation region is larger than the resistance value of the other hetero semiconductor region.

  The first electric field relaxation region has a current flowing when receiving an electric field from a direction perpendicular to a direction in which a crystal axis of a semiconductor constituting the semiconductor substrate is inclined with respect to a horizontal plane of the semiconductor substrate. Less than the current flowing in the electric field relaxation region.

  By adopting such a characteristic technical idea, when a high voltage is applied to the cathode electrode, even if the avalanche breakdown current is concentrated at a specific portion of the electric field relaxation region, that is, at a location where the dielectric breakdown electric field is low, It is possible to reduce the current flowing in the electric field relaxation region formed at the position where the electric field is received from the plane orientation (a-plane) side where the dielectric breakdown electric field is low, and the electric field relaxation region can be prevented from being broken. An embodiment realizing the technical idea of the present invention will be described below.

  3 is a plan view showing the configuration of the semiconductor device according to the first embodiment of the present invention. FIG. 4A is a cross-sectional view taken along the line AA in FIG. 3, and FIG. 3 is a sectional view taken along line BB in FIG. The semiconductor device of Example 1 shown in FIGS. 3 and 4 functions as a heterojunction type diode formed in silicon carbide semiconductor substrate 100. Silicon carbide semiconductor substrate 100 is carbonized of single-crystal polytype 4H—SiC whose principal surface normal line is inclined by about 8 ° in the <11_20> direction with respect to the <0001> axis of the crystal axis (having an offset angle). A silicon semiconductor substrate 1 and a silicon carbide epitaxial layer 2 deposited on the first main surface side of the silicon carbide semiconductor substrate 1 by a chemical vapor deposition method or the like.

  On the first main surface of silicon carbide semiconductor substrate 100, hetero semiconductor region 3 made of, for example, polycrystalline silicon of a semiconductor material having a band gap different from that of single crystal 4H—SiC is formed. A junction is formed. As shown in FIG. 3, an electric field relaxation region 4 made of P-type silicon carbide is formed on the first main surface of silicon carbide epitaxial layer 2 so as to terminate the end of the heterojunction. An anode electrode 5 is formed on the hetero semiconductor region 3 so as to be in contact with the hetero semiconductor region 3, and a cathode electrode 6 is formed on the silicon carbide semiconductor substrate 1 so as to be in contact with the silicon carbide semiconductor substrate 1.

As shown in FIG. 4A, the hetero semiconductor region 3 includes a P ⁺ type polycrystalline silicon layer 7 having a high P type impurity concentration and a P type impurity concentration compared to the impurity concentration of the polycrystalline silicon layer 7. And a low P ⁻ type polycrystalline silicon layer 8 (8A, 8B). That is, along the electric field relaxation regions 4A and 4B which are arranged and formed in the current flow path of the current flowing between the anode electrode 5 and the electric field relaxation regions 4A and 4B and arranged on opposite sides across the anode electrode 5. The opposite peripheral portions of the hetero semiconductor region 3 are constituted by P ⁻ type polycrystalline silicon layers 8A and 8B having a low impurity concentration, and the other hetero semiconductor regions 3 of the peripheral portion are P ⁺ type having a high impurity concentration. The polycrystalline silicon layer 7 is formed.

  Thus, as shown in FIG. 4A, the peripheral edge of the hetero semiconductor region 3 in the junction region where the electric field relaxation regions 4A and 4B and the hetero semiconductor region 3 are stacked, the anode electrode 5 and the hetero semiconductor region As shown in FIG. 4 (b), the impurity concentration of the hetero semiconductor region 3 located between the peripheral region of the anode electrode 5 in the junction region where the layer 3 is laminated and the electric field relaxation regions 4C and 4D are heterogeneous. It is set lower than the impurity concentration of the hetero semiconductor region 3 between the peripheral edge of the hetero semiconductor region 3 in the junction region where the semiconductor region 3 is laminated and the closest anode electrode 5.

As shown in FIG. 3, the P ⁻ -type polycrystalline silicon layer 8 having a low impurity concentration is disposed between a predetermined opposed electric field relaxation region 4 and the anode electrode 5. Further, the tangent of the outer peripheral portion of the predetermined opposed electric field relaxation region 4 in contact with the P ⁻ type polycrystalline silicon layer 8 having a low impurity concentration is at least perpendicular to the <11_20> direction and the <0001> axis The direction is perpendicular to the inclination direction.

  That is, the electric field relaxation regions 4A and 4B arranged and formed in the region of the plane orientation in which the dielectric breakdown electric field strength of the silicon carbide semiconductor substrate 100 is lower than other plane orientations, that is, <0001 of the crystal axis of the silicon carbide semiconductor substrate 100 The impurity concentration of the peripheral edge region of the hetero semiconductor region 3 positioned in parallel with the electric field relaxation regions 4A and 4B arranged in the <11_20> direction, which is the direction in which the axis is inclined, is arranged and formed in another region. It is set lower than the impurity concentration of the hetero semiconductor region 3.

  By setting the concentration in this manner, the hetero semiconductor region 3 between the anode electrode 5 and at least a part of the region where the electric field relaxation regions 4A and 4B and the hetero semiconductor region 3 shown in FIG. The resistance is based on the resistance of the hetero semiconductor region 3 between at least a part of the region where the electric field relaxation regions 4C and 4D and the hetero semiconductor region 3 shown in FIG. Get higher.

  As a result, the resistance of the hetero semiconductor region 3 between at least a part of the region where the electric field relaxation regions 4A and 4B that are liable to break down at the time of avalanche breakdown and the hetero semiconductor region 3 are in contact with the anode electrode 5 is described. Is higher than the resistance of the hetero semiconductor region 3 between at least a part of the region where the electric field relaxation regions 4C and 4D where the breakdown hardly occurs and the hetero semiconductor region 3 are in contact with the closest anode electrode 5 .

  Next, the operation of this semiconductor device will be described.

  For example, when the cathode electrode 6 is grounded and a positive potential is applied to the anode electrode 5, a conduction characteristic corresponding to the forward characteristic of the diode can be obtained.

On the other hand, when the anode electrode 5 is grounded and a high voltage is applied to the cathode electrode 6, as shown in FIG. 4A, the resistance value is high between the anode electrode 5 and the electric field relaxation regions 4A and 4B. Since the P ⁻ type polycrystalline silicon layer 8 (low impurity concentration) is arranged and formed, voltage distribution due to the resistance component occurs, and the voltage applied to the electric field relaxation regions 4A and 4B is as shown in FIG. The voltage applied to the electric field relaxation regions 4C and 4D shown in FIG. That is, at the time of avalanche breakdown in the reverse characteristics of the diode, the breakdown current flowing through the electric field relaxation regions 4A and 4B is smaller than the breakdown current flowing through the electric field relaxation regions 4C and 4D. As a result, it is possible to prevent the specific portion of the current relaxation region from being destroyed at the time of avalanche breakdown that has occurred in the prior art, and a high avalanche resistance can be realized.

  Next, a method for manufacturing the semiconductor device will be described with reference to FIGS. 5A to 5C (FIGS. 5-A, 5-B, and 5-C) showing manufacturing steps. 5, (a1) to (a3) are cross-sectional views along the line AA in FIG. 3, and (b1) to (b3) are along the line BB in FIG. FIG.

  In FIG. 5, first, a silicon carbide semiconductor substrate 100 in which a silicon carbide epitaxial layer 2 is deposited on a first main surface of a silicon carbide semiconductor substrate 1 made of single crystal 4H—SiC is prepared, and a predetermined region of the silicon carbide epitaxial layer 2 is prepared. The electric field relaxation region 4 (4A, 4B, 4C, 4D) is formed in a ring shape (FIGS. 5-A (a1), (b1)). Electric field relaxation region 4 may use either P-type silicon carbide or silicon carbide having a high resistance (very low impurity concentration).

Subsequently, after depositing a P ⁻ type polycrystalline silicon layer 8 to be the hetero semiconductor region 3 on the first main surface of the silicon carbide epitaxial layer 2, using a photoresist or the like as a mask material, a P ⁻ type polycrystalline silicon layer is formed. For example, boron of a P-type impurity is selectively ion-implanted into the silicon layer 8 to form a P ⁺ -type polycrystalline silicon layer 7, and regions having different impurity concentrations are selectively formed inside the hetero semiconductor region 3. (FIG. 5-B (a2), (b2)). Thereby, the hetero semiconductor region 3 having different resistance can be easily formed.

  Finally, the hetero semiconductor region 3 is selectively removed by etching, the anode electrode 5 is formed so as to contact the hetero semiconductor region 3, and the cathode electrode 6 is formed so as to contact the silicon carbide semiconductor substrate 1. 3. The semiconductor device of Example 1 shown in FIG. 4 is completed (FIGS. 5-C (a3) and (b3)).

  Thus, by locally changing the impurity concentration of the hetero semiconductor region 3, that is, by selectively adjusting the impurity concentration of the hetero semiconductor region 3, the resistance of the hetero semiconductor region is locally changed and the electric field is changed. Since the amount of current flowing through the relaxation region is controlled, the current amount can be reduced by locally reducing the thickness of the electric field relaxation region or lowering the impurity concentration in the silicon carbide epitaxial layer around the electric field relaxation region where breakdown is likely to occur. Compared to the method of controlling the above, it can be carried out easily and can be realized at a low manufacturing cost.

  6 is a plan view showing a configuration of a semiconductor device according to Embodiment 2 of the present invention. FIG. 7A is a cross-sectional view taken along the line AA in FIG. 6, and FIG. 6 is a sectional view taken along line BB in FIG. A feature of the semiconductor device of the second embodiment shown in FIGS. 6 and 7 is that the previous embodiment is used as means for limiting the current in the electric field relaxation region 4 formed at a position where dielectric breakdown is more likely to occur than others. In place of the method of selectively adjusting the impurity concentration of the hetero semiconductor region 3 employed in 1, the hetero semiconductor region 3 in the region where the impurity concentration is lowered in the first embodiment is formed thinner than other regions, As a result, a method of setting the resistance higher than that in the other regions is adopted, and the others are the same as in the first embodiment.

  The semiconductor device of Example 2 shown in FIGS. 6 and 7 is a heterojunction type diode formed in silicon carbide semiconductor substrate 100. Silicon carbide semiconductor substrate 100 is carbonized of single-crystal polytype 4H—SiC whose principal surface normal line is inclined by about 8 ° in the <11_20> direction with respect to the <0001> axis of the crystal axis (having an offset angle). A silicon semiconductor substrate 1 and a silicon carbide epitaxial layer 2 deposited on the first main surface side of the silicon carbide semiconductor substrate 1 by a chemical vapor deposition method or the like.

On the first main surface of silicon carbide semiconductor substrate 100, hetero semiconductor region 3 made of, for example, a P ⁺ -type polycrystalline silicon layer 7 of a semiconductor material having a band gap different from that of single crystal 4H—SiC is formed. A heterojunction is formed with 100. On the first main surface of silicon carbide epitaxial layer 2, an electric field relaxation region 4 made of P-type silicon carbide is formed in a ring shape so as to terminate the end of the heterojunction as shown in FIG. An anode electrode 5 is formed on the hetero semiconductor region 3 so as to be in contact with the hetero semiconductor region 3, and a cathode electrode 6 is formed on the silicon carbide semiconductor substrate 1 so as to be in contact with the silicon carbide semiconductor substrate 1.

  Along the electric field relaxation regions 4A and 4B, which are arranged and formed in the current flow path of the current flowing between the anode electrode 5 and the electric field relaxation regions 4A and 4B, and arranged on opposite sides across the anode electrode 5. The opposing peripheral edge portions of the hetero semiconductor region 3 arranged and formed in are formed thinner than the other peripheral edge portions.

  Thus, as shown in FIG. 7A, the peripheral edge of the hetero semiconductor region 3 in the junction region where the electric field relaxation regions 4A and 4B and the hetero semiconductor region 3 are stacked, the anode electrode 5 and the hetero semiconductor region As shown in FIG. 7 (b), the thickness of the hetero semiconductor region 3 located between the peripheral region of the anode electrode 5 in the junction region where 3 is laminated and the electric field relaxation regions 4C and 4D is heterogeneous. The hetero semiconductor region 3 is formed thinner than the thickness of the hetero semiconductor region 3 between the peripheral edge of the hetero semiconductor region 3 in the junction region where the semiconductor region 3 is stacked and the closest anode electrode 5.

Further, as shown in FIG. 6, the hetero semiconductor region 3 having a small thickness is disposed between a predetermined opposed electric field relaxation region 4 and the anode electrode 5. Furthermore, the tangent of the outer peripheral portion of the predetermined electric field relaxation region 4 that is in contact with the thin hetero semiconductor region 3 (P ⁺ -type polycrystalline silicon layer 7) is perpendicular to at least the <11_20> direction. And the direction perpendicular to the inclination direction of the <0001> axis.

  That is, electric field relaxation regions 4A and 4B arranged in a region having a plane orientation where the dielectric breakdown strength of silicon carbide semiconductor substrate 100 is lower than other plane orientations, that is, <0001> of the crystal axis of silicon carbide semiconductor substrate 100 The thickness of the peripheral edge region of the hetero semiconductor region 3 located in parallel with the electric field relaxation regions 4A and 4B arranged and formed in the <11_20> direction, which is the direction in which the axis is inclined, is arranged and formed in another region. It is formed thinner than the thickness of the semiconductor region 3.

  With such a shape, the resistance of the hetero semiconductor region 3 between at least a part of the region where the electric field relaxation regions 4A and 4B and the hetero semiconductor region 3 shown in FIG. The resistance of the hetero semiconductor region 3 between at least a part of the region where the electric field relaxation regions 4C and 4D and the hetero semiconductor region 3 shown in FIG. 7B are in contact with the closest anode electrode 5 is higher. .

  As a result, the resistance of the hetero semiconductor region 3 between at least a part of the region where the electric field relaxation regions 4A and 4B that are liable to break down at the time of avalanche breakdown and the hetero semiconductor region 3 are in contact with the anode electrode 5 is described. Is higher than the resistance of the hetero semiconductor region 3 between at least a part of the region where the electric field relaxation regions 4C and 4D where the breakdown hardly occurs and the hetero semiconductor region 3 are in contact with the closest anode electrode 5.

  Therefore, in the second embodiment, as in the first embodiment described above, the breakdown current flowing through the electric field relaxation regions 4A and 4B is the breakdown current flowing through the electric field relaxation regions 4C and 4D during the avalanche breakdown in the reverse characteristics of the diode. Less than. As a result, it is possible to prevent the specific portion of the current relaxation region from being destroyed at the time of avalanche breakdown that has occurred in the prior art, and a high avalanche resistance can be realized.

  In the second embodiment, since the hetero semiconductor region 3 can be formed using polycrystalline silicon having a single impurity concentration as compared with the first embodiment, the height of the heterojunction barrier is constant. Thus, leakage current can be reduced.

  FIG. 8 is a plan view showing a configuration of a semiconductor device according to Example 3 of the present invention, FIG. 9A is a cross-sectional view taken along the line AA in FIG. 8, and FIG. FIG. 8 is a sectional view taken along line BB in FIG. The semiconductor device of the third embodiment shown in FIGS. 8 and 9 is characterized in that the previous embodiment is used as a means for limiting the current in the electric field relaxation region 4 formed at a position where dielectric breakdown is more likely to occur. 1 instead of the method of selectively adjusting the impurity concentration of the hetero semiconductor region 3 adopted in 1 above, the width direction (plane orientation <11_20> direction of the hetero semiconductor region 3 in the region where the impurity concentration is lowered in the first embodiment The length in the direction perpendicular to the other region is formed longer than that in the other regions, thereby adopting a method of setting the resistance higher than that in the other regions. It is the same.

  The semiconductor device of Example 2 shown in FIGS. 8 and 9 is a heterojunction type diode formed in silicon carbide semiconductor substrate 100. Silicon carbide semiconductor substrate 100 is carbonized of single-crystal polytype 4H—SiC whose principal surface normal line is inclined by about 8 ° in the <11_20> direction with respect to the <0001> axis of the crystal axis (having an offset angle). A silicon semiconductor substrate 1 and a silicon carbide epitaxial layer 2 deposited on the first main surface side of the silicon carbide semiconductor substrate 1 by a chemical vapor deposition method or the like.

On the first main surface of silicon carbide semiconductor substrate 100, hetero semiconductor region 3 made of, for example, a P ⁺ -type polycrystalline silicon layer 7 of a semiconductor material having a band gap different from that of single crystal 4H—SiC is formed. A heterojunction is formed with 100. On the first main surface of silicon carbide epitaxial layer 2, an electric field relaxation region 4 made of P-type silicon carbide is formed in a ring shape so as to terminate the end of the heterojunction as shown in FIG. An anode electrode 5 is formed on the hetero semiconductor region 3 so as to be in contact with the hetero semiconductor region 3, and a cathode electrode 6 is formed on the silicon carbide semiconductor substrate 1 so as to be in contact with the silicon carbide semiconductor substrate 1.

  Further, as shown in FIG. 9A, the peripheral edge of the hetero semiconductor region 3 in the junction region where the electric field relaxation regions 4A and 4B and the hetero semiconductor region 3 are stacked, the anode electrode 5 and the hetero semiconductor region 3 Of the hetero semiconductor region 3 located between the peripheral edge of the anode electrode 5 in the junction region where the electrodes are stacked (current flow path in the hetero semiconductor region 3 of the current flowing from the anode electrode 5 to the electric field relaxation regions 4A and 4B) 9 (b), as shown in FIG. 9 (b), from the peripheral edge of the hetero semiconductor region 3 in the junction region where the electric field relaxation regions 4C and 4D and the hetero semiconductor region 3 are stacked, From the distance (L2) of the hetero semiconductor region 3 in the adjacent anode electrode 5 (current flow path in the hetero semiconductor region 3 of the current flowing from the anode electrode 5 to the electric field relaxation regions 4C and 4D). It has been formed long.

In addition, as shown in FIG. 8, the wide hetero semiconductor region 3 is disposed between a predetermined opposed electric field relaxation region 4 and the anode electrode 5. Further, the wide hetero semiconductor region 3 (
The tangent of the outer peripheral portion of the predetermined opposed electric field relaxation region 4 in contact with the P ⁺ -type polycrystalline silicon layer 7) is at least perpendicular to the <11_20> direction and in the tilt direction of the <0001> axis On the other hand, it is perpendicular.

  That is, electric field relaxation regions 4A and 4B arranged in a region having a plane orientation where the dielectric breakdown strength of silicon carbide semiconductor substrate 100 is lower than other plane orientations, that is, <0001> of the crystal axis of silicon carbide semiconductor substrate 100 A hetero semiconductor in which the width of the peripheral end region of the hetero semiconductor region 3 located in parallel with the electric field relaxation regions 4A and 4B arranged in the <11_20> direction, which is the direction in which the axis is inclined, is arranged in another region. It is formed wider than the width of the region 3.

  With such a shape, the resistance of the hetero semiconductor region 3 between at least a part of the region where the electric field relaxation regions 4A and 4B and the hetero semiconductor region 3 shown in FIG. The resistance of the hetero semiconductor region 3 between at least a part of the region where the electric field relaxation regions 4C and 4D and the hetero semiconductor region 3 shown in FIG. 9B are in contact with the closest anode electrode 5 is higher. .

  As a result, the resistance of the hetero semiconductor region 3 between at least a part of the region where the electric field relaxation regions 4A and 4B that are liable to break down at the time of avalanche breakdown and the hetero semiconductor region 3 are in contact with the anode electrode 5 is described. Is higher than the resistance of the hetero semiconductor region 3 between at least a part of the region where the electric field relaxation regions 4C and 4D where the breakdown hardly occurs and the hetero semiconductor region 3 are in contact with the closest anode electrode 5.

  Therefore, in the third embodiment, as in the first embodiment described above, the breakdown current flowing through the electric field relaxation regions 4A and 4B is the breakdown current flowing through the electric field relaxation regions 4C and 4D during the avalanche breakdown in the reverse characteristics of the diode. Less than. As a result, it is possible to prevent the specific portion of the current relaxation region from being destroyed at the time of avalanche breakdown that has occurred in the prior art, and a high avalanche resistance can be realized.

  In addition, since the third embodiment has a structure that can be implemented only by changing the shape of the anode electrode 5 as compared with the prior art described above, it is possible to reduce the cost and increase the avalanche without adding a process to the prior art. A tolerant semiconductor device can be realized.

  10 is a plan view showing a configuration of a semiconductor device according to Example 4 of the present invention, FIG. 11A is a cross-sectional view taken along the line AA of FIG. 10, and FIG. FIG. 10 is a cross-sectional view taken along line BB of FIG. A feature of the semiconductor device of the fourth embodiment shown in FIGS. 10 and 11 is that the technical idea of the present invention described above is realized by a semiconductor device having the functions of both a transistor and a diode. As a means for limiting the electric current in the electric field relaxation region 4 formed at a position where it is more likely to occur than the others, the method of selectively adjusting the impurity concentration of the hetero semiconductor region 3 employed in the previous embodiment 1 and the previous implementation To adopt both methods of forming the length of the hetero semiconductor region 3 employed in Example 3 in the width direction (direction perpendicular to the direction of the plane orientation <11_20>) longer than other regions. is there.

  The semiconductor device of the fourth embodiment shown in FIGS. 10 and 11 has both functions of a transistor and a diode having a heterojunction type formed on the silicon carbide semiconductor substrate 100. Silicon carbide semiconductor substrate 100 is carbonized of single-crystal polytype 4H—SiC whose principal surface normal line is inclined by about 8 ° in the <11_20> direction with respect to the <0001> axis of the crystal axis (having an offset angle). A silicon semiconductor substrate 1 and a silicon carbide epitaxial layer 2 deposited on the first main surface side of the silicon carbide semiconductor substrate 1 by a chemical vapor deposition method or the like.

  On the first main surface of silicon carbide semiconductor substrate 100, hetero semiconductor region 3 made of, for example, polycrystalline silicon of a semiconductor material having a band gap different from that of single crystal 4H—SiC is formed. A junction is formed. On the first main surface of silicon carbide epitaxial layer 2, an electric field relaxation region 4 made of P-type silicon carbide is formed in a ring shape so as to terminate the end of the heterojunction as shown in FIG. An anode electrode 5 is formed on the hetero semiconductor region 3 so as to be in contact with the hetero semiconductor region 3, and a cathode electrode 6 is formed on the silicon carbide semiconductor substrate 1 so as to be in contact with the silicon carbide semiconductor substrate 1.

As shown in FIG. 11A, the hetero semiconductor region 3 includes an N ⁺ -type polycrystalline silicon layer 9 having a high N-type impurity concentration and an N-type impurity concentration compared to the impurity concentration of the polycrystalline silicon layer 9. And a low N ⁻ type polycrystalline silicon layer 10 (10A, 10B). That is, along the electric field relaxation regions 4A and 4B which are arranged and formed in the current flow path of the current flowing between the anode electrode 5 and the electric field relaxation regions 4A and 4B and arranged on opposite sides across the anode electrode 5. The opposite peripheral portions of the hetero semiconductor region 3 are composed of N ⁻ type polycrystalline silicon layers 10A and 10B having a low impurity concentration, and the other hetero semiconductor regions 3 of the peripheral portion are N ⁺ type having a high impurity concentration. The polycrystalline silicon layer 9 is used.

  Thus, as shown in FIG. 11A, the peripheral edge of the hetero semiconductor region 3 in the junction region where the electric field relaxation regions 4A and 4B and the hetero semiconductor region 3 are stacked, the anode electrode 5 and the hetero semiconductor region As shown in FIG. 11 (b), the impurity concentration of the hetero semiconductor region 3 located between the peripheral region of the anode electrode 5 in the junction region where 3 is laminated and the heterogeneous regions 4C and 4D are heterogeneous. It is set lower than the impurity concentration of the hetero semiconductor region 3 between the peripheral edge of the hetero semiconductor region 3 in the junction region where the semiconductor region 3 is laminated and the closest anode electrode 5.

As shown in FIG. 10, the N ⁻ -type polycrystalline silicon layer 9 having a low impurity concentration is disposed between a predetermined opposing electric field relaxation region 4 and the anode electrode 5. Further, the tangent of the outer peripheral portion of the predetermined opposed electric field relaxation region 4 in contact with the N ⁻ type polycrystalline silicon layer 9 having a low impurity concentration is at least perpendicular to the <11_20> direction and <0001> The direction is perpendicular to the direction of inclination of the shaft.

  That is, electric field relaxation regions 4A and 4B arranged in a region having a plane orientation where the dielectric breakdown strength of silicon carbide semiconductor substrate 100 is lower than other plane orientations, that is, <0001> of the crystal axis of silicon carbide semiconductor substrate 100 The impurity concentration of the peripheral region of the hetero semiconductor region 3 located in parallel with the electric field relaxation regions 4A and 4B arranged and formed in the <11_20> direction, which is the direction in which the axis is inclined, is arranged and formed in another region. The impurity concentration is set lower than that of the semiconductor region 3.

  By setting the concentration, the hetero semiconductor region 3 between the anode electrode 5 and at least a part of the region where the electric field relaxation regions 4A and 4B and the hetero semiconductor region 3 shown in FIG. The resistance is based on the resistance of the hetero semiconductor region 3 between at least a part of the region where the electric field relaxation regions 4C and 4D and the hetero semiconductor region 3 shown in FIG. Get higher.

  11A, the peripheral edge of the hetero semiconductor region 3 in the junction region where the electric field relaxation regions 4A and 4B and the hetero semiconductor region 3 are stacked, the anode electrode 5, and the hetero semiconductor region 3 As shown in FIG. 11 (b), the length of the hetero semiconductor region 3 located between the peripheral region of the anode electrode 5 in the junction region where the electrode layers are stacked is equal to the electric field relaxation regions 4C and 4D and the hetero semiconductor region. 3 is formed longer (wider) than the length of the hetero semiconductor region 3 from the peripheral edge of the hetero semiconductor region 3 to the nearest anode electrode 5 in the junction region where 3 is laminated.

Further, as shown in FIG. 10, the wide (long distance) hetero semiconductor region 3 is disposed between a predetermined opposed electric field relaxation region 4 and the anode electrode 5. Further, the tangent of the outer peripheral portion of the predetermined opposing electric field relaxation region 4 in contact with the wide (long distance) hetero semiconductor region 3 (N ⁻ type polycrystalline silicon layers 10A and 10B) is at least <11_20>. It is perpendicular to the direction and perpendicular to the direction of inclination of the <0001> axis.

  That is, electric field relaxation regions 4A and 4B arranged in a region having a plane orientation where the dielectric breakdown strength of silicon carbide semiconductor substrate 100 is lower than other plane orientations, that is, <0001> of the crystal axis of silicon carbide semiconductor substrate 100 A hetero semiconductor in which the width of the peripheral end region of the hetero semiconductor region 3 located in parallel with the electric field relaxation regions 4A and 4B arranged in the <11_20> direction, which is the direction in which the axis is inclined, is arranged in another region. It is formed wider than the width of the region 3.

  Due to such a shape, the resistance of the hetero semiconductor region 3 between at least a part of the region where the electric field relaxation regions 4A and 4B and the hetero semiconductor region 3 shown in FIG. The resistance of the hetero semiconductor region 3 between at least a part of the region where the electric field relaxation regions 4C and 4D and the hetero semiconductor region 3 are in contact with each other and the closest anode electrode 5 shown in FIG. .

  As a result, the resistance of the hetero semiconductor region 3 between at least a part of the region where the electric field relaxation regions 4A and 4B that are liable to break down at the time of avalanche breakdown and the hetero semiconductor region 3 are in contact with the anode electrode 5 is described. Is higher than the resistance of the hetero semiconductor region 3 between at least a part of the region where the electric field relaxation regions 4C and 4D where the breakdown hardly occurs and the hetero semiconductor region 3 are in contact with the closest anode electrode 5.

  A trench (groove) 11 is formed so as to penetrate through the hetero semiconductor region 3 and reach the silicon carbide epitaxial layer 2. A gate electrode 13 is formed inside the trench 11 adjacent to the heterojunction via the gate insulating film 12. Is formed. The gate electrode 13 is electrically insulated from the anode electrode 5 by the gate insulating film 12 and the interlayer insulating film 14. Further, the gate electrode 13 is electrically connected to the gate pad 15 as shown in FIG. 10, and a gate voltage is applied from the outside through the gate pad 15.

  Although not shown in FIG. 10, the trench 11, the gate insulating film 12 and the gate electrode 13 are arranged and formed in stripes in the vertical direction in FIG.

  Next, the operation of this semiconductor device will be described.

  First, when an appropriate voltage is applied to the cathode electrode 6 with the anode electrode 5 and the gate electrode 13 being grounded, the anode electrode 5 and the cathode electrode 6 are electrically cut off by a heterojunction energy barrier. It becomes a state. As a result, no current flows between the anode electrode 5 and the cathode electrode 6, and the device is turned off.

  On the other hand, when an appropriate predetermined voltage is applied to the gate electrode 13 in a state where the anode electrode 5 is grounded and an appropriate predetermined voltage is applied to the cathode electrode 6, it is applied to the hetero semiconductor region 3 via the gate insulating film 12. The height of the energy barrier of the heterojunction is changed by the gate electric field, and electrons are accumulated in the depletion region formed inside the hetero semiconductor region 3 to form an accumulation layer. Thereby, an electron flows from the anode electrode 5 to the cathode electrode 6 by the electric field from the cathode electrode 6, and it will be in an ON state. Thereafter, when the gate electrode 13 is grounded and the gate voltage applied to the gate electrode 13 is removed in a state where an appropriate predetermined voltage is applied to the cathode electrode 6, the cathode electrode 6 is turned off.

  By such an operation, the semiconductor device according to the fourth embodiment functions as an insulated gate drive type transistor in which the anode electrode 5 is used as a source electrode and the cathode electrode 6 is used as a drain electrode, and the switching control is performed by a gate voltage.

  Next, when the cathode electrode 6 and the gate electrode 13 are grounded and an appropriate voltage is applied to the anode electrode 5, the forward characteristics of the diode are obtained as in the semiconductor device described in the first to third embodiments. Corresponding conduction characteristics are obtained, and it functions as a unipolar freewheeling diode.

  Therefore, in the fourth embodiment, in the semiconductor device having the functions of both a transistor and a diode, the breakdown current flowing in the electric field relaxation regions 4A and 4B is applied to the electric field relaxation regions 4C and 4D at the time of avalanche breakdown in the reverse characteristics of the diode. Less than the flowing breakdown current. As a result, it is possible to prevent the specific portion of the current relaxation region from being destroyed at the time of avalanche breakdown that has occurred in the prior art, and a high avalanche resistance can be realized.

  In the first to fourth embodiments, the material constituting the semiconductor substrate is described using single crystal 4H—SiC. However, other materials such as gallium nitride may be used.

In addition, although polycrystalline silicon is used as the material for the hetero semiconductor region, single crystal silicon or amorphous silicon may be used, and the material is not limited to silicon material, and silicon germanium may be used.

DESCRIPTION OF SYMBOLS 1,200 ... Silicon carbide semiconductor substrate 2 ... Silicon carbide epitaxial layer 3 ... Hetero semiconductor region 4,201 ... Electric field relaxation region 4A ... Electric field relaxation region 4A, 4B, 4C, 4D ... Electric field relaxation region 5 ... Anode electrode 6 ... Cathode electrode 7, 8, 8A, 8B, 9, 10A, 10B ... polycrystalline silicon layer 11 ... trench 12 ... gate insulating film 13 ... gate electrode 14 ... interlayer insulating film 15 ... gate pad 100 ... silicon carbide semiconductor substrate

Claims (7)

A semiconductor substrate;
A hetero semiconductor region stacked on the main surface of the semiconductor substrate to form a heterojunction with the semiconductor substrate;
In a semiconductor device having an electric field relaxation region formed in the semiconductor substrate at the periphery of the heterojunction,
Among the electric field relaxation regions, when the first electric field relaxation region receiving an electric field from the plane orientation side where the dielectric breakdown electric field strength is lower than other plane orientations receives the electric field, the first electric field relaxation region flows into the first electric field relaxation region. A semiconductor device, wherein a resistance value of a first hetero semiconductor region located in a current flow path of current is larger than a resistance value of another hetero semiconductor region. Said first field when subjected to an electric field from the direction perpendicular to the first direction that has semiconductor crystal axis inclined to the electric field relaxation region constituting the semiconductor substrate with respect to a horizontal plane of said semiconductor body 2. The semiconductor device according to claim 1, wherein a current flowing through the relaxation region is smaller than a current flowing through the other electric field relaxation regions. The semiconductor device according to claim 1, wherein an impurity concentration of the first hetero semiconductor region is lower than an impurity concentration of other hetero semiconductor regions. 3. The semiconductor device according to claim 1, wherein a thickness of the first hetero semiconductor region is smaller than a thickness of the other hetero semiconductor region. The current path of the first hetero semiconductor region when a current flows to the first electric field relaxation region through the first hetero semiconductor region is longer than the current paths of the other hetero semiconductor regions. The semiconductor device according to claim 1 or 2. Having a gate electrode formed in the hetero semiconductor region;
Functions as a diode having the semiconductor substrate as a cathode and the hetero semiconductor region as an anode, and the semiconductor substrate as a drain, the hetero semiconductor region as a source, and switching control based on a gate voltage applied to the gate electrode 6. The semiconductor device according to claim 1, wherein the semiconductor device functions as a transistor to be operated. The semiconductor substrate is formed of silicon carbide or gallium nitride,
The semiconductor device according to claim 1, wherein the hetero semiconductor region is formed of any one of single crystal silicon, polycrystalline silicon, amorphous silicon, and silicon germanium.

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