JP5340912B2 - 電気的に強化されたワイヤボンドパッケージ - Google Patents

電気的に強化されたワイヤボンドパッケージ Download PDF

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JP5340912B2
JP5340912B2 JP2009501011A JP2009501011A JP5340912B2 JP 5340912 B2 JP5340912 B2 JP 5340912B2 JP 2009501011 A JP2009501011 A JP 2009501011A JP 2009501011 A JP2009501011 A JP 2009501011A JP 5340912 B2 JP5340912 B2 JP 5340912B2
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bond
finger
insulating material
pad
bond pad
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JP2009530842A (ja
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ワイランド クリス
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台灣積體電路製造股▲ふん▼有限公司
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Description

本発明は集積回路（ＩＣ）のパッケージングに関するものである。より詳細には、本発明は、半導体ダイとパッケージ基板間の選択された接続導体が絶縁材料で被覆される、ＩＣデバイスダイのワイヤボンディングに関するものである。
電子産業はより微小な領域により高機能なデバイスを実現する半導体技術の進歩に依存し続けている。多くの用途に対してより高機能なデバイスを実現するためには、一枚のシリコンウェハに多数の電子デバイスを集積する必要がある。シリコンウェハの単位領域当たりの電子デバイス数が増加するにつれて、製造プロセスはより困難になる。
多くの専門分野における様々な用途に対して、多岐に渡る半導体デバイスが製造されてきた。このようなシリコンベースの半導体デバイスは、多くの場合、ｐチャンネルＭＯＳ（ＰＭＯＳ）、ｎチャンネルＭＯＳ（ＮＭＯＳ）および相補型ＭＯＳ（ＣＭＯＳ）トランジスタのような金属酸化物半導体電界効果トランジスタ（ＭＯＳＦＥＴ）、バイポーラトランジスタ、及びＢｉＣＭＯＳトランジスタを含む。このようなＭＯＳＦＥＴデバイスは導電性ゲートとシリコン様基板との間に絶縁材料を含むため、これらのデバイスは一般にＩＧＦＥＴｓ（絶縁ゲートＦＥＴ）と呼ばれる。
これらの半導体デバイスは一般に半導体基板を具え、その上に多くの能動素子が形成されている。個々の能動素子の特定の構造はデバイスタイプ間で相違しうる。例えばＭＯＳトランジスタにおいては、能動素子は一般にソースおよびドレイン領域とソース／ドレイン間の電流を調整するゲート電極とを具える。
さらに例えばＣＭＯＳ、ＢｉＣＭＯＳ、バイポーラなどのように、多くのウェハ製造プロセスにおいて製造されるこれらのデバイスは、デジタルデバイスであってもアナログデバイスであっても良い。また基板はシリコン、ガリウムヒ素（ＧａＡｓ）あるいは微小電子回路を製造するのに適した他の基板でもよい。
製造プロセスを受けた後に、シリコンウェハは規定数のデバイスを有する。これらのデバイスはテストされ、正常なデバイスが収集されてパッケージングされる。
複雑なＩＣデバイスのパッケージングはデバイスの最終的な性能にますます影響を与えている。多くのパッケージは基板を具え、この基板上の、パッドランドで囲まれた規定のダイ設置領域にデバイスダイが装着される。デバイスダイ自身がボンディングパッドを有し、ダイ設置領域を囲むそれぞれのパッドランドからそれぞれのボンドパッドへと接続されたボンドワイヤを経て外部への接続を容易にしている。前記パッドランドは基板内に規定された電気導体を経て外部接点へ接続する。幾つかのパッケージタイプにおいては、組み立てられたデバイスは適切な成形材料内に封止することにより周囲の損傷から保護される。
デバイスが複雑さを増すにつれ、ワイヤボンドの数は数百に達する。継続する微細化に合わせてパッケージサイズを縮小し、かつ電子製品の機能強化を維持するために、設計はワイヤボンド間の間隔を縮小する傾向にある。これらの製品にはノート型パソコン、携帯情報端末（ＰＤＡｓ）、無線電話、自動車の電子制御モジュールなどが含まれる。
技術がもっと多くの性能をより小さなパッケージに詰め込むにつれ、封止プロセス中に隣接するボンドワイヤが屈曲して互いに接触する危険があり、こうしたワイヤの接触は電気的短絡につながる。ボンドワイヤの短絡を防止するために、米国特許第６，０４６，０７５号、名称「Oxide Wire Bond Insulation in Semiconductor Assemblies（半導体組み立てにおける酸化物によるワイヤボンド絶縁）」、が提案されており、その全内容がそっくりそのままここに援用される。
一実施例において、絶縁ボンディングワイヤが半導体集積回路パッケージに設けられている。隣接するボンドワイヤ間の短絡防止に役立つ電気的に絶縁されたボンドワイヤを提供するためにボンドワイヤには酸素プラズマ酸化物が形成される。
しかし、ボンドワイヤ上に形成された酸化物はやや脆い。このため封止中、形成材料の流入によるボンドワイヤの屈曲で絶縁材料の剥離を引き起こし、隣接するボンドワイヤが互いに接触して短絡する危険を引き起こしかねない。
ボンドワイヤを絶縁化する課題に取り組む必要があり、適用する絶縁化は封止の困難に耐え、ボンドワイヤに代わる別の接続導体を提供するものでなければならない。
本発明は、パッケージ封止中のボンドワイヤの運動が隣接するボンドワイヤ間の短絡へとつながる可能性があるボンドワイヤに絶縁体を設けるのが有益であることを確かめた。幾つかのデバイスダイ／パッケージ位置ではボンドワイヤの代わりに絶縁材料で囲まれた導電ストラップを使用することができる。他の場所では、一つあるいはそれ以上のボンドワイヤを弾性絶縁材料で被覆することができる。例えば信号ピンは絶縁材料で被覆されたボンドワイヤが適するが、デバイスの基準電圧接続には導電ストラップが適するものとし得る。
一実施例では、パッケージ内に電気的に絶縁された接続を有する集積回路（ＩＣ）デバイスが存在する。前記ＩＣデバイスは、ダイ設置領域に装着された、複数のボンディングパッドを有する半導体デバイスを具える。複数のボンドフィンガーを有するリードフレームがダイ設置領域を取り囲んでいる。複数の互いに孤立した接続導体のそれぞれの第１の端が前記半導体デバイス上の対応するボンディングパッドに接続され、前記複数の互いに孤立した接続導体のそれぞれ第２の端が前記リードフレームの対応するボンドフィンガーに接続されている。前記複数の互いに孤立した接続導体の少なくとも一部は絶縁材料で被膜されている。
他の実施例では、ＢＧＡパッケージ基板内に集積回路（ＩＣ）が存在し、前記ＢＧＡパッケージ基板は電気的に絶縁された接続を有する。前記ＩＣは、ダイ設置領域に装着された複数のボンディングパッドを有する半導体デバイスを具える。複数のボンディングフィンガーが前記ダイ設置領域を取り囲んでいる。それぞれの第１の端が半導体デバイス上の対応するボンディングパッドに接続され、それぞれの第２の端が対応するボンディングフィンガーに接続された複数の互いに孤立した接続導体が存在する。前記複数の互いに孤立した接続導体の一部は絶縁材料で被膜されている。
更なる他の実施例において、パッケージ基板内に電気的に絶縁された接続を有する集積回路（ＩＣ）デバイスが存在する。前記ＩＣデバイスは、ダイ設置領域上に装着された複数のボンディングパッドを有する半導体デバイスを具える。ボンディングフィンガーが前記ダイ設置領域を取り囲んでいる。それぞれの第１の端が半導体デバイス上の対応するボンディングパッドに接続され、それぞれの第２の端が対応するボンディングフィンガーに接続された複数の信号接続導体が存在する。信号接続導体のいくつかは、弾性絶縁材で被膜されたボンドワイヤである。それぞれの第１の端が半導体デバイス上の対応するボンディングパッドに接続され、それぞれの第２の端が対応するボンディングフィンガーに接続された複数の基準電圧導体が存在する。前記基準電圧導体のいくつかは、絶縁材料のダムで囲まれた導電ストラップである。保護膜が前記半導体基板上の半導体デバイス、信号接続導体、基準電圧導体およびボンドフィンガーを封止する。
他の実施例では、半導体デバイスチップを含むパッケージ基板内に強化された導体を設ける方法が提供される。前記方法では適切なパッケージ基板とボンドフィンガーの組み合わせを選択する。選択されたボンドフィンガーの上に基準電圧の位置を決定する。続いて絶縁化する信号ピンを決定する。ストラップ溝を印刷するパターンをマスクに決定し、前記マスクを使用してストラップ溝を前記パッケージ基板に形成する。導電材料を堆積して前記ストラップ溝内に充填する。先に決定した信号ピンを絶縁または非絶縁ワイヤでボンディングする。絶縁信号線のそれぞれの端をそれぞれのボンドパッドおよびボンドフィンガーにて密閉する。半導体デバイスチップを保護膜内に封止する。
本発明の上記の要約は、本発明が開示する全ての実施例あるいは全ての特徴を示すことを意図したわけではない。他の特徴および実施例は、以下の図と詳細な説明で提供される。
本発明は、添付の図と関連して以下に記載する本発明の様々な実施例の詳細な説明を参酌すると完全に理解出来る。
本発明は様々な変更および代替が可能であり、その詳細が図に例示され、以下に詳細に説明される。しかし本発明を特定の個々の実施例に限定されないことに注意されたい。むしろ本発明は従属する請求項により特定された本発明の精神および範囲に含まれる全ての変更例、同等例、および代替例をカバーするものである。
本発明はワイヤボンドパッケージ内における電気導体の短絡の可能性を低減するのに有用であることが示された。短絡は弾性絶縁材料でボンドワイヤを絶縁化することによって防止される。さらに、導電ストラップを用いて電源と接地をそれぞれのボンドパッドとパッケージリードフレームのボンドフィンガーとの間に接続することによって、前記ワイヤボンドパッケージの電気的特性が改良される。前記導電ストラップは、絶縁ボンドワイヤのインピーダンスを低減する。更なる増強のために、前記導電ストラップ間に絶縁材料を介在させてもよい。形成材料で封止する間、介在された絶縁材料がボンドワイヤおよび導電ストラップの運動を最小限に食い止める。導体の接触を引き起こすどのような運動も、これらの導体は絶縁材料で保護されるため、これらの導体を短絡しない。
一実施例において、本発明を利用することによりボールグリッドアレイ（ＢＧＡ）パッケージを改良した。導電ストラップはＩＣデバイスの電源と接地パッドをパッケージ基板上のそれぞれのボンドフィンガーに接続する。導電ストラップ付近のボンドワイヤは弾性材料で絶縁化される。導電ストラップ付近にないボンドワイヤは、他のボンドワイヤに対して短絡しそうにないため絶縁化されない。
図１Ａを参照されたい。一つのＩＣデバイスがＢＧＡ基板５内にパッケージされている。半導体デバイス１００がダイ設置領域１０上に装着されている。半導体デバイス１００は複数のボンドパッド２０ａ、２５ａ、３０ａ、および３５ａを有する。複数のボンドフィンガー２０ｂ、２５ｂ、３０ｂ、および３５ｂを有するリードフレームが前記ダイ装着領域１０を取り囲んでいる。これらのボンドパッド（２０ａ、２５ａ、３０ａ、および３５ａ）とボンドフィンガー（２０ｂ、２５ｂ、３０ｂ、および３５ｂ）はそれぞれ互いに接続される。この例では、ボンドフィンガー２５ｂは電源（ＶＤＤ）接続であり、ボンドフィンガー３０ｂは接地（ＧＮＤ）接続、そしてボンドフィンガー２０ｂは第１の信号（ＳＩＧ）接続である。本発明の一実施例では、これらの３つの接続を取り囲む絶縁材料が付加される。別の信号接続（ＳＩＧ２）のボンドフィンガー３５ｂはボンドワイヤによってボンドパッド３５ａに接続される。
絶縁材料の層１５が基板５に塗布される。導電ストラップ領域２５ｃがＶＤＤボンドフィンガー２５ｂとボンドパッド２５ａの間に決定される。他の導電ストラップ領域３０ｃがＧＮＤボンドフィンガー３０ｂおよびボンドパッド３０ａの間に決定される。孔２０ｃがＳＩＧボンドフィンガー２０ｂとボンドパッド２０ａの間に決定される。別の孔３５ｃがボンドフィンガー３５ｂおよびボンドパッド３５ａの間に決定される。導電ストラップ領域はフォトリソグラフィにより決定されても良い。またソルダーマスクに組み込んでも良い。成形樹脂領域で導電ストラップを含む溝を決定してもよい。個々のプロセスにおいて、塗装または噴霧によりパリレン樹脂を選択的に塗布してもよい。
図１Ｂを参照されたい。信号（ＳＩＧ）として規定されたボンドパッド２０ａ上で、ボンドワイヤ４０がボンドパッド２０ａを、信号ピン５５に接続するボンドフィンガー２０ｂに接続している。ボンドワイヤ４０は弾性絶縁材４５で被覆されている。非絶縁ワイヤの代わりに、自動ボンディング装置は絶縁ボンドワイヤを分配する。ボンドワイヤは個々の用途に応じて金、銅、あるいはアルミニウムにしてよい。ボンドワイヤはパリレン、エポキシ、あるいはポリカーボネートで絶縁化されてよい。接地（ＧＮＤ）として規定された別のボンドパッド３０ａ上において、導電ストラップ３０ｄが導電ストラップ領域３０ｃ内に形成され、ボンディングパッド３０ａをパッケージ接地ピンに接続するボンドフィンガー３０ｂに接続する。ＶＤＤなどの電源（ＰＷＲ）として規定された別のボンドパッド２５ａ上において、導電ストラップ２５ｄが導電ストラップ領域２５ｃ内に形成される。ボンディングパッド２５ａはパッケージ接地ピンに接続するボンディングフィンガー２５ｂに接続される。ボンドパッド３５ａは非絶縁ボンドワイヤ５０によりボンドフィンガー３５ｂに接続される。この領域では、保護膜内に封止中に隣接するボンドワイヤが屈曲して互いに接触する可能性はほとんどない。導電材料としてはスパッタ金属、電気めっき金属、硬化処理が施されたスラリー状の導電プラスチックあるいはプラズマ蒸着金属などでよい。導電材料は、金、銀、アルミニウム、ニッケル、導電ポリマーなどが挙げられるが、それらに制限されるわけではない。更なる導電材料として、アルミニウム、銅、銀、ニッケル、およびカーボンナノチューブなどの導電性充填材を含むプラスチックなども挙げられる。
図１Ｃを参照されたい。前記パッケージ基板５には、パッケージに電気的に接続された半導体デバイス１００が保護被膜５０内に封止される。
図１Ｄおよび１Ｅは図１Ｃのパッケージされた半導体デバイス１００の異なる領域の側面図を示す。図１Ｄは部分１５ａにおいて絶縁材料１５で囲まれた導電ストラップ２５ｄを示す。図１Ｅは絶縁ボンドワイヤ４０および非絶縁ボンドワイヤ５０を示す。保護被膜５０はこれらのボンドワイヤ４０、５０を封止する。絶縁材料１５は導電ストラップ２５ｄおよび３０ｄが封止中持続する力によって移動することを防止する。
本発明による他の実施例では、絶縁ボンドワイヤ４０は、ボンドフィンガーおよびボンドパッドにて追加の絶縁化がなされ、絶縁被覆４５の両端が密閉される。図１Ｆを参照されたい。ボンドワイヤ４０は完全に絶縁されている。完全に絶縁されたボンドワイヤを導電材料で覆うことができる。この導電材料は電源や接地などの基準電圧に接続される。基準電圧が完全に絶縁されたボンドワイヤに近づくほど、基準電圧に対するボンドワイヤのインピーダンスが低減する。
これまで記載された実施例は基板に塗布された単層の絶縁材料について適用可能であり、導電ストラップは同一面上に位置している。しかし、本発明は複数層の導電ストラップと絶縁層が使用される基板においても適用可能である。
図２を参照されたい。半導体デバイス２００は本発明の一実施例により組み立てられている。基板２０５はそれぞれパワー（ＰＷＲ）用、接地（ＧＮＤ）用、信号（ＳＩＧ）用および第２の信号（ＳＩＧ２）用のボンドフィンガー２１０ｂ、２１５ｂ、２２０ｂおよび２２５ｂを有する。ダイ設置領域３１０上に装着された半導体デバイスダイ３００上に、それぞれＰＷＲ、ＧＮＤ、ＳＩＧ、およびＳＩＧ２として規定されたボンドパッド２１０ａ、２１５ａ、２２０ａ、および２２５ａが存在する。これらのボンドパッドは、対応するボンドフィンガー２１０ｂ、２１５ｂ、２２０ｂ、および２２５ｂに電気的に接続され、それらのボンドフィンガー上にはんだボールを設けてもよい。ＳＩＧはそのボンドフィンガー２２０ｂを半導体デバイス２００上のボンドパッド２２０ａに接続するボンドワイヤ２５０を有する。ボンドワイヤ２５０は絶縁材料２５５で被覆されている。ボンドフィンガー２２０ｂ（ＳＩＧ）にて、絶縁材料２５５で被覆されたボンドワイヤ２５０は別の絶縁材料２６０の中に封止することができ、ボンドパッド２２０ａにて、絶縁材料２５５で被覆されたボンドワイヤ２５０は別の絶縁材料２６５の中に封止することができる。これらの付加的な封止ステップは、付近に形成される他の導電体に対する短絡から保護するのに役立つ。導電ストラップ２１５は、パッドランド２１５ｂ（ＧＮＤ）とボンドパッド２１５ａとを接続する。導電ストラップ２１５上に絶縁材料２７０を塗布することができる。次の導電層２１０ｃはボンドフィンガー２１０ｂ（ＰＷＲ）に接続する。絶縁材料２７０は導電ストラップ２１０ｃとストラップ２１５との短絡を防止する。導電ストラップ２１０ｃ上に、更なる絶縁材料２７５を塗布することができる。短絡に対して特別な注意を必要としない領域において、ボンドワイヤ２３０はボンドパッド２２５ａをＳＩＧ２にてボンドフィンガー２２５ｂと接続する。上述したようにデバイスダイ３００を装着し電気接続を施した後、組み立て品は絶縁材料２８０で封止される。
他の実施例において、図１に示されているパッケージが使用されるかもしれないが、更なる絶縁ダムが導電ストラップの間に規定されている。これらのダムは、封止中に導電ストラップが運動して場合によってはお互いに短絡する可能性を低減する。
デバイス上に複数の電源レールと基準接地が存在する場合がある。複雑なＩＣデバイス中では複数の電源が利用可能である。例えば、それぞれ別個の電源バスおよび接地バスを内部コアのために及び入力／出力ピンの外部リングのために規定することができる。多くの場合、これらの別個の電源／接地バスは、スイッチングトランジェントをＩＣデバイスコアから分離することによってデバイス性能を改良するのに役立つ。
本発明はＩＣデバイスダイを接続するためにワイヤボンディングを使用する様々なパッケージに適用出来る。これらのパッケージにはリードレスチップキャリア（ＬＣＣ）、ボールグリッドアレイ（ＢＧＡ）などが挙げられるが、それらに制限されない。
図３を参照されたい。本発明によるＩＣデバイスをパッケージングするプロセス例１００においては、利用者はまず適切なパッケージタイプを選択する（ステップ１１０）。続いて半導体ダイを取り囲む選択したボンドフィンガーに基準電圧ピン（つまりＶＤＤとＧＮＤ）の位置を規定する（ステップ１２０）。さらに信号ピン（つまり入力と出力）の位置を決定する（ステップ１３０）。インピーダンスが制御されなければならないこれらの信号ピンは基準電圧ピンの近くに位置させることができる。これらのピンはまた、続く成形材料内への封止中に移動されやすいため、絶縁ボンドワイヤの使用が必要である。さらにこれらの絶縁ボンドワイヤの端における絶縁化を考慮する必要がある。基準電圧と信号ピンの位置は、個々のＩＣデバイス、パッケージデザインの制限、製造の容易さ、コスト等によって決まる。
ステップ１３０で信号ピンと基準電圧ピンの位置を決定した後、ＩＣボンドパッドをそれぞれのパッケージボンドフィンガーと接続する導電ストラップの位置を決定する（ステップ１４０）。絶縁溝と絶縁ダムがパッケージ基板上にプリントされるようにストラップマスクを形成する。これらの溝は弾性絶縁材料で形成されても良い。これらの絶縁材料にはエポキシ、サーモプラスチックまたはシリコーン樹脂などが挙げられるが、それらに制限されない。一プロセス例においては、ストラップマスクパターンは標準的なリソグラフィ技術によって被着される。ＩＣのボンドパッドとその対応するボンドフィンガーとを取り囲む溝を形成する。利用者は溝を充填するために導電材料を塗布する（ステップ１５０）。基準電圧はボンドワイヤによって与えられる電気接続よりも強固な電気接続を有し、より高い電流を流すことが出来る。基準電圧のための電気接続を行った後、ワイヤボンドを用いるピンをボンディングする（ステップ１６０）。ボンドワイヤを互いの短絡から保護するために、弾性絶縁材料で被覆されたボンドワイヤを使用する。絶縁ボンドワイヤの端にて（ボンドパッドおよびリードフレームのボンドフィンガーにて）更なる絶縁化プロセス１７０を追加することができる。ＩＣデバイスダイと接続を損傷から保護するために、パッケージは適切な成形材料内への封止プロセス１８０を受ける。
本発明は幾つかの特定の実施例に関して記載されているが、当業者は添付の特許請求の範囲に記載されている本発明の精神および範囲から離れることなく、多くの変更が可能であることを認識されよう。
パッケージ基板の上面図であり、本発明の一実施例におけるパッケージ基板の個々のボンドパッドとボンドフィンガーとの間に形成された基準電圧ストラップを決定する絶縁トレンチを示す。 図１Ａの上面図であって、絶縁トレンチが導電材料で充填され基準電圧をＩＣデバイスダイからパッケージ基板に接続する。 絶縁被膜内に封止された図１Ｂの上面図である。 絶縁材料に覆われた電源ストラップを示す図１Ｃの断面図である。 本発明による絶縁ボンドワイヤを示す図１Ｃの断面図である。 本発明の他の実施例の断面図である。 導電ストラップとして多層膜を使用し、一つの導電ストラップが絶縁ボンドワイヤを覆うパッケージの断面図である。 本発明の一実施例による電気的に強化されたパッケージの製造プロセスのフローチャートである。

Claims (10)

  1. 電気的に絶縁された接続を有するパッケージ内に実装された集積回路（ＩＣ）デバイスであって、
    該ＩＣデバイスは、
    ダイ設置領域と該ダイ設置領域に隣接する第１のフィンガー領域とを具える基板であって、前記第１のフィンガー領域は第１のボンドフィンガーと第２のボンドフィンガーと第３のボンドフィンガーとを具え、前記第１のボンドフィンガーは前記第２のボンドフィンガーより前記ダイ設置領域に近く、前記第３のボンドフィンガーは前記第２のボンドフィンガーよりも前記ダイ設置領域から遠い、基板と、
    前記ダイ設置領域に装着された半導体デバイスであって、該半導体デバイスは第１のボンドパッドと第２のボンドパッドと第３のボンドパッドとを具え、前記第１のボンドパッドは前記第２のボンドパッドよりも前記第１のフィンガー領域に近く、前記第３のボンドパッドは前記第２のボンドパッドよりも前記第１のフィンガー領域から遠い、半導体デバイスと、
    前記第１のボンドパッドを覆うが、前記第２のボンドパッドを覆わない、第１の絶縁材料と、
    前記第１のボンドフィンガーを覆うが、前記第２のボンドフィンガーを覆わない、第２の絶縁材料と、
    前記第１のボンドパッドと前記第１のボンドフィンガーとを接続し、絶縁被覆により隔離され、前記第１の絶縁材料及び前記第２の絶縁材料により封止される、第１のボンドワイヤと、
    前記第２のボンドパッドを前記第２のボンドフィンガーに接続し、前記第１の絶縁材料、前記第２の絶縁材料及び前記絶縁被覆を覆う、第１の導電ストラップと、
    前記第１の導電ストラップ、前記第２のボンドフィンガーと前記第３のボンドフィンガーとの間の前記基板、及び、前記第２のボンドパッドと前記第３のボンドパッドとの間の前記半導体デバイスを覆う、第３の絶縁材料と、
    前記第３のボンドパッドを前記第３のボンドフィンガーに接続し、前記第３の絶縁材料を覆う、第２の導電ストラップと、
    を具える、ＩＣデバイス。
  2. 前記第１のボンドワイヤは、前記第１のボンドパッドと前記第１のボンドフィンガーとの間の第１の信号接続を与える、請求項１に記載されたＩＣデバイス。
  3. 前記第１の導電ストラップは、前記第２のボンドパッドと前記第２のボンドフィンガーとの間の接地接続を与える、請求項１または請求項２に記載されたＩＣデバイス。
  4. 前記第１の導電ストラップが、銅、アルミニウム、金、銀、ニッケル、はんだ、導電性充填材を有するプラスチック、のうちの少なくとも一つである、請求項１から請求項３のいずれか１項に記載されたＩＣデバイス。
  5. 前記基板がリードフレームまたはボールグリッドアレイ（ＢＧＡ）パッケージ基板である、請求項１から請求項４のいずれか１項に記載されたＩＣデバイス。
  6. 前記第２の導電ストラップは、前記第３のボンドパッドと前記第３のボンドフィンガーとの間の電源接続を与える、請求項１から請求項５のいずれか１項に記載されたＩＣデバイス。
  7. 前記第２の導電ストラップが、銅、アルミニウム、金、銀、ニッケル、はんだおよび導電充填材を有するプラスチック、のうちの少なくとも一つである、請求項６に記載されたＩＣデバイス。
  8. 前記基板は、第４のボンドフィンガーを具える第２のフィンガー領域をさらに具え、前記第１のフィンガー領域及び前記第２のフィンガー領域は前記ダイ設置領域を挟み込み、
    前記半導体デバイスは、前記第１のフィンガー領域よりも前記第２のフィンガー領域に近い、第４のボンドパッドをさらに具え、
    第２のボンドワイヤは、前記第４のボンドパッドと前記第４のボンドフィンガーとを接続する、請求項１から請求項７のいずれか１項に記載されたＩＣデバイス。
  9. 前記第２のボンドワイヤは、前記第４のボンドパッドと前記第４のボンドフィンガーとの間の第２の信号接続を与える、請求項８に記載されたＩＣデバイス。
  10. 前記半導体デバイス、前記基板、前記ボンドワイヤ、前記導電ストラップおよび前記ボンドフィンガーを封止する保護膜をさらに具える、請求項１から請求項９のいずれか１項に記載されたＩＣデバイス。
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EP2002478A1 (en) 2008-12-17
EP2002478B1 (en) 2016-09-07
JP2009530842A (ja) 2009-08-27
WO2007107964A1 (en) 2007-09-27
CN101410974B (zh) 2013-02-20
US20090102067A1 (en) 2009-04-23
US8203219B2 (en) 2012-06-19
CN101410974A (zh) 2009-04-15

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