JP5330376B2 - 集積装置及びその製造方法、並びに、システム・イン・パッケージ - Google Patents
集積装置及びその製造方法、並びに、システム・イン・パッケージ Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 239000003990 capacitor Substances 0.000 claims description 227
- 239000000758 substrate Substances 0.000 claims description 153
- 239000004065 semiconductor Substances 0.000 claims description 39
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 238000000708 deep reactive-ion etching Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
第1の基板側及び反対側の第2の基板側を有する半導体基板と;
半導体基板の第1の基板側から、第2の基板側まで延在する基板貫通ビアと;
半導体基板におけるトレンチキャパシタと;
を有する集積装置であって、
前記トレンチキャパシタは、少なくとも4つの多数の導電性のキャパシタ電極層を異なるキャパシタ電極層が互いに電気的に絶縁されるように誘電体層と交互の配列で含んでいるトレンチ充填物を有し;
キャパシタ電極層は、第1又は第2の基板側に設けたキャパシタ端子に接続され;
トレンチキャパシタ及び基板貫通ビアは、それぞれ、半導体基板中に10μmを超える同等の横方向の延びを有するトレンチ開口及びビア開口内に形成されることを特徴とする。
前記キャパシタ電極層は、それぞれ、前記第1又は第2の基板側に設けた各割り当てられたキャパシタ端子に接続されるようにする。
第1の基板側と反対側の第2の基板側とを有する半導体基板を準備するステップと;
前記半導体基板中に、10μmを越える同等の横方向の延びを有し、且つ前記半導体基板の前記第1の基板側から反対側の前記第2の基板側の方へ延在する、トレンチ開口及びビア開口を同時に形成するステップと;
前記トレンチ開口内に、少なくとも4つの多数の導電性のキャパシタ電極層を誘電層と交互の配列で含むトレンチ充填物を製造し、異なるキャパシタ電極層は互いに電気的に絶縁されるようにする、トレンチ充填物形成ステップと;
前記第1又は第2の基板側上に2つのキャパシタ端子を製造し、設けられたキャパシタ端子に前記キャパシタ電極層を交互に接続するステップと;
前記ビア開口に基板貫通ビアを製造するステップと、を含む。
マルチキャパシタを4つの異なる設定にすることができる。その設定は、以下の通りである。
ステップ502:少なくとも10μmの横方向の延びを有するトレンチ開口及びビア開口を同時に形成する;
ステップ504:トレンチキャパシタのためのトレンチ充填物及び貫通基板ビアのためのビア充填物を製造する;
ステップ506:キャパシタ端子を製造して、接続する。
Claims (14)
- 第1の基板側及び反対側の第2の基板側を有する半導体基板と;
前記第1の基板側から、前記第2の基板側まで延在する基板貫通ビアと;
前記半導体基板におけるトレンチキャパシタと;
を有する集積装置であって、
前記トレンチキャパシタは、少なくとも4つの多数の導電性のキャパシタ電極層を異なるキャパシタ電極層が互いに電気的に絶縁されるように、誘電層と交互の配列で含んでいるトレンチ充填物を有し、;
前記キャパシタ電極層は、前記第1又は第2の基板側に設けたキャパシタ端子に接続され;
前記トレンチキャパシタ及び基板貫通ビアは、それぞれ、前記半導体基板中に10μmを超える同等の横方向の延びを有するトレンチ開口及びビア開口内に形成されることを特徴とする、集積装置。 - 前記半導体基板は、前記第1の基板側から前記第2の基板側まで延在し、且つ前記トレンチキャパシタは、第1のドープドウェル内に形成される、請求項1に記載の集積装置。
- 前記開口の底部及び/又は側壁に最も近いキャパシタ電極層は、前記キャパシタ端子のいずれにも接続されない、請求項2に記載の集積装置。
- 前記半導体基板における第2のドープドウェル内に配置されるトランジスタを備えている、請求項3に記載の集積装置。
- 前記トレンチキャパシタの誘電体層は、SiO2又はSi3N4又は酸窒化シリコンで作成される、請求項1に記載の集積装置。
- 前記キャパシタ電極層は、ポリシリコンで作成される、請求項1に記載の集積装置。
- 前記トレンチキャパシタ及び前記基板貫通ビアは、前記半導体基板に15〜100μmの間の同等の横方向の延びを有するそれぞれの開口内に形成される、請求項1に記載の集積装置。
- 前記トレンチ開口は、前記第1の基板側から前記第2の基板側までの深さ方向における当該トレンチ開口の深さの延びと、第1の基板側の主基板表面に平行な方向における横方向の延びとの比によって定義されるアスペクト比を有し、当該アスペクト比は少なくとも2である、請求項1に記載の集積装置。
- 前記トレンチキャパシタは、少なくとも500nF/mm2のキャパシタンス密度を有する、請求項1に記載の集積装置。
- 前記半導体基板に設定可能なトレンチキャパシタをさらに備え、
前記設定可能なトレンチキャパシタは、異なるキャパシタ電極層が互いに電気的に絶縁されるように、少なくとも4つの、多数の導電性のキャパシタ電極層を誘電体層との交互の配列で含んでいるトレンチ充填物を有し;
前記キャパシタ電極層は、それぞれ、前記第1又は第2の基板側に設けた各割り当てられたキャパシタ端子に接続される、請求項1に記載の集積装置。 - 異なるキャパシタ電極層間に電気的に相互接続される複数のスイッチング素子を有するスイッチングユニットであって、前記個々のスイッチング素子は、第1のスイッチング状態においては、2つの各キャパシタ電極層を互いに電気的に接続するように設定され、且つ第2のスイッチング状態においては、前記と同一の2つの各キャパシタ電極層を互いに電気的に切り離すように設定され、前記スイッチング素子は、制御入力端子を有し、且つ当該制御入力端子に印加されるスイッチ制御信号に基づいて、第1又は第2のスイッチング状態を担うように設定される、スイッチングユニットと;
前記スイッチングユニットに接続され、且つ前記トレンチ充填物のキャパシタ電極層を用いて複数のマルチキャパシタ構成の各1つを形成するための、それぞれの制御信号を生成して、前記スイッチングユニットに供給するように設定される制御ユニットと、をさらに備えている、請求項1に記載の集積装置。 - 請求項1に記載の集積装置を備えている、システム・イン・パッケージ。
- 集積装置を製造する方法であって、
第1の基板側と反対側の第2の基板側とを有する半導体基板を準備するステップと;
前記半導体基板中に、10μmを越える同等の横方向の延びを有し、且つ前記半導体基板の前記第1の基板側から反対側の前記第2の基板側の方へ延在する、トレンチ開口及びビア開口を同時に形成するステップと;
前記トレンチ開口内に、少なくとも4つの多数の導電性のキャパシタ電極層を誘電層と交互の配列で含むトレンチ充填物を製造し、異なるキャパシタ電極層は互いに電気的に絶縁されるようにする、トレンチ充填物形成ステップと;
前記第1又は第2の基板側上に2つのキャパシタ端子を製造し、設けられたキャパシタ端子に前記キャパシタ電極層を交互に接続するステップと;
前記ビア開口に基板貫通ビアを製造するステップと、を含むことを特徴とする、集積装置の製造方法。 - 前記トレンチ開口とビア開口との同時形成ステップは、当該トレンチ開口とビア開口とを形成するための深堀り反応性イオンエッチングを行うステップを含む、請求項13に記載の集積装置の製造方法。
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Application Number | Priority Date | Filing Date | Title |
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EP07107974 | 2007-05-10 | ||
EP07107974.3 | 2007-05-10 | ||
PCT/IB2008/051824 WO2008139393A1 (en) | 2007-05-10 | 2008-05-08 | Integration substrate with a ultra-high-density capacitor and a through-substrate via |
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JP2010530128A JP2010530128A (ja) | 2010-09-02 |
JP5330376B2 true JP5330376B2 (ja) | 2013-10-30 |
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US (1) | US8729665B2 (ja) |
EP (2) | EP2145351A1 (ja) |
JP (1) | JP5330376B2 (ja) |
WO (1) | WO2008139393A1 (ja) |
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US12002758B2 (en) | 2021-11-04 | 2024-06-04 | International Business Machines Corporation | Backside metal-insulator-metal (MIM) capacitors extending through backside interlayer dielectric (BILD) layer or semiconductor layer and partly through dielectric layer |
TWI799061B (zh) * | 2022-01-07 | 2023-04-11 | 力晶積成電子製造股份有限公司 | 電容器結構及其製造方法 |
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JPH01179443A (ja) * | 1988-01-06 | 1989-07-17 | Fujitsu Ltd | 半導体装置 |
US6261895B1 (en) | 1999-01-04 | 2001-07-17 | International Business Machines Corporation | Polysilicon capacitor having large capacitance and low resistance and process for forming the capacitor |
US6689643B2 (en) | 2002-04-25 | 2004-02-10 | Chartered Semiconductor Manufacturing Ltd. | Adjustable 3D capacitor |
US7030481B2 (en) * | 2002-12-09 | 2006-04-18 | Internation Business Machines Corporation | High density chip carrier with integrated passive devices |
WO2004114397A1 (en) | 2003-06-20 | 2004-12-29 | Koninklijke Philips Electronics N.V. | Electronic device, assembly and methods of manufacturing an electronic device |
DE10358299A1 (de) * | 2003-12-12 | 2005-07-14 | Infineon Technologies Ag | Kondensatorbauelement |
US7435627B2 (en) * | 2005-08-11 | 2008-10-14 | International Business Machines Corporation | Techniques for providing decoupling capacitance |
EP1949418A2 (en) * | 2005-11-08 | 2008-07-30 | Nxp B.V. | Integrated capacitor arrangement for ultrahigh capacitance values |
JP5054019B2 (ja) * | 2005-11-08 | 2012-10-24 | エヌエックスピー ビー ヴィ | 高周波数動作においてアプリケーションを分離するのに適したトレンチキャパシタ装置 |
WO2007131967A1 (en) | 2006-05-15 | 2007-11-22 | Koninklijke Philips Electronics N.V. | Integrated low-loss capacitor-arrray structure |
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US20100244189A1 (en) | 2010-09-30 |
EP2145351A1 (en) | 2010-01-20 |
EP3043381A1 (en) | 2016-07-13 |
WO2008139393A1 (en) | 2008-11-20 |
US8729665B2 (en) | 2014-05-20 |
JP2010530128A (ja) | 2010-09-02 |
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