JP5273749B2 - Method for manufacturing printed wiring board - Google Patents

Method for manufacturing printed wiring board Download PDF

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JP5273749B2
JP5273749B2 JP2011050952A JP2011050952A JP5273749B2 JP 5273749 B2 JP5273749 B2 JP 5273749B2 JP 2011050952 A JP2011050952 A JP 2011050952A JP 2011050952 A JP2011050952 A JP 2011050952A JP 5273749 B2 JP5273749 B2 JP 5273749B2
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connection pad
insulating layer
diameter
semiconductor chip
wiring board
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JP2011109152A (en
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裕幸 森
一茂 河崎
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a printed wiring board in which a solder bump of a mounted semiconductor chip is unlikely to break. <P>SOLUTION: A coreless substrate 20 which is a kind of printed wiring board includes an insulating layer 26a having a principal surface and a connection pad 24 buried in the insulating layer 26a. The connection pad 24 is in a shape of a hat with a brim. Namely, the connection pad 24 comprises a plate portion 36 having a diameter &phiv;1 of 95 &mu;m and a contact portion 38 having a diameter &phiv;c of 75 &mu;m. A principal surface 39 of the contact portion 38 is exposed on the principal surface 7 of the insulating layer 26a. Since the diameter &phiv;c of the contact portion 38 is substantially equal to a diameter &phiv;2 of a bump base metal 11 on the side of the semiconductor chip 8, mechanical stress applied in a direction wherein a semiconductor chip 8 is drawn and peeled from the coreless substrate 20 is dispersed equally to both sides of the connection pad 24 and bump base metal 11 in such a case, so that breakage is unlikely to occur. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

本発明は、プリント配線板及びその製造方法に関し、さらに詳しくは、コア基板を有さないコアレス基板、半導体パッケージ及びそれらの製造方法に関する。   The present invention relates to a printed wiring board and a method for manufacturing the same, and more particularly to a coreless substrate having no core substrate, a semiconductor package, and a method for manufacturing the same.

米国第５９２６７９８号特許明細書（特許文献１）は、Ｃ４(Controlled Collapse Chip Connection)技術を用いたフリップチップ実装技術を開示する。この技術は、半導体チップ（ＩＣチップ）をプリント配線板上に実装するものである。実装される半導体チップは、多数のはんだバンプアレイを備える。   US Pat. No. 5,926,798 (Patent Document 1) discloses a flip chip mounting technique using a C4 (Controlled Collapse Chip Connection) technique. In this technique, a semiconductor chip (IC chip) is mounted on a printed wiring board. The semiconductor chip to be mounted includes a large number of solder bump arrays.

図１４は、Ｃ４技術により、コア基板を有さないコアレス基板上に半導体チップを実装した半導体パッケージのはんだバンプ周辺を拡大して示す断面図である。同図に示されるように、コアレス基板１は、絶縁層２と、ランド３と、ビア４と、接続パッド５とを備える。ランド３は円柱（薄い円板）状をなし、絶縁層２内に完全に埋設される。接続パッド５もランドの一種で円柱（薄い円板）状をなし、絶縁層２内に埋設されるが、その主面６は絶縁層２の主面７で露出する。ビア４は円錐台又は円柱状をなし、ランド３と接続パッド５との間に形成され、ランド３と接続パッド５とを電気的に接続する。   FIG. 14 is an enlarged cross-sectional view showing the periphery of a solder bump of a semiconductor package in which a semiconductor chip is mounted on a coreless substrate that does not have a core substrate by C4 technology. As shown in the figure, the coreless substrate 1 includes an insulating layer 2, lands 3, vias 4, and connection pads 5. The land 3 has a cylindrical shape (thin disc) and is completely embedded in the insulating layer 2. The connection pad 5 is also a kind of land and has a cylindrical (thin disc) shape and is embedded in the insulating layer 2, but its main surface 6 is exposed at the main surface 7 of the insulating layer 2. The via 4 has a truncated cone shape or a cylindrical shape, and is formed between the land 3 and the connection pad 5, and electrically connects the land 3 and the connection pad 5.

一方、半導体パッケージ１０は、バンプアレイを構成するはんだバンプ９を備える。半導体チップ８の底面には、はんだバンプ９に加わる衝撃を吸収するために、クッション膜１３が形成される。また、はんだバンプ９の下（はんだバンプ９と半導体チップ８の底面との間）には、バンプ下地金属(UBM; Under Bump Metal)１１がメッキされる。   On the other hand, the semiconductor package 10 includes solder bumps 9 constituting a bump array. A cushion film 13 is formed on the bottom surface of the semiconductor chip 8 in order to absorb the impact applied to the solder bumps 9. Further, under the solder bump 9 (between the solder bump 9 and the bottom surface of the semiconductor chip 8), a bump base metal (UBM) 11 is plated.

接続パッド５上にはんだバンプ９を搭載し、あらかじめ付着されたはんだ１２を溶融し、はんだバンプ９を接続パッド５にはんだ付けする。これにより、半導体チップ８はコアレス基板１に実装される。   The solder bump 9 is mounted on the connection pad 5, the solder 12 adhered in advance is melted, and the solder bump 9 is soldered to the connection pad 5. Thereby, the semiconductor chip 8 is mounted on the coreless substrate 1.

ここで、接続パッド５の直径φ１は約９５μｍであり、バンプ下地金属１１の直径φ２は約７５μｍであり、接続パッド５の直径φ１はバンプ下地金属１１の直径φ２よりも大きい。そのため、半導体チップ８をコアレス基板１から引き剥がす方向に機械的な応力が加わると、その応力は小径のバンプ下地金属１１側に集中し、その部分から破断が起こりやすい。   Here, the diameter φ1 of the connection pad 5 is about 95 μm, the diameter φ2 of the bump base metal 11 is about 75 μm, and the diameter φ1 of the connection pad 5 is larger than the diameter φ2 of the bump base metal 11. Therefore, when mechanical stress is applied in the direction in which the semiconductor chip 8 is peeled off from the coreless substrate 1, the stress is concentrated on the small-diameter bump base metal 11 side, and breakage tends to occur from that portion.

接続パッド５の直径φ１をバンプ下地金属１１の直径φ２と同じにすることができれば、機械的な応力は接続パッド５及びバンプ下地金属１１の両側に均等に分散し、破断が起こりにくくなると予想される。しかしながら、以下の理由で、これらの径を同じにすることはできない。   If the diameter φ1 of the connection pad 5 can be made the same as the diameter φ2 of the bump base metal 11, the mechanical stress is evenly distributed on both sides of the connection pad 5 and the bump base metal 11, and it is expected that breakage is less likely to occur. The However, these diameters cannot be the same for the following reasons.

バンプ下地金属１１は約１５０μｍのピッチで形成しなければならない。しかしながら、バンプ下地金属１１の直径φ２を大きくすると、隣接するバンプ下地金属１１との間の距離が短くなる。そのため、メッキをパターン化してバンプ下地金属１１を形成するに際して、バンプ下地金属１１以外の領域にある不要なメッキを取り除くことが難しくなり、歩留まりが低下する。一方、接続パッド５の直径φ１を小さくすることも困難である。ビア４の直径や位置の製造公差を考慮すると、接続パッド５の直径φ１は９５μｍが限界だからである。   The bump base metal 11 must be formed at a pitch of about 150 μm. However, when the diameter φ2 of the bump base metal 11 is increased, the distance between the adjacent bump base metal 11 is shortened. Therefore, when the bump base metal 11 is formed by patterning the plating, it is difficult to remove unnecessary plating in a region other than the bump base metal 11, and the yield decreases. On the other hand, it is difficult to reduce the diameter φ1 of the connection pad 5. This is because the diameter φ1 of the connection pad 5 is limited to 95 μm in consideration of the manufacturing tolerance of the diameter and position of the via 4.

なお、特開２００３−３７１３５号公報（特許文献２）は、配線板上に、バンプを用いて半導体チップを実装する半導体装置において、配線板から半導体チップまでの高さを所定の高さに確保することが可能な技術を開示する（同公報００２１段落参照）。半導体チップを配線板上に搬送し、半導体チップの外部端子と配線板上の突起導体の位置合わせをして熱圧着する。半導体チップの外部端子上には、バンプ下地金属を介在させてはんだボールが設けられており、はんだボールを溶融して熱圧着した後の絶縁基板から半導体チップまでの高さを突起導体の高さ分だけ高くすることができる（同公報００５５段落参照）。しかしながら、突起導体は配線板から突出しているため、はんだボールの製造ばらつきによる量の変化、半導体チップの取付傾き、半導体チップの取付加重のばらつきなどにより、半導体チップの外部端子と配線板上の突起導体との接合面の直径を一定に確保することは困難である。   Japanese Patent Laid-Open No. 2003-37135 (Patent Document 2) secures a height from a wiring board to a semiconductor chip at a predetermined height in a semiconductor device in which a semiconductor chip is mounted on a wiring board using bumps. A technique that can be used is disclosed (see paragraph 0021 of the publication). The semiconductor chip is transferred onto the wiring board, and the external terminals of the semiconductor chip and the protruding conductors on the wiring board are aligned and thermocompression bonded. Solder balls are provided on the external terminals of the semiconductor chip with bump base metal interposed therebetween. The height from the insulating substrate to the semiconductor chip after the solder balls are melted and thermocompression bonded is the height of the protruding conductor. Can be increased by an amount (see paragraph 0055 of the same publication). However, since the protruding conductor protrudes from the wiring board, the protrusions on the external terminals of the semiconductor chip and the wiring board are affected by variations in the amount due to manufacturing variations of the solder balls, semiconductor chip mounting inclination, semiconductor chip mounting weight variations, etc. It is difficult to ensure a constant diameter of the joint surface with the conductor.

また、特開平１０−２４２６４９号公報（特許文献３）は、はんだバンプを備えた多層プリント配線板を開示する（同公報図１９及び図２０参照）。この多層プリント配線板上には、無電解銅めっき膜及び電解銅めっき膜が積層され、その上にはんだバンプが形成される。この配線板上にはまた、ソルダーレジストが形成される。しかしながら、銅めっき膜とソルダーレジストが重なる部分が凸になり、銅めっき膜がなくソルダーレジストのみがある部分が凹になるため、この多層プリント配線板の表面は平面にならない。そのため、多層プリント配線板とその上に実装される半導体チップとの間にアンダーフィル樹脂を均一速度で流し込むことができない。
米国第５９２６７９８号特許明細書 特開２００３−３７１３５号公報 特開平１０−２４２６４９号公報 特開平１０−２３３４１７号公報 特開２０００−２６９２７１号公報 Japanese Patent Laid-Open No. 10-242649 (Patent Document 3) discloses a multilayer printed wiring board provided with solder bumps (see FIGS. 19 and 20). On this multilayer printed wiring board, an electroless copper plating film and an electrolytic copper plating film are laminated, and solder bumps are formed thereon. A solder resist is also formed on the wiring board. However, the portion where the copper plating film and the solder resist overlap is convex, and the portion where there is no copper plating film and only the solder resist is concave, the surface of the multilayer printed wiring board is not flat. Therefore, the underfill resin cannot be poured at a uniform speed between the multilayer printed wiring board and the semiconductor chip mounted thereon.
US Pat. No. 5,926,798 JP 2003-37135 A Japanese Patent Laid-Open No. 10-242649 Japanese Patent Laid-Open No. 10-233417 JP 2000-269271 A

本発明の目的は、実装された半導体チップのはんだバンプが破断し難いプリント配線板、半導体パッケージ及びそれらの製造方法を提供することである。   An object of the present invention is to provide a printed wiring board, a semiconductor package, and a manufacturing method thereof, in which solder bumps of a mounted semiconductor chip are hardly broken.

課題を解決するための手段及び発明の効果Means for Solving the Problems and Effects of the Invention

本発明によるプリント配線板は、主面を有する絶縁層と、絶縁層内に埋設される接続パッドとを備える。前記接続パッドは、表裏を有するプレート部と、プレート部の表側に位置し、絶縁層の主面で露出する主面を有し、プレート部よりも小さいコンタクト部とを含む。   The printed wiring board according to the present invention includes an insulating layer having a main surface and a connection pad embedded in the insulating layer. The connection pad includes a plate portion having front and back surfaces, and a contact portion that is located on the front side of the plate portion, has a main surface exposed at the main surface of the insulating layer, and is smaller than the plate portion.

本発明によれば、接続パッドが鍔のある帽子(hat)状になっているため、コンタクト部のみを小さくし、たとえば実装される半導体チップのバンプ下地金属と同じくらいの面積（直径）となる半導体パッケージを製造することができる。これにより、半導体チップをプリント配線板から引き剥がす方向に機械的な応力が加わっても、その応力は接続パッド及びバンプ下地金属の両側に分散し、バンプの破断が起こりにくくなる。   According to the present invention, since the connection pad has a hooked hat shape, only the contact portion is reduced, and for example, the area (diameter) is the same as the bump base metal of the semiconductor chip to be mounted. A semiconductor package can be manufactured. As a result, even if mechanical stress is applied in the direction in which the semiconductor chip is peeled off from the printed wiring board, the stress is dispersed on both sides of the connection pad and the bump base metal, and the bumps are not easily broken.

好ましくは、プリント配線板はさらに、絶縁層内に埋設され、プレート部の裏側と接触するビアを備える。   Preferably, the printed wiring board further includes a via embedded in the insulating layer and in contact with the back side of the plate portion.

この場合、プレート部はビアに比べて大きいのでプレート部とビアの位置合わせマージンを有し、このため、ビアと確実に接続される。   In this case, since the plate portion is larger than the via, it has an alignment margin between the plate portion and the via, and is thus reliably connected to the via.

本発明によるプリント配線板の製造方法は、母材を用意する工程と、第１の貫通孔を有する第１の膜を母材上に形成する工程と、第１の貫通孔上に位置しかつ第１の貫通孔よりも大きい第２の貫通孔を有する第２の膜を第１の膜上に形成する工程と、第１及び第２の貫通孔内に金属を充填して接続パッドを形成する工程と、接続パッドの形成後、第１及び第２の膜を除去する工程と、母材及び接続パッドを覆うように絶縁層を形成する工程と、絶縁層の形成後、母材を除去する工程とを含む。   The method for manufacturing a printed wiring board according to the present invention includes a step of preparing a base material, a step of forming a first film having a first through hole on the base material, a position on the first through hole, and Forming a second film having a second through hole larger than the first through hole on the first film, and forming a connection pad by filling the first and second through holes with metal Removing the first and second films after forming the connection pad, forming an insulating layer so as to cover the base material and the connection pad, and removing the base material after forming the insulating layer. Including the step of.

本発明によれば、鍔のある帽子状の接続パッドを有するプリント配線板を容易に製造することができる。さらに、このプリント配線板を用いた半導体パッケージを製造することができる。   ADVANTAGE OF THE INVENTION According to this invention, the printed wiring board which has a hat-shaped connection pad with a ridge can be manufactured easily. Furthermore, a semiconductor package using this printed wiring board can be manufactured.

以下、図面を参照し、本発明の実施の形態を詳しく説明する。図中同一又は相当部分には同一符号を付してその説明は繰り返さない。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

図１を参照して、本発明の実施の形態による半導体パッケージ１０は、コアレス基板２０と、コアレス基板２０上に実装される半導体チップ８とを備える。コアレス基板２０は、ビルトアップ層２２と、複数のランド３と、複数のビア４と、複数の接続パッド２４とを備える。ビルトアップ層２２は、積層された複数の絶縁層２６からなる。ランド３は円柱（薄い円板）状をなし、絶縁層２６内に完全に埋設され、絶縁層２６内の配線層と接続される。ビア４は円柱又は円錐台状をなし、絶縁層２６内に完全に埋設され、ランド３と接続パッド２４との間に形成され、ランド３と接続パッド２４とを電気的に接続する層間接続部として機能する。接続パッド２４は、半導体チップ８側にある最も外側の絶縁層２６ａ内に埋設される。接続パッド２４の詳細は後述する。   Referring to FIG. 1, a semiconductor package 10 according to an embodiment of the present invention includes a coreless substrate 20 and a semiconductor chip 8 mounted on the coreless substrate 20. The coreless substrate 20 includes a built-up layer 22, a plurality of lands 3, a plurality of vias 4, and a plurality of connection pads 24. The built-up layer 22 includes a plurality of stacked insulating layers 26. The land 3 has a cylindrical (thin disc) shape, is completely embedded in the insulating layer 26, and is connected to the wiring layer in the insulating layer 26. The via 4 has a cylindrical or truncated cone shape, is completely embedded in the insulating layer 26, is formed between the land 3 and the connection pad 24, and electrically connects the land 3 and the connection pad 24. Function as. The connection pad 24 is embedded in the outermost insulating layer 26a on the semiconductor chip 8 side. Details of the connection pad 24 will be described later.

コアレス基板２０はさらに、接続パッド２８と、複数のはんだバンプ３０と、キャパシタ３２とを備える。   The coreless substrate 20 further includes connection pads 28, a plurality of solder bumps 30, and capacitors 32.

接続パッド２８は円柱（薄い円板）状をなし、接続パッド２４と反対側にある最も外側の絶縁層２６ｂ上に形成される。はんだバンプ３０は接続パッド２８にはんだ付けされ、ＢＧＡ端子を構成する。キャパシタ３２は接続パッド２８にはんだ付けされる。絶縁層２６ｂ上であって接続パッド２８を除く領域には、はんだ保護膜（ソルダーレジスト）３４が形成される。   The connection pad 28 has a cylindrical (thin disc) shape, and is formed on the outermost insulating layer 26 b on the opposite side to the connection pad 24. The solder bump 30 is soldered to the connection pad 28 to constitute a BGA terminal. The capacitor 32 is soldered to the connection pad 28. A solder protective film (solder resist) 34 is formed on the insulating layer 26b in a region excluding the connection pads 28.

一方、半導体チップ８は、バンプアレイを構成するはんだバンプ９を備える。図２は、半導体パッケージ１０のはんだバンプ９周辺を拡大して示す断面図である。同図に示されるように、半導体チップ８の底面には、はんだバンプ９に加わる衝撃を吸収するために、クッション膜１３が形成される。また、はんだバンプ９の下（はんだバンプ９と半導体チップ８の底面との間）には、チタン、クロム、銅などのバンプ下地金属１１がメッキされ、敷設される。   On the other hand, the semiconductor chip 8 includes solder bumps 9 constituting a bump array. FIG. 2 is an enlarged cross-sectional view showing the periphery of the solder bump 9 of the semiconductor package 10. As shown in the figure, a cushion film 13 is formed on the bottom surface of the semiconductor chip 8 in order to absorb the impact applied to the solder bumps 9. Further, under the solder bump 9 (between the solder bump 9 and the bottom surface of the semiconductor chip 8), a bump base metal 11 such as titanium, chromium, or copper is plated and laid.

接続パッド２４上にあらかじめ付着されたはんだ１２を溶融し、はんだバンプ９を接続パッド２４にはんだ付けする。これにより、半導体チップ８はコアレス基板２０に実装される。また、図１に示されるように、半導体チップ８とコアレス基板２０との間にはアンダーフィル樹脂３５が充填される。   The solder 12 previously deposited on the connection pad 24 is melted, and the solder bump 9 is soldered to the connection pad 24. Thereby, the semiconductor chip 8 is mounted on the coreless substrate 20. As shown in FIG. 1, an underfill resin 35 is filled between the semiconductor chip 8 and the coreless substrate 20.

ここで、図１４に示した従来の接続パッド５が円柱状であるのに対し、この接続パッド２４は縁のある帽子(hat)状である。より具体的には、接続パッド２４は、プレート部３６と、コンタクト部３８とからなる。プレート部３６は円柱（薄い円板）状をなし、その直径φ１は従来の接続パッド５の直径φ１と同じ約９５μｍであり、その厚みは約１０μｍである。コンタクト部３８は円柱（薄い円板）状をなし、その直径φｃはプレート部３６の直径φ１よりも小さく、かつ、バンプ下地金属１１の直径φ２とほぼ等しい約７５μｍであり、その厚みは約２０μｍである。コンタクト部３８は、プレート部３６の表側に位置する。コンタクト部３８の主面３９は、絶縁層２６ａの主面７で露出する。コンタクト部３８の主面３９と絶縁層２６ａの主面７とは同一平面上にある。また、プレート部３６及びコンタクト部３８は同軸にかつ一体的に形成される。そのため、接続パッド２４は、帽子の縁にあたる鍔部４０を有する。鍔部４０は、幅が約１０μｍのリング状をなす。ビア４は、プレート部３６の裏側と接触する。   Here, the conventional connection pad 5 shown in FIG. 14 has a cylindrical shape, whereas the connection pad 24 has a hat-like shape with an edge. More specifically, the connection pad 24 includes a plate portion 36 and a contact portion 38. The plate portion 36 has a cylindrical (thin disc) shape, and its diameter φ1 is about 95 μm, which is the same as the diameter φ1 of the conventional connection pad 5, and its thickness is about 10 μm. The contact portion 38 has a cylindrical (thin disc) shape, and its diameter φc is smaller than the diameter φ1 of the plate portion 36 and is approximately 75 μm, which is substantially equal to the diameter φ2 of the bump base metal 11, and its thickness is approximately 20 μm. It is. The contact portion 38 is located on the front side of the plate portion 36. The main surface 39 of the contact portion 38 is exposed at the main surface 7 of the insulating layer 26a. The main surface 39 of the contact portion 38 and the main surface 7 of the insulating layer 26a are on the same plane. The plate portion 36 and the contact portion 38 are formed coaxially and integrally. Therefore, the connection pad 24 has the collar part 40 which hits the edge of a hat. The collar portion 40 has a ring shape with a width of about 10 μm. The via 4 is in contact with the back side of the plate portion 36.

この実施の形態によれば、コンタクト部３８の直径φｃがバンプ下地金属１１の直径φ２とほぼ等しいため、半導体チップ８をコアレス基板２０から引き剥がす方向に機械的な応力が加わっても、その応力は接続パッド２４及びバンプ下地金属１１の両側に均等に分散し、破断が起こりにくい。しかも、接続パッド２４の直径全体を小さくしているのではなく、コンタクト部３８の直径φｃだけを小さくし、プレート部３６の直径φ１を小さくせず、約９５μｍのまま維持しているため、ビア４の直径や位置の製造公差を考慮しても、ビア４の位置が接続パッド２４の位置から大きくずれることはなく、ビア４と接続パッド２４とを確実に接続することができる。一方、バンプ下地金属１１の直径φ２を大きくせず、約７５μｍのまま維持しているため、メッキをパターン化してバンプ下地金属１１を形成するに際して、歩留まりが低下することもない。   According to this embodiment, since the diameter φc of the contact portion 38 is substantially equal to the diameter φ2 of the bump base metal 11, even if mechanical stress is applied in the direction of peeling the semiconductor chip 8 from the coreless substrate 20, the stress Are evenly distributed on both sides of the connection pad 24 and the bump base metal 11 and are not easily broken. In addition, since the entire diameter of the connection pad 24 is not reduced, only the diameter φc of the contact portion 38 is reduced, and the diameter φ1 of the plate portion 36 is not reduced, and is maintained at about 95 μm. Even if the manufacturing tolerance of the diameter and the position of 4 is taken into consideration, the position of the via 4 does not greatly deviate from the position of the connection pad 24, and the via 4 and the connection pad 24 can be reliably connected. On the other hand, since the diameter φ2 of the bump base metal 11 is not increased and is maintained at about 75 μm, the yield is not lowered when the bump base metal 11 is formed by patterning the plating.

また、接続パッド２４には鍔部４０があるため、半導体チップ８をコアレス基板２０から引き剥がす方向に機械的な応力が加わっても、鍔部４０が絶縁層２６ａに引っ掛かり、接続パッド２４は破壊されにくい。また、コンタクト部３８の主面３９と絶縁層２６ａの主面７とは同一平面上にあり、コアレス基板２０全体の主面が平面であるため、アンダーフィル樹脂３５は均一速度で半導体チップ８とコアレス基板２０との間に流れ込む。   Further, since the connection pad 24 has the flange portion 40, even if mechanical stress is applied in the direction in which the semiconductor chip 8 is peeled off from the coreless substrate 20, the flange portion 40 is caught by the insulating layer 26 a and the connection pad 24 is destroyed. It is hard to be done. In addition, since the main surface 39 of the contact portion 38 and the main surface 7 of the insulating layer 26a are on the same plane, and the main surface of the entire coreless substrate 20 is a flat surface, the underfill resin 35 is in contact with the semiconductor chip 8 at a uniform speed. It flows between the coreless substrate 20.

次に、複数の絶縁層２６を有する上記コアレス基板２０の製造方法の一例を説明する。ビルトアップ層２２は、図１上で下方向に形成される。具体的には次の通り。   Next, an example of a method for manufacturing the coreless substrate 20 having the plurality of insulating layers 26 will be described. The built-up layer 22 is formed downward in FIG. Specifically:

まず図３に示すように、銅板からなる母材４２を用意し、母材４２の上にネガ系のレジストフィルム４４を塗布する。   First, as shown in FIG. 3, a base material 42 made of a copper plate is prepared, and a negative resist film 44 is applied on the base material 42.

次に図４に示すように、フォトリソグラフィ法を用いて、所定パターンを有するマスク４６でレジストフィルム４４を覆い、所定時間露光する。レジストフィルム４４のうちマスク４６の遮光部４８で遮光された部分には光は照射されないが、それ以外の部分には光が照射される。遮光部４８は円形をなし、その直径は約７５μｍである。   Next, as shown in FIG. 4, the resist film 44 is covered with a mask 46 having a predetermined pattern by using a photolithography method and exposed for a predetermined time. In the resist film 44, light is not irradiated on a portion shielded by the light shielding portion 48 of the mask 46, but light is irradiated on the other portions. The light shielding part 48 is circular and has a diameter of about 75 μm.

次に図５に示すように、レジストフィルム４４を現像しかつ洗浄すると、光が照射されなかった部分だけが除去され、レジスト溝である貫通孔５０が形成され、光が照射された部分５２だけが残る。これにより、レジストフィルム４４がパターン化される。   Next, as shown in FIG. 5, when the resist film 44 is developed and washed, only the portion that has not been irradiated with light is removed, the through hole 50 that is a resist groove is formed, and only the portion 52 that has been irradiated with light. Remains. Thereby, the resist film 44 is patterned.

次に、図３及び図４に示した工程とほぼ同じ工程を繰り返す。すなわち図６に示すように、パターン化されたレジストフィルム４４の上に同じ材質のレジストフィルム５４を貼付する。そして、上記マスク４６と異なるパターンを有するマスク５６でレジストフィルム５４を覆い、所定時間露光する。レジストフィルム５４のうちマスク５６の遮光部５８で遮光された部分には光は照射されないが、それ以外の部分には光が照射される。遮光部５８は円形をなし、その直径は約９５μｍである。この工程では、遮光部５８の中心が貫通孔５０の中心（図４に示した工程で遮光部４８の中心のあった位置）にほぼ一致するように、マスク５６は位置決めされる。   Next, substantially the same steps as those shown in FIGS. 3 and 4 are repeated. That is, as shown in FIG. 6, a resist film 54 of the same material is stuck on the patterned resist film 44. Then, the resist film 54 is covered with a mask 56 having a pattern different from the mask 46 and exposed for a predetermined time. In the resist film 54, light is not irradiated to a portion shielded by the light shielding portion 58 of the mask 56, but light is irradiated to other portions. The light shielding portion 58 is circular and has a diameter of about 95 μm. In this step, the mask 56 is positioned so that the center of the light shielding portion 58 substantially coincides with the center of the through hole 50 (the position where the center of the light shielding portion 48 was located in the step shown in FIG. 4).

次に図７に示すように、レジストフィルム５４を現像しかつ洗浄すると、光が照射されなかった部分だけが除去され、レジスト溝である貫通孔６０が形成され、光が照射された部分６２だけが残る。これにより、レジストフィルム５４がパターン化される。その結果、円柱状の貫通孔５０の上に円柱状の貫通孔６０が形成される。   Next, as shown in FIG. 7, when the resist film 54 is developed and washed, only the portion that has not been irradiated with light is removed, the through hole 60 that is a resist groove is formed, and only the portion 62 that has been irradiated with light. Remains. Thereby, the resist film 54 is patterned. As a result, a cylindrical through hole 60 is formed on the cylindrical through hole 50.

次に図８に示すように、母材４２上の貫通孔５０内に金等のバリアメタル６４をメッキし、さらにバリアメタル上の貫通孔５０及び６０内に銅等の金属６６をメッキする。バリアメタル６４は、後に母材４２をエッチングで除去する工程でエッチングストッパとして機能する。   Next, as shown in FIG. 8, a barrier metal 64 such as gold is plated in the through hole 50 on the base material 42, and a metal 66 such as copper is plated in the through holes 50 and 60 on the barrier metal. The barrier metal 64 functions as an etching stopper in a process of removing the base material 42 by etching later.

次に図９に示すように、レジストフィルム４４及び５４を従来の剥離プロセスを用いて剥離する。これにより、上述したプレート部３６及びコンタクト部３８からなる帽子状の接続パッド２４が形成される。   Next, as shown in FIG. 9, the resist films 44 and 54 are stripped using a conventional stripping process. Thereby, the cap-shaped connection pad 24 including the plate portion 36 and the contact portion 38 is formed.

次に図１０に示すように、絶縁フィルム６８をラミネートする。この工程は真空中で行われるので、絶縁フィルム６８は鍔部４０の下にまで潜り込む。これにより、上述した絶縁層２６ａ（絶縁フィルム６８）が形成される。   Next, as shown in FIG. 10, an insulating film 68 is laminated. Since this process is performed in a vacuum, the insulating film 68 sinks to the bottom of the flange 40. Thereby, the insulating layer 26a (insulating film 68) described above is formed.

次に図１１に示すように、プレート部３６の真上にある絶縁フィルム６８（絶縁層２６ａ）にレーザを用いてビア孔７０を形成する。   Next, as shown in FIG. 11, a via hole 70 is formed in the insulating film 68 (insulating layer 26 a) just above the plate portion 36 using a laser.

次に図１２に示すように、ビア孔７０が形成された絶縁フィルム６８上に銅等の金属７２をメッキしてパターン化する。これにより、ビア孔７０内に充填された金属７２は上述したビア４となり、ビア孔７０及び絶縁フィルム６８上でパターン化された金属７２は上述したランド３を構成する。このランド３は、次に形成される絶縁層の配線層に接続される。   Next, as shown in FIG. 12, a metal 72 such as copper is plated on the insulating film 68 in which the via hole 70 is formed, and is patterned. Thus, the metal 72 filled in the via hole 70 becomes the above-described via 4, and the metal 72 patterned on the via hole 70 and the insulating film 68 constitutes the above-described land 3. The land 3 is connected to a wiring layer of an insulating layer to be formed next.

同様に、絶縁フィルムのラミネート、レーザによるビア孔の形成及び金属のメッキを繰り返すことにより、複数の絶縁層２６を形成して図１に示したビルトアップ層２２を形成する。ビルトアップ層２２を形成する工程自体は周知である。   Similarly, a plurality of insulating layers 26 are formed by repeating lamination of insulating films, formation of via holes by laser, and plating of metal to form the built-up layer 22 shown in FIG. The process itself for forming the built-up layer 22 is well known.

最後に図１３に示すように、エッチングにより銅の母材４２を除去する。このとき、金等のバリアメタル６４はエッチングされないので、銅等の金属６６までエッチングされることはない。そのため、コンタクト部３８の主面３９と絶縁層２６ａの主面とは同一平面上に形成される。   Finally, as shown in FIG. 13, the copper base material 42 is removed by etching. At this time, since the barrier metal 64 such as gold is not etched, the metal 66 such as copper is not etched. Therefore, the main surface 39 of the contact portion 38 and the main surface of the insulating layer 26a are formed on the same plane.

この製造方法によれば、帽子状の接続パッド２４を備えたコアレス基板２０を容易に製造することができる。   According to this manufacturing method, the coreless substrate 20 provided with the cap-shaped connection pad 24 can be easily manufactured.

上述した寸法はあくまで例示であり、これに限定されるものではない。たとえばコンタクト部３８の直径は半導体チップ８のバンプ下地金属１１の直径と全く同じでなくてもよく、７０〜８０μｍくらいでもよい。たとえばコンタクト部３８の面積とバンプ下地金属１１の面積がほぼ等しくなるようにしてもよい。また、プレート部３６の直径は９０〜１００μｍくらいでもよく、また、９５μｍよりもかなり大きくてもよい。   The dimensions described above are merely examples, and the present invention is not limited to these. For example, the diameter of the contact portion 38 may not be exactly the same as the diameter of the bump base metal 11 of the semiconductor chip 8 and may be about 70 to 80 μm. For example, the area of the contact portion 38 and the area of the bump base metal 11 may be substantially equal. The diameter of the plate portion 36 may be about 90 to 100 μm, and may be considerably larger than 95 μm.

また、上記実施の形態の接続パッド２４では、円板状のプレート部３６の中心と円板状のコンタクト部３８の中心とが一致しているが、完全に一致している必要はなく、多少ずれていてもよい。また、プレート部３６とコンタクト部３８という２つの独立した部材で接続パッド２４が構成されている必要はなく、全体として鍔のある帽子状であればよい。また、プレート部３６及びコンタクト部３８の平面形状は円形であるが、これに限定されることなく、楕円形や多角形などであってもよい。   Further, in the connection pad 24 of the above embodiment, the center of the disk-shaped plate portion 36 and the center of the disk-shaped contact portion 38 are coincident with each other. It may be shifted. Further, the connection pad 24 does not need to be configured by two independent members, that is, the plate portion 36 and the contact portion 38, and may be a hat-like shape having a collar as a whole. The planar shape of the plate portion 36 and the contact portion 38 is circular, but is not limited to this, and may be an ellipse or a polygon.

また、上記実施の形態による製造方法ではバリアメタル６４を母材４２上に形成しているが、バリアメタル６４を省略し、銅等の金属６６を母材４２上に直接形成してもよい。   In the manufacturing method according to the above embodiment, the barrier metal 64 is formed on the base material 42. However, the barrier metal 64 may be omitted and the metal 66 such as copper may be directly formed on the base material 42.

また、上記実施の形態はコアレス基板２０であるが、本発明はこれに限定されることなく、コア基板を有する一般的なプリント配線板にも適用可能である。   Moreover, although the said embodiment is the coreless board | substrate 20, this invention is not limited to this, It is applicable also to the general printed wiring board which has a core board | substrate.

以上、本発明の実施の形態を説明したが、上述した実施の形態は本発明を実施するための例示に過ぎない。よって、本発明は上述した実施の形態に限定されることなく、その趣旨を逸脱しない範囲内で上述した実施の形態を適宜変形して実施することが可能である。   While the embodiments of the present invention have been described above, the above-described embodiments are merely examples for carrying out the present invention. Therefore, the present invention is not limited to the above-described embodiment, and can be implemented by appropriately modifying the above-described embodiment without departing from the spirit thereof.

本発明の実施の形態による半導体パッケージの全体構成示す断面図である。It is sectional drawing which shows the whole structure of the semiconductor package by embodiment of this invention. 図１に示した半導体パッケージにおけるコアレス基板の接続パッド周辺を拡大して示す断面図である。FIG. 2 is an enlarged cross-sectional view showing the periphery of a connection pad of a coreless substrate in the semiconductor package shown in FIG. 1. 図１に示したコアレス基板の製造方法を示す最初の工程を示す断面図である。It is sectional drawing which shows the first process which shows the manufacturing method of the coreless board | substrate shown in FIG. 図３に示した工程の次の工程を示す断面図である。FIG. 4 is a cross-sectional view showing a step subsequent to the step shown in FIG. 3. 図４に示した工程の次の工程を示す断面図である。FIG. 5 is a cross-sectional view showing a step subsequent to the step shown in FIG. 4. 図５に示した工程の次の工程を示す断面図である。FIG. 6 is a cross-sectional view showing a step subsequent to the step shown in FIG. 5. 図６に示した工程の次の工程を示す断面図である。FIG. 7 is a cross-sectional view showing a step subsequent to the step shown in FIG. 6. 図７に示した工程の次の工程を示す断面図である。FIG. 8 is a cross-sectional view showing a step subsequent to the step shown in FIG. 7. 図８に示した工程の次の工程を示す断面図である。FIG. 9 is a cross-sectional view showing a step subsequent to the step shown in FIG. 8. 図９に示した工程の次の工程を示す断面図である。FIG. 10 is a cross-sectional view showing a step subsequent to the step shown in FIG. 9. 図１０に示した工程の次の工程を示す断面図である。FIG. 11 is a cross-sectional view showing a step subsequent to the step shown in FIG. 10. 図１１に示した工程の次の工程を示す断面図である。FIG. 12 is a cross-sectional view showing a step subsequent to the step shown in FIG. 11. 図１２に示した工程の次の工程を示す断面図である。FIG. 13 is a cross-sectional view showing a step subsequent to the step shown in FIG. 12. 従来の半導体パッケージにおけるコアレス基板の接続パッド周辺を拡大して示す断面図である。It is sectional drawing which expands and shows the connection pad periphery of the coreless board | substrate in the conventional semiconductor package.

３ ランド
４ ビア
７，３９ 主面
８ 半導体チップ
９ はんだバンプ
１０ 半導体パッケージ
１１ バンプ下地金属
１３ クッション膜
２０ コアレス基板
２２ ビルトアップ層
２４ 接続パッド
２６，２６ａ，２６ｂ 絶縁層
３６ プレート部
３８ コンタクト部
４０ 鍔部
４２ 母材
４４，５４ レジストフィルム
４６，５６ マスク
４８，５８ 遮光部
５０，６０ 貫通孔
５６ マスク
６６，７２ 金属
６８ 絶縁フィルム
７０ ビア孔 3 Land 4 Via 7, 39 Main surface 8 Semiconductor chip 9 Solder bump 10 Semiconductor package 11 Bump base metal 13 Cushion film 20 Coreless substrate 22 Built-up layer 24 Connection pad 26, 26a, 26b Insulating layer 36 Plate portion 38 Contact portion 40 Part 42 Base material 44, 54 Resist film 46, 56 Mask 48, 58 Light shielding part 50, 60 Through hole 56 Mask 66, 72 Metal 68 Insulating film 70 Via hole

Claims (3)

母材を用意する工程と、
第１の貫通孔を有する第１の膜を前記母材上に形成する工程と、
前記第１の貫通孔上に位置しかつ前記第１の貫通孔よりも大きい第２の貫通孔を有する第２の膜を前記第１の膜上に形成する工程と、
前記第１及び第２の貫通孔内に金属を充填して接続パッドを形成する工程と、
前記接続パッドの形成後、前記第１及び第２の膜を除去する工程と、
前記母材及び前記接続パッドを覆うように絶縁層を形成する工程と、
前記絶縁層の形成後、前記母材を除去する工程とを含む、プリント配線板の製造方法。 Preparing a base material;
Forming a first film having a first through hole on the base material;
Forming a second film on the first film, the second film being located on the first through-hole and having a second through-hole larger than the first through-hole;
Filling the first and second through holes with metal to form connection pads;
Removing the first and second films after forming the connection pads;
Forming an insulating layer so as to cover the base material and the connection pads;
And a step of removing the base material after forming the insulating layer. 請求項１に記載のプリント配線板の製造方法であってさらに、
前記絶縁層の形成後、前記母材の除去前に、前記第１の絶縁層に前記接続パッドまで貫通するビア穴を形成する工程と、
前記ビア穴内に金属を充填してビアを形成する工程とを含む、プリント配線板の製造方法。 The printed wiring board manufacturing method according to claim 1, further comprising:
Forming a via hole penetrating to the connection pad in the first insulating layer after forming the insulating layer and before removing the base material;
Forming a via by filling a metal in the via hole. 請求項１に記載のプリント配線板の製造方法であって、
前記第１の膜を形成する工程は、
前記母材上に第１のレジストフィルムを形成する工程と、
フォトリソグラフィ法により前記第１のレジストフィルムに前記第１の貫通孔を形成する工程とを含み、
前記第２の膜を形成する工程は、
前記第１の貫通孔が形成された第１のレジストフィルム上に第２のレジストフィルムを形成する工程と、
フォトリソグラフィ法により前記第２のレジストフィルムに前記第２の貫通孔を形成する工程とを含む、プリント配線板の製造方法。
It is a manufacturing method of the printed wiring board according to claim 1,
The step of forming the first film includes
Forming a first resist film on the base material;
Forming the first through hole in the first resist film by a photolithography method,
The step of forming the second film includes
Forming a second resist film on the first resist film in which the first through hole is formed;
Forming the second through hole in the second resist film by a photolithography method.
JP2011050952A 2011-03-09 2011-03-09 Method for manufacturing printed wiring board Expired - Fee Related JP5273749B2 (en)

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